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Simple PCIe FMC carrier SPEC
Commit 204ff681 authored by Federico Vaga's avatar Federico Vaga
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Merge branch 'release/v1.4.0'

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*.o
*.ko
*.mod.c
.*.o.cmd
.*.ko.cmd
*.mod.d
*.o.d
*.tmp
.tmp_versions
modules.order
Module.symvers
\#*
*~
GTAGS
GPATH
GRTAGS
Makefile.specific
\ No newline at end of file
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[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
CHANGELOG 0 → 100644
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# Changelog
## [1.4.0] 2019-09-11
### Added
- [hdl] spec-base IP-core to support SPEC based designs
- [sw] Driver for GN4124 FCL using Linux FPGA manager
- [sw] Driver for GN4124 GPIO using Linux GPIOlib
- [sw] Driver for gn412x-core DMA using Linux DMA engine
- [sw] Support for spec-base IP-core
- [sw] Support for FMC
## [x.x.x] 2012-12-14
### Changed
- HDL: GN412x-CORE upgrade
## [x.x.x] 2012-12-14
### Added
- HDL: golden bitstream
## [0.0.0]
Start the development
LICENSES/GPL-2.0.txt 0 → 100644
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GNU GENERAL PUBLIC LICENSE
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spec-fmc-carrier
Copyright (C) 2019 CERN (https://home.cern)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
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Manifest.py 0 → 100644
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modules = { "local" : [ "hdl/rtl" ] }
if action == "synthesis":
modules["local"].append("hdl/syn/common")
README.rst 0 → 100644
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==============================
Simple PCIe FMC Carrier - SPEC
==============================
This git repository contains the HDL code necessary to enable most of
the SPEC features and the correspondent Linux driver.
distribution/Makefile 0 → 100644
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TOP_DIR ?= $(shell pwd)/../
HDL_DIR ?= $(TOP_DIR)/hdl
DRIVER_NAME := spec-fmc-carrier
VERSION := $(shell git describe --abbrev=0)
DIR_NAME := $(DRIVER_NAME)-$(VERSION)
KEEP_TEMP ?= n
BUILD ?= $(abspath build)
BUILD_DKMS := $(BUILD)/dkms
BUILD_DKMSSOURCE := $(BUILD_DKMS)/source
BUILD_DKMSTREE := $(BUILD_DKMS)/tree
DKMS_OPT := --dkmstree $(BUILD_DKMSTREE) -m $(DRIVER_NAME)/$(VERSION)
all: kernel
CHEBY ?= /usr/bin/cheby
spec-core-fpga.h:
$(CHEBY) --gen-c -i $(HDL_DIR)/rtl/spec_base_regs.cheby > /tmp/$@
kernel: dkms-tar dkms-rpm
dkms-tree:
@mkdir -p $(BUILD_DKMSSOURCE)
@mkdir -p $(BUILD_DKMSTREE)
dkms-src: dkms-tree spec-core-fpga.h
$(eval $@_src := $(shell git ls-tree -r --name-only HEAD $(TOP_DIR) | grep "kernel" | tr '\n' ' '))
$(eval $@_dir := $(BUILD_DKMSSOURCE)/$(DRIVER_NAME)-$(VERSION))
@mkdir -p $($@_dir)/platform_data
@mv /tmp/spec-core-fpga.h $($@_dir)
@cp -a $($@_src) $(TOP_DIR)/distribution/dkms.conf $($@_dir)
@mv $($@_dir)/gn412x-gpio.h $($@_dir)/platform_data
@cp -a $(TOP_DIR)/LICENSES/GPL-2.0.txt $($@_dir)/LICENSE
@sed -r -i -e "s/^VERSION\s=\s.*/VERSION = $(VERSION)/" $($@_dir)/Makefile
@sed -r -i -e "s/@PKGNAME@/$(DRIVER_NAME)/" $($@_dir)/dkms.conf
@sed -r -i -e "s/@PKGVER@/$(VERSION)/" $($@_dir)/dkms.conf
dkms-add: dkms-src
@dkms add $(DKMS_OPT) --sourcetree $(BUILD_DKMSSOURCE)
dkms-tar: dkms-add
@dkms mktarball $(DKMS_OPT) --source-only
dkms-rpm: dkms-add
@dkms mkrpm $(DKMS_OPT) --source-only
clean:
@rm -rf $(BUILD)
.PHONY: dkmstree dkms-add kernel-dkms-tar
distribution/dkms.conf 0 → 100644
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PACKAGE_NAME="@PKGNAME@"
PACKAGE_VERSION="@PKGVER@"
CLEAN="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 clean"
MAKE[0]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
MAKE[1]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
MAKE[2]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
MAKE[3]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
BUILT_MODULE_NAME[0]="@PKGNAME@"
BUILT_MODULE_NAME[1]="gn412x-gpio"
BUILT_MODULE_NAME[2]="gn412x-fcl"
BUILT_MODULE_NAME[3]="spec-gn412x-dma"
DEST_MODULE_LOCATION[0]="/updates"
DEST_MODULE_LOCATION[1]="/updates"
DEST_MODULE_LOCATION[2]="/updates"
DEST_MODULE_LOCATION[3]="/updates"
BUILD_DEPENDS[0]="fmc"
BUILD_DEPENDS[1]="fpga_mgr"
BUILD_DEPENDS[2]="i2c-ocores"
AUTOINSTALL="yes"
doc/Makefile 0 → 100644
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# Minimal makefile for Sphinx documentation
#
# You can set these variables from the command line.
SPHINXOPTS =
SPHINXBUILD = sphinx-build
SOURCEDIR = .
BUILDDIR = _build
# Put it first so that "make" without argument is like "make help".
help:
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: help Makefile
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
\ No newline at end of file
doc/conf.py 0 → 100644
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# -*- coding: utf-8 -*-
#
# Configuration file for the Sphinx documentation builder.
#
# This file does only contain a selection of the most common options. For a
# full list see the documentation:
# http://www.sphinx-doc.org/en/master/config
# -- Path setup --------------------------------------------------------------
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
#
# import os
# import sys
# sys.path.insert(0, os.path.abspath('.'))
# -- Project information -----------------------------------------------------
project = 'SPEC'
copyright = '2019, Federico Vaga <federico.vaga@cern.ch>, Tristan Gingold <tristan.gingold@cern.ch>, Dimitris Lampridis <dimitrios.lampridis@cern.ch>'
author = 'Federico Vaga <federico.vaga@cern.ch>, Tristan Gingold <tristan.gingold@cern.ch>, Dimitris Lampridis <dimitrios.lampridis@cern.ch>'
# The short X.Y version
version = ''
# The full version, including alpha/beta/rc tags
release = 'v1.4'
# -- General configuration ---------------------------------------------------
# If your documentation needs a minimal Sphinx version, state it here.
#
# needs_sphinx = '1.0'
# Add any Sphinx extension module names here, as strings. They can be
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
extensions = [
]
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
# The suffix(es) of source filenames.
# You can specify multiple suffix as a list of string:
#
# source_suffix = ['.rst', '.md']
source_suffix = '.rst'
# The master toctree document.
master_doc = 'index'
# The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages.
#
# This is also used if you do content translation via gettext catalogs.
# Usually you set "language" from the command line for these cases.
language = None
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
# This pattern also affects html_static_path and html_extra_path.
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
# The name of the Pygments (syntax highlighting) style to use.
pygments_style = None
# -- Options for HTML output -------------------------------------------------
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#
html_theme = 'alabaster'
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the
# documentation.
#
# html_theme_options = {}
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
html_static_path = ['_static']
# Custom sidebar templates, must be a dictionary that maps document names
# to template names.
#
# The default sidebars (for documents that don't match any pattern) are
# defined by theme itself. Builtin themes are using these templates by
# default: ``['localtoc.html', 'relations.html', 'sourcelink.html',
# 'searchbox.html']``.
#
# html_sidebars = {}
# -- Options for HTMLHelp output ---------------------------------------------
# Output file base name for HTML help builder.
htmlhelp_basename = 'SPECdoc'
# -- Options for LaTeX output ------------------------------------------------
latex_elements = {
# The paper size ('letterpaper' or 'a4paper').
#
# 'papersize': 'letterpaper',
# The font size ('10pt', '11pt' or '12pt').
#
# 'pointsize': '10pt',
# Additional stuff for the LaTeX preamble.
#
# 'preamble': '',
# Latex figure (float) alignment
#
# 'figure_align': 'htbp',
}
# Grouping the document tree into LaTeX files. List of tuples
# (source start file, target name, title,
# author, documentclass [howto, manual, or own class]).
latex_documents = [
(master_doc, 'SPEC.tex', 'SPEC Documentation',
'Federico Vaga \\textless{}federico.vaga@cern.ch\\textgreater{}, Tristan Gingold \\textless{}tristan.gingold@cern.ch\\textgreater{}, Dimitris Lampridis \\textless{}dimitrios.lampridis@cern.ch\\textgreater{}', 'manual'),
]
# -- Options for manual page output ------------------------------------------
# One entry per manual page. List of tuples
# (source start file, name, description, authors, manual section).
man_pages = [
(master_doc, 'spec', 'SPEC Documentation',
[author], 1)
]
# -- Options for Texinfo output ----------------------------------------------
# Grouping the document tree into Texinfo files. List of tuples
# (source start file, target name, title, author,
# dir menu entry, description, category)
texinfo_documents = [
(master_doc, 'SPEC', 'SPEC Documentation',
author, 'SPEC', 'One line description of project.',
'Miscellaneous'),
]
# -- Options for Epub output -------------------------------------------------
# Bibliographic Dublin Core info.
epub_title = project
# The unique identifier of the text. This can be a ISBN number
# or the project homepage.
#
# epub_identifier = ''
# A unique identification for the text.
#
# epub_uid = ''
# A list of files that should not be packed into the epub file.
epub_exclude_files = ['search.html']
doc/hdl-spec-base.rst 0 → 100644
View file @ 204ff681
.. _spec_hdl_spec_base:
SPEC Base HDL Component
=======================
The ``SPEC base`` HDL component provides the basic support for the SPEC card
and it strongly recommended for any SPEC based application. The VHDL code for
this component is part of the `SPEC project`_ source code as well as the
necessary Linux drivers.
Interface Rules
---------------
The ``SPEC base`` is an :ref:`FPGA device <device-structure>` that contains
all the necessary logic to use the SPEC carrier's features.
Rule
The ``SPEC base`` design must follow the FPGA design guide lines
Rule
The ``SPEC base`` instance must be present in any SPEC based
design.
Rule
The ``SPEC base`` metadata table must contain the following
constant values
========== ========== ================== ============
Offset Size (bit) Name Default (LE)
0x00000000 32 Vendor ID 0x000010DC
0x00000004 32 Device ID 0x53504543
0x00000008 32 Version <variable>
0x0000000C 32 Byte Order Mark 0xFFFE0000
0x00000010 128 Source ID <variable>
0x00000020 32 Capability Mask <variable>
0x00000030 128 Vendor UUID 0x00000000
========== ========== ================== ============
Observation
The ``SPEC base`` typically is instantiated in a *top level* design
next to an ``Application Device``.
Rule
The ``SPEC base`` must have a 32bit register containing the offset
to the ``Application Device``. If there is no application, then the content
of this register must be ``0x00000000``.
Observation
The ``Application Device`` offset is design specific and it must be
declared in the ``Application Access`` register
Version 1.4
~~~~~~~~~~~
Rule
The ``SPEC base`` metadata table must contain the following
constant values for this version.
========== ========== ================== ============
Offset Size (bit) Name Default (LE)
0x00000000 32 Vendor ID 0x000010DC
0x00000004 32 Device ID 0x53504543
0x00000008 32 Version 0x0104xxxx
0x0000000C 32 Byte Order Mark 0xFFFE0000
0x00000010 128 Source ID <variable>
0x00000020 32 Capability Mask 0x0000000x
0x00000030 128 Vendor UUID 0x00000000
========== ========== ================== ============
Rule
The ``SPEC base`` is made of the following components
=================== ============ ========== =============
Component Start End Cap. Mask Bit
CSR 0x00000040 0x0000005F (Mandatory)
Therm. & ID 0x00000070 0x0000007F 1
Gen-Core I2C Ocore 0x00000080 0x0000009F (Mandatory)
Gen-Core SPI 0x000000A0 0x000000BF 2
DMA for DDR 0x000000C0 0x000000FF 5
Gen-Core VIC 0x00000100 0x000001FF 0
Build info 0x00000200 0x000002FF 4
White-Rabbit 0x00001000 0x00001FFF 3
=================== ============ ========== =============
Observation
The capability mask value ``0x1F`` means that all optional components
are instantiated.
Rule
The ``SPEC base`` must connect the VIC IRQ output to the ``GPIO 8`` on
the GN4124 chip
Observation
The GN4124 ``GPIO 9`` can be used for interrupts by the application.
Rule
The ``SPEC base`` reserves the first 6 interrupt lines of
the internal interrupt controller (``VIC``) for the following purposes:
============== ===================
Interrupt Line Component
0 Gen-Core I2C Ocore
1 Gen-Core SPI
2 Gen-Core Gennum DMA DONE
3 (reserved)
4 (reserved)
5 (reserved)
============== ===================
.. _`SPEC project`: https://ohwr.org/project/spec
doc/index.rst 0 → 100644
View file @ 204ff681
================================
Welcome to SPEC's documentation!
================================
The Simple PCIe FMC Carrier (SPEC) is a 4 lane PCIe card that has an
FPGA and can hold one FMC module and one SFP connector.
Its bridge to the PCIe bus is the Gennum GN4124 chip and its purpose
is to create a bridge between the PCIe bus and the FPGA. With the
exception of the M25P32 FLASH memory, all components are connected to
the FPGA. This implies that an FPGA configuration is necessary to
fully use the card.
The `SPEC project`_ is hosted on the `Open HardWare Repository`_
.. toctree::
:maxdepth: 2
:caption: Contents:
hdl-spec-base
sw-driver
Indices and tables
==================
* :ref:`genindex`
* :ref:`modindex`
* :ref:`search`
.. _`Open HardWare Repository`: https://ohwr.org/
.. _`SPEC project`: https://ohwr.org/project/spec
doc/sw-driver.rst 0 → 100644
View file @ 204ff681
SPEC Driver(s)
==============
There are drivers for the GN4124 chip and there are drivers for the
:ref:`SPEC base<spec_hdl_spec_base>` component. All these drivers are
managed by:
SPEC FMC Carrier
This is the driver that wrap up all the physical components and the
:ref:`SPEC base<spec_hdl_spec_base>` ones. It configures the card so
that all components cooperate correctly.
The driver for the GN4124 chip are always present and distributed as
part of the SPEC driver. They must work no matter what FPGA design has
been loaded on FPGA.
GN4124 GPIO
This driver provides support for the GN4124 GPIOs. It uses the standard
Linux `GPIO interface`_ and it export a dedicated IRQ domain.
Gn4124 FCL
This driver provides support for the GN4124 FCL (FPGA Configuration Loader).
It uses the `FPGA manager interface`_ to program the FPGA at runtime.
If the SPEC based application is using the :ref:`SPEC
base<spec_hdl_spec_base>` component then it can profit from the
following driver. They are not all mandatory, it depends on the
application, and most of them are distributed separately:
SPEC GN412x DMA
This driver provides for DMA transfers to/from the SPEC DDR. It uses
the standard Linux `DMA Engine`_. It is part of the `SPEC project`_
I2C OCORE
This is the driver for the I2C OCORE IP-core. It is used to communicate with
the standard FMC EEPROM available what on FMC modules. The driver is
available in Linux.
SPI OCORE
This is the driver for the SPI OCORE IP-core. It is used to communicate with
the M25P32 FLASH memory where FPGA bitstreams are stored. The driver is
distributed separately.
VIC
The driver for the VIC interrupt controller IP-core. The driver is
distributed separately.
.. _`SPEC project`: https://ohwr.org/project/spec
.. _`GPIO interface`: https://www.kernel.org/doc/html/latest/driver-api/gpio/index.html
.. _`FPGA manager interface`: https://www.kernel.org/doc/html/latest/driver-api/fpga/index.html
.. _`DMA Engine`: https://www.kernel.org/doc/html/latest/driver-api/dmaengine/index.html~
hdl/golden/Manifest.py deleted 100644 → 0
View file @ a465c3cc
fetchto = "ip_cores"
modules = { "local" : [ "top", "platform" ] }
hdl/golden/platform/Manifest.py deleted 100644 → 0
View file @ a465c3cc
modules = {"local" : "xilinx"}
hdl/golden/platform/xilinx/Manifest.py deleted 100644 → 0
View file @ a465c3cc
files = [ "wr_xilinx_pkg.vhd" ]
modules = {"local" : ["wr_gtp_phy", "chipscope"]}
\ No newline at end of file
hdl/golden/platform/xilinx/chipscope/Manifest.py deleted 100644 → 0
View file @ a465c3cc
files =["chipscope_icon.ngc", "chipscope_ila.ngc" ]
hdl/golden/platform/xilinx/chipscope/chipscope_icon.ngc deleted 100644 → 0
View file @ a465c3cc
XILINX-XDB 0.1 STUB 0.1 ASCII
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\ No newline at end of file
hdl/golden/platform/xilinx/chipscope/chipscope_ila.ngc deleted 100644 → 0
View file @ a465c3cc
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/golden/platform/xilinx/wr_gtp_phy/Manifest.py deleted 100644 → 0
View file @ a465c3cc
files = ["gtp_bitslide.vhd",
"gtp_phase_align.vhd",
"gtp_phase_align_virtex6.vhd",
"gtx_reset.vhd",
"whiterabbitgtx_wrapper_gtx.vhd",
# "whiterabbitgtp_wrapper.vhd",
"whiterabbitgtp_wrapper_tile.vhd",
"wr_gtp_phy_spartan6.vhd",
"wr_gtx_phy_virtex6.vhd"];
hdl/golden/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd deleted 100644 → 0
View file @ a465c3cc
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - bitslide state machine
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_bitslide.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Module implements a manual bitslide alignment state machine and
-- provides the obtained bitslide value to the MAC.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-- 2011-09-12 0.6 twlostow Virtex6 port
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_bitslide is
generic (
-- set to non-zero value to enable some simulation speedups (reduce delays)
g_simulation : integer;
g_target : string := "spartan6");
port (
gtp_rst_i : in std_logic;
-- GTP
gtp_rx_clk_i : in std_logic;
-- '1' indicates that the GTP has detected a comma in the incoming serial stream
gtp_rx_comma_det_i : in std_logic;
gtp_rx_byte_is_aligned_i : in std_logic;
-- GTP ready flag (PLL locked and RX signal present)
serdes_ready_i : in std_logic;
-- GTP manual bitslip control line
gtp_rx_slide_o : out std_logic;
-- GTP CDR reset, asserted when the link is lost to set the bitslide to a known
-- value
gtp_rx_cdr_rst_o : out std_logic;
-- Current bitslide, in UIs
bitslide_o : out std_logic_vector(4 downto 0);
-- '1' when the bitsliding has been completed and the link is up
synced_o : out std_logic
);
end gtp_bitslide;
architecture behavioral of gtp_bitslide is
function f_eval_sync_detect_threshold
return integer is
begin
if(g_simulation /= 0) then
return 256;
elsif(g_target = "spartan6") then
return 8192;
else
return 16384;
end if;
end f_eval_sync_detect_threshold;
function f_eval_pause_tics return integer is
begin
if(g_target = "spartan6") then
return 31;
else
return 63;
end if;
end f_eval_pause_tics;
constant c_pause_tics : integer := f_eval_pause_tics;
constant c_sync_detect_threshold : integer := f_eval_sync_detect_threshold;
type t_bitslide_fsm_state is (S_SYNC_LOST, S_STABILIZE, S_SLIDE, S_PAUSE, S_GOT_SYNC, S_RESET_CDR);
signal cur_slide : unsigned(4 downto 0);
signal state : t_bitslide_fsm_state;
signal counter : unsigned(15 downto 0);
signal commas_missed : unsigned(1 downto 0);
begin -- behavioral
p_do_slide : process(gtp_rx_clk_i, gtp_rst_i)
begin
if gtp_rst_i = '1' then
state <= S_SYNC_LOST;
gtp_rx_slide_o <= '0';
counter <= (others => '0');
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
elsif rising_edge(gtp_rx_clk_i) then
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
case state is
-- State: synchronization lost. Waits until a comma pattern is detected
when S_SYNC_LOST =>
cur_slide <= (others => '0');
counter <= (others => '0');
gtp_rx_slide_o <= '0';
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
commas_missed <= (others => '0');
if(gtp_rx_comma_det_i = '1') then
state <= S_STABILIZE;
end if;
-- State: stabilize:
when S_STABILIZE =>
if(gtp_rx_comma_det_i = '1') then
counter <= counter + 1;
commas_missed <= (others => '0');
else
commas_missed <= commas_missed + 1;
if(commas_missed(1) = '1') then
state <= S_SYNC_LOST;
end if;
end if;
if(counter = to_unsigned(c_sync_detect_threshold, counter'length)) then
counter <= (others => '0');
state <= S_PAUSE;
end if;
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
when S_SLIDE =>
cur_slide <= cur_slide + 1;
gtp_rx_slide_o <= '1';
counter <= (others => '0');
state <= S_PAUSE;
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
when S_PAUSE =>
counter <= counter + 1;
gtp_rx_slide_o <= '0';
if(counter = to_unsigned(c_pause_tics, counter'length)) then
if(gtp_rx_byte_is_aligned_i = '0') then
state <= S_SLIDE;
else
state <= S_GOT_SYNC;
end if;
end if;
when S_GOT_SYNC =>
gtp_rx_slide_o <= '0';
bitslide_o <= std_logic_vector(cur_slide);
synced_o <= '1';
if(gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0') then
gtp_rx_cdr_rst_o <= '1';
state <= S_SYNC_LOST;
end if;
when others => null;
end case;
end if;
end process;
end behavioral;
hdl/golden/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd deleted 100644 → 0
View file @ a465c3cc
------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - TX phase alignment
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_phase_align.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: TX phase alignment state machine, as recommended by Xilinx.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_phase_align is
generic
(g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic
);
end gtp_phase_align;
architecture behavioral of gtp_phase_align is
constant c_wait_en_phase_align : integer := 32;
constant c_wait_set_phase_align : integer := 512;
constant c_phase_align_duration : integer := 8192;
type t_align_state is (S_ALIGN_IDLE, S_ALIGN_PAUSE, S_ALIGN_WAIT, S_ALIGN_SET_PHASE, S_ALIGN_DONE);
signal counter : unsigned(13 downto 0);
signal state : t_align_state;
begin -- behavioral
p_align : process(gtp_tx_clk_i, gtp_rst_i)
begin
if rising_edge(gtp_tx_clk_i) then
if gtp_rst_i = '1' then
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '0';
state <= S_ALIGN_IDLE;
else
if(align_en_i = '0') then
state <= S_ALIGN_IDLE;
else
case (state) is
when S_ALIGN_IDLE =>
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '0';
if(align_en_i = '1') then
state <= S_ALIGN_PAUSE;
end if;
when S_ALIGN_PAUSE =>
counter <= counter + 1;
if(counter = to_unsigned(c_wait_en_phase_align, counter'length)) then
state <= S_ALIGN_WAIT;
end if;
when S_ALIGN_WAIT =>
gtp_tx_en_pma_phase_align_o <= '1';
counter <= counter + 1;
if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align, counter'length)) then
state <= S_ALIGN_SET_PHASE;
end if;
when S_ALIGN_SET_PHASE =>
counter <= counter +1;
gtp_tx_pma_set_phase_o <= '1';
if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align + c_phase_align_duration, counter'length)) then
state <= S_ALIGN_DONE;
end if;
when S_ALIGN_DONE =>
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '1';
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
hdl/golden/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd deleted 100644 → 0
View file @ a465c3cc
------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - TX phase alignment
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_phase_align.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: TX phase alignment state machine, as recommended by Xilinx.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-- 2011-09-12 0.6 twlostow Virtex6 port
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_phase_align_virtex6 is
generic
(g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
gtp_tx_dly_align_disable_o : out std_logic;
gtp_tx_dly_align_reset_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic
);
end gtp_phase_align_virtex6;
architecture behavioral of gtp_phase_align_virtex6 is
constant c_dly_align_reset_time : integer := 16;
constant c_wait_set_phase_align : integer := 32;
constant c_phase_align_duration : integer := 8192;
type t_align_state is (S_ALIGN_IDLE, S_DLY_ALIGN_RESET, S_ALIGN_WAIT, S_ALIGN_SET_PHASE, S_ALIGN_DONE);
signal counter : unsigned(13 downto 0);
signal state : t_align_state;
begin -- behavioral
p_align : process(gtp_tx_clk_i, gtp_rst_i)
begin
if rising_edge(gtp_tx_clk_i) then
if gtp_rst_i = '1' then
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
counter <= (others => '0');
align_done_o <= '0';
state <= S_ALIGN_IDLE;
else
if(align_en_i = '0') then
state <= S_ALIGN_IDLE;
else
case (state) is
when S_ALIGN_IDLE =>
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
counter <= (others => '0');
align_done_o <= '0';
if(align_en_i = '1') then
state <= S_DLY_ALIGN_RESET;
end if;
when S_DLY_ALIGN_RESET =>
counter <= counter + 1;
gtp_tx_dly_align_reset_o <= '1';
gtp_tx_dly_align_disable_o <= '1';
if(counter = to_unsigned(c_dly_align_reset_time, counter'length)) then
state <= S_ALIGN_WAIT;
end if;
when S_ALIGN_WAIT =>
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
gtp_tx_en_pma_phase_align_o <= '1';
counter <= counter + 1;
if(counter = to_unsigned(c_dly_align_reset_time + c_wait_set_phase_align, counter'length)) then
state <= S_ALIGN_SET_PHASE;
end if;
when S_ALIGN_SET_PHASE =>
counter <= counter +1;
gtp_tx_pma_set_phase_o <= '1';
if(counter = to_unsigned(c_dly_align_reset_time + c_wait_set_phase_align + c_phase_align_duration, counter'length)) then
state <= S_ALIGN_DONE;
end if;
when S_ALIGN_DONE =>
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_disable_o <= '0';
counter <= (others => '0');
align_done_o <= '1';
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
hdl/golden/platform/xilinx/wr_gtp_phy/gtx_reset.vhd deleted 100644 → 0
View file @ a465c3cc
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtx_reset is
port (
clk_tx_i : in std_logic;
rst_i : in std_logic;
txpll_lockdet_i : in std_logic;
gtx_test_o : out std_logic_vector(12 downto 0)
);
end gtx_reset;
architecture behavioral of gtx_reset is
type t_state is (IDLE, PAUSE, FIRST_RST, PAUSE2, SECOND_RST, DONE);
signal state : t_state;
signal counter : unsigned(15 downto 0);
begin -- behavioral
process(clk_tx_i)
begin
if rising_edge(clk_tx_i) then
if rst_i = '1' then
state <= IDLE;
counter <= (others => '0');
else
if(txpll_lockdet_i = '0') then
state <= IDLE;
else
case state is
when IDLE =>
counter <= (others => '0');
gtx_test_o <= "1000000000000";
if(txpll_lockdet_i = '1') then
state <= PAUSE;
end if;
when PAUSE =>
counter <= counter + 1;
gtx_test_o <= "1000000000000";
if(counter = 1024) then
state <= FIRST_RST;
end if;
when FIRST_RST =>
counter <= counter + 1;
gtx_test_o <= "1000000000010";
if(counter = 1024 + 256) then
state <= PAUSE2;
end if;
when PAUSE2=>
counter <= counter + 1;
gtx_test_o <= "1000000000000";
if(counter = 1024 + 2*256) then
state <= SECOND_RST;
end if;
when SECOND_RST =>
counter <= counter + 1;
gtx_test_o <= "1000000000010";
if(counter = 1024 + 3*256) then
state <= DONE;
end if;
when DONE =>
gtx_test_o <= "1000000000000";
end case;
end if;
end if;
end if;
end process;
end behavioral;
hdl/golden/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd deleted 100644 → 0
View file @ a465c3cc
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.4
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : whiterabbitgtp_wrapper.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module WHITERABBITGTP_WRAPPER (a GTP Wrapper)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of,
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
--***************************** Entity Declaration ****************************
entity WHITERABBITGTP_WRAPPER is
generic
(
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
WRAPPER_CLK25_DIVIDER_0 : integer := 5;
WRAPPER_CLK25_DIVIDER_1 : integer := 5;
WRAPPER_PLL_DIVSEL_FB_0 : integer := 2;
WRAPPER_PLL_DIVSEL_FB_1 : integer := 2;
WRAPPER_PLL_DIVSEL_REF_0 : integer := 1;
WRAPPER_PLL_DIVSEL_REF_1 : integer := 1;
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X1_Y0)
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_LOOPBACK0_IN : in std_logic_vector(2 downto 0);
TILE0_LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN : in std_logic;
TILE0_CLK01_IN : in std_logic;
TILE0_GTPRESET0_IN : in std_logic;
TILE0_GTPRESET1_IN : in std_logic;
TILE0_PLLLKDET0_OUT : out std_logic;
TILE0_RESETDONE0_OUT : out std_logic;
TILE0_RESETDONE1_OUT : out std_logic;
TILE0_REFCLKOUT0_OUT : out std_logic;
TILE0_REFCLKOUT1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXCHARISK0_OUT : out std_logic;
TILE0_RXCHARISK1_OUT : out std_logic;
TILE0_RXDISPERR0_OUT : out std_logic;
TILE0_RXDISPERR1_OUT : out std_logic;
TILE0_RXNOTINTABLE0_OUT : out std_logic;
TILE0_RXNOTINTABLE1_OUT : out std_logic;
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXBYTEISALIGNED0_OUT : out std_logic;
TILE0_RXBYTEISALIGNED1_OUT : out std_logic;
TILE0_RXCOMMADET0_OUT : out std_logic;
TILE0_RXCOMMADET1_OUT : out std_logic;
TILE0_RXSLIDE0_IN : in std_logic;
TILE0_RXSLIDE1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT : out std_logic_vector(7 downto 0);
TILE0_RXDATA1_OUT : out std_logic_vector(7 downto 0);
TILE0_RXUSRCLK0_IN : in std_logic;
TILE0_RXUSRCLK1_IN : in std_logic;
TILE0_RXUSRCLK20_IN : in std_logic;
TILE0_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_RXCDRRESET0_IN : in std_logic;
TILE0_RXCDRRESET1_IN : in std_logic;
TILE0_RXN0_IN : in std_logic;
TILE0_RXN1_IN : in std_logic;
TILE0_RXP0_IN : in std_logic;
TILE0_RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARISK0_IN : in std_logic;
TILE0_TXCHARISK1_IN : in std_logic;
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TILE0_TXENPMAPHASEALIGN0_IN : in std_logic;
TILE0_TXENPMAPHASEALIGN1_IN : in std_logic;
TILE0_TXPMASETPHASE0_IN : in std_logic;
TILE0_TXPMASETPHASE1_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN : in std_logic_vector(7 downto 0);
TILE0_TXDATA1_IN : in std_logic_vector(7 downto 0);
TILE0_TXUSRCLK0_IN : in std_logic;
TILE0_TXUSRCLK1_IN : in std_logic;
TILE0_TXUSRCLK20_IN : in std_logic;
TILE0_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXN0_OUT : out std_logic;
TILE0_TXN1_OUT : out std_logic;
TILE0_TXP0_OUT : out std_logic;
TILE0_TXP1_OUT : out std_logic
);
end WHITERABBITGTP_WRAPPER;
architecture RTL of WHITERABBITGTP_WRAPPER is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of RTL : architecture is "WHITERABBITGTP_WRAPPER,s6_gtpwizard_v1_4,{gtp0_protocol_file=Start_from_scratch,gtp1_protocol_file=Use_GTP0_settings}";
--***************************** Signal Declarations *****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tile0_plllkdet0_i : std_logic;
signal tile0_plllkdet1_i : std_logic;
signal tile0_plllkdet0_i2 : std_logic;
--*************************** Component Declarations **************************
component WHITERABBITGTP_WRAPPER_TILE
generic
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 4;
TILE_CLK25_DIVIDER_1 : integer := 4;
TILE_PLL_DIVSEL_FB_0 : integer := 5;
TILE_PLL_DIVSEL_FB_1 : integer := 5;
TILE_PLL_DIVSEL_REF_0 : integer := 2;
TILE_PLL_DIVSEL_REF_1 : integer := 2;
--
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
REFCLKOUT0_OUT : out std_logic;
REFCLKOUT1_OUT : out std_logic;
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
RXDISPERR1_OUT : out std_logic;
RXNOTINTABLE0_OUT : out std_logic;
RXNOTINTABLE1_OUT : out std_logic;
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT : out std_logic;
RXBYTEISALIGNED1_OUT : out std_logic;
RXCOMMADET0_OUT : out std_logic;
RXCOMMADET1_OUT : out std_logic;
RXSLIDE0_IN : in std_logic;
RXSLIDE1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(7 downto 0);
RXDATA1_OUT : out std_logic_vector(7 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN : in std_logic;
RXCDRRESET1_IN : in std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN : in std_logic;
TXCHARISK1_IN : in std_logic;
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN : in std_logic;
TXENPMAPHASEALIGN1_IN : in std_logic;
TXPMASETPHASE0_IN : in std_logic;
TXPMASETPHASE1_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(7 downto 0);
TXDATA1_IN : in std_logic_vector(7 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic
);
end component;
--********************************* Main Body of Code**************************
begin
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
simulation : if WRAPPER_SIMULATION = 1 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i2;
process
begin
wait until tile0_plllkdet0_i'event;
if(tile0_plllkdet0_i = '1') then
tile0_plllkdet0_i2 <= '1' after 100 ns;
else
tile0_plllkdet0_i2 <= tile0_plllkdet0_i;
end if;
end process;
end generate simulation;
implementation : if WRAPPER_SIMULATION = 0 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i;
end generate implementation;
--------------------------- Tile Instances -------------------------------
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X1_Y0)
tile0_whiterabbitgtp_wrapper_i : WHITERABBITGTP_WRAPPER_TILE
generic map
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP => WRAPPER_SIM_GTPRESET_SPEEDUP,
TILE_CLK25_DIVIDER_0 => WRAPPER_CLK25_DIVIDER_0,
TILE_CLK25_DIVIDER_1 => WRAPPER_CLK25_DIVIDER_1,
TILE_PLL_DIVSEL_FB_0 => WRAPPER_PLL_DIVSEL_FB_0,
TILE_PLL_DIVSEL_FB_1 => WRAPPER_PLL_DIVSEL_FB_1,
TILE_PLL_DIVSEL_REF_0 => WRAPPER_PLL_DIVSEL_REF_0,
TILE_PLL_DIVSEL_REF_1 => WRAPPER_PLL_DIVSEL_REF_1,
--
TILE_PLL_SOURCE_0 => "PLL0",
TILE_PLL_SOURCE_1 => "PLL0"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN => TILE0_LOOPBACK0_IN,
LOOPBACK1_IN => TILE0_LOOPBACK1_IN,
--------------------------------- PLL Ports --------------------------------
REFCLKOUT1_OUT => REFCLKOUT1_OUT,
REFCLKOUT0_OUT => REFCLKOUT0_OUT,
CLK00_IN => TILE0_CLK00_IN,
CLK01_IN => TILE0_CLK01_IN,
GTPRESET0_IN => TILE0_GTPRESET0_IN,
GTPRESET1_IN => TILE0_GTPRESET1_IN,
PLLLKDET0_OUT => tile0_plllkdet0_i,
PLLLKDET1_OUT => tile0_plllkdet1_i,
RESETDONE0_OUT => TILE0_RESETDONE0_OUT,
RESETDONE1_OUT => TILE0_RESETDONE1_OUT,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT => TILE0_RXCHARISK0_OUT,
RXCHARISK1_OUT => TILE0_RXCHARISK1_OUT,
RXDISPERR0_OUT => TILE0_RXDISPERR0_OUT,
RXDISPERR1_OUT => TILE0_RXDISPERR1_OUT,
RXNOTINTABLE0_OUT => TILE0_RXNOTINTABLE0_OUT,
RXNOTINTABLE1_OUT => TILE0_RXNOTINTABLE1_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT => TILE0_RXBYTEISALIGNED0_OUT,
RXBYTEISALIGNED1_OUT => TILE0_RXBYTEISALIGNED1_OUT,
RXCOMMADET0_OUT => TILE0_RXCOMMADET0_OUT,
RXCOMMADET1_OUT => TILE0_RXCOMMADET1_OUT,
RXSLIDE0_IN => TILE0_RXSLIDE0_IN,
RXSLIDE1_IN => TILE0_RXSLIDE1_IN,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT => TILE0_RXDATA0_OUT,
RXDATA1_OUT => TILE0_RXDATA1_OUT,
RXUSRCLK0_IN => TILE0_RXUSRCLK0_IN,
RXUSRCLK1_IN => TILE0_RXUSRCLK1_IN,
RXUSRCLK20_IN => TILE0_RXUSRCLK20_IN,
RXUSRCLK21_IN => TILE0_RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN => TILE0_RXCDRRESET0_IN,
RXCDRRESET1_IN => TILE0_RXCDRRESET1_IN,
RXN0_IN => TILE0_RXN0_IN,
RXN1_IN => TILE0_RXN1_IN,
RXP0_IN => TILE0_RXP0_IN,
RXP1_IN => TILE0_RXP1_IN,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT => TILE0_GTPCLKFBEAST_OUT,
GTPCLKFBWEST_OUT => TILE0_GTPCLKFBWEST_OUT,
GTPCLKOUT0_OUT => TILE0_GTPCLKOUT0_OUT,
GTPCLKOUT1_OUT => TILE0_GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN => TILE0_TXCHARISK0_IN,
TXCHARISK1_IN => TILE0_TXCHARISK1_IN,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN => TILE0_TXENPMAPHASEALIGN0_IN,
TXENPMAPHASEALIGN1_IN => TILE0_TXENPMAPHASEALIGN1_IN,
TXPMASETPHASE0_IN => TILE0_TXPMASETPHASE0_IN,
TXPMASETPHASE1_IN => TILE0_TXPMASETPHASE1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN => TILE0_TXDATA0_IN,
TXDATA1_IN => TILE0_TXDATA1_IN,
TXUSRCLK0_IN => TILE0_TXUSRCLK0_IN,
TXUSRCLK1_IN => TILE0_TXUSRCLK1_IN,
TXUSRCLK20_IN => TILE0_TXUSRCLK20_IN,
TXUSRCLK21_IN => TILE0_TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT => TILE0_TXN0_OUT,
TXN1_OUT => TILE0_TXN1_OUT,
TXP0_OUT => TILE0_TXP0_OUT,
TXP1_OUT => TILE0_TXP1_OUT
);
end RTL;
hdl/golden/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd deleted 100644 → 0
View file @ a465c3cc
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
--***************************** Entity Declaration ****************************
entity WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
generic
(
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 4;
TILE_CLK25_DIVIDER_1 : integer := 4;
TILE_PLL_DIVSEL_FB_0 : integer := 5;
TILE_PLL_DIVSEL_FB_1 : integer := 5;
TILE_PLL_DIVSEL_REF_0 : integer := 2;
TILE_PLL_DIVSEL_REF_1 : integer := 2;
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
REFCLKOUT0_OUT : out std_logic;
REFCLKOUT1_OUT : out std_logic;
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
CLK10_IN : in std_logic;
CLK11_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
RXDISPERR1_OUT : out std_logic;
RXNOTINTABLE0_OUT : out std_logic;
RXNOTINTABLE1_OUT : out std_logic;
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT : out std_logic;
RXBYTEISALIGNED1_OUT : out std_logic;
RXCOMMADET0_OUT : out std_logic;
RXCOMMADET1_OUT : out std_logic;
RXSLIDE0_IN : in std_logic;
RXSLIDE1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(7 downto 0);
RXDATA1_OUT : out std_logic_vector(7 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN : in std_logic;
RXCDRRESET1_IN : in std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN : in std_logic;
TXCHARISK1_IN : in std_logic;
TXCHARDISPMODE0_IN: in std_logic;
TXCHARDISPMODE1_IN: in std_logic;
TXCHARDISPVAL0_IN: in std_logic;
TXCHARDISPVAL1_IN: in std_logic;
TXRUNDISP0_OUT : out std_logic_vector(3 downto 0);
TXRUNDISP1_OUT : out std_logic_vector(3 downto 0);
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN : in std_logic;
TXENPMAPHASEALIGN1_IN : in std_logic;
TXPMASETPHASE0_IN : in std_logic;
TXPMASETPHASE1_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(7 downto 0);
TXDATA1_IN : in std_logic_vector(7 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic
);
end WHITERABBITGTP_WRAPPER_TILE_SPARTAN6;
architecture RTL of WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
-- RX Datapath signals
signal rxdata0_i : std_logic_vector(31 downto 0);
signal rxchariscomma0_float_i : std_logic_vector(2 downto 0);
signal rxcharisk0_float_i : std_logic_vector(2 downto 0);
signal rxdisperr0_float_i : std_logic_vector(2 downto 0);
signal rxnotintable0_float_i : std_logic_vector(2 downto 0);
signal rxrundisp0_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata0_i : std_logic_vector(31 downto 0);
signal txkerr0_float_i : std_logic_vector(2 downto 0);
signal txrundisp0_float_i : std_logic_vector(2 downto 0);
-- RX Datapath signals
signal rxdata1_i : std_logic_vector(31 downto 0);
signal rxchariscomma1_float_i : std_logic_vector(2 downto 0);
signal rxcharisk1_float_i : std_logic_vector(2 downto 0);
signal rxdisperr1_float_i : std_logic_vector(2 downto 0);
signal rxnotintable1_float_i : std_logic_vector(2 downto 0);
signal rxrundisp1_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata1_i : std_logic_vector(31 downto 0);
signal txkerr1_float_i : std_logic_vector(2 downto 0);
signal txrundisp1_float_i : std_logic_vector(2 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
------------------- GTP Datapath byte mapping -----------------
RXDATA0_OUT <= rxdata0_i(7 downto 0);
txdata0_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA0_IN);
RXDATA1_OUT <= rxdata1_i(7 downto 0);
txdata1_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA1_IN);
----------------------------- GTPA1_DUAL Instance --------------------------
gtpa1_dual_i : GTPA1_DUAL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (true),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_REFCLK0_SOURCE => ("000"),
SIM_REFCLK1_SOURCE => ("000"),
SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP),
CLK25_DIVIDER_0 => (TILE_CLK25_DIVIDER_0),
CLK25_DIVIDER_1 => (TILE_CLK25_DIVIDER_1),
PLL_DIVSEL_FB_0 => (TILE_PLL_DIVSEL_FB_0),
PLL_DIVSEL_FB_1 => (TILE_PLL_DIVSEL_FB_1),
PLL_DIVSEL_REF_0 => (TILE_PLL_DIVSEL_REF_0),
PLL_DIVSEL_REF_1 => (TILE_PLL_DIVSEL_REF_1),
--PLL Attributes
CLKINDC_B_0 => (true),
CLKRCV_TRST_0 => (true),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (2),
PLL_SATA_0 => (false),
PLL_SOURCE_0 => (TILE_PLL_SOURCE_0),
PLL_TXDIVSEL_OUT_0 => (2),
PLLLKDET_CFG_0 => ("111"),
--
CLKINDC_B_1 => (true),
CLKRCV_TRST_1 => (true),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (2),
PLL_SATA_1 => (false),
PLL_SOURCE_1 => (TILE_PLL_SOURCE_1),
PLL_TXDIVSEL_OUT_1 => (2),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"000008000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
TX_TDCC_CFG_0 => ("00"),
CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
TX_TDCC_CFG_1 => ("00"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"80082"),
TX_BUFFER_USE_0 => (false),
TX_XCLK_SEL_0 => ("TXUSR"),
TXRX_INVERT_0 => ("111"),
PMA_TX_CFG_1 => (x"80082"),
TX_BUFFER_USE_1 => (false),
TX_XCLK_SEL_1 => ("TXUSR"),
TXRX_INVERT_1 => ("111"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("011"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("011"),
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (true),
OOBDETECT_THRESHOLD_0 => ("110"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce048"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (false),
RCV_TERM_VTTRX_0 => (true),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (false),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (true),
OOBDETECT_THRESHOLD_1 => ("110"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce048"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (false),
RCV_TERM_VTTRX_1 => (true),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (false),
TX_DETECT_RX_CFG_1 => (x"1832"),
--PRBS Detection Attributes
RXPRBSERR_LOOPBACK_0 => ('0'),
RXPRBSERR_LOOPBACK_1 => ('0'),
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => ("1111111111"),
DEC_MCOMMA_DETECT_0 => (false),
DEC_PCOMMA_DETECT_0 => (false),
DEC_VALID_COMMA_ONLY_0 => (true),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (true),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (true),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => ("1111111111"),
DEC_MCOMMA_DETECT_1 => (false),
DEC_PCOMMA_DETECT_1 => (false),
DEC_VALID_COMMA_ONLY_1 => (true),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (true),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (true),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (false),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (false),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (true),
RX_EN_IDLE_RESET_BUF_0 => (true),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (true),
RX_EN_IDLE_RESET_BUF_1 => (true),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (false),
CLK_COR_KEEP_IDLE_0 => (false),
CLK_COR_MAX_LAT_0 => (18),
CLK_COR_MIN_LAT_0 => (16),
CLK_COR_PRECEDENCE_0 => (true),
CLK_COR_REPEAT_WAIT_0 => (0),
CLK_COR_SEQ_1_1_0 => ("0100000000"),
CLK_COR_SEQ_1_2_0 => ("0000000000"),
CLK_COR_SEQ_1_3_0 => ("0000000000"),
CLK_COR_SEQ_1_4_0 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_1_0 => ("0100000000"),
CLK_COR_SEQ_2_2_0 => ("0000000000"),
CLK_COR_SEQ_2_3_0 => ("0000000000"),
CLK_COR_SEQ_2_4_0 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_USE_0 => (false),
CLK_CORRECT_USE_0 => (false),
RX_DECODE_SEQ_MATCH_0 => (true),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (false),
CLK_COR_KEEP_IDLE_1 => (false),
CLK_COR_MAX_LAT_1 => (18),
CLK_COR_MIN_LAT_1 => (16),
CLK_COR_PRECEDENCE_1 => (true),
CLK_COR_REPEAT_WAIT_1 => (0),
CLK_COR_SEQ_1_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2_1 => ("0000000000"),
CLK_COR_SEQ_1_3_1 => ("0000000000"),
CLK_COR_SEQ_1_4_1 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_1_1 => ("0100000000"),
CLK_COR_SEQ_2_2_1 => ("0000000000"),
CLK_COR_SEQ_2_3_1 => ("0000000000"),
CLK_COR_SEQ_2_4_1 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_USE_1 => (false),
CLK_CORRECT_USE_1 => (false),
RX_DECODE_SEQ_MATCH_1 => (true),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (false),
CHAN_BOND_SEQ_1_1_0 => ("0000000000"),
CHAN_BOND_SEQ_1_2_0 => ("0000000000"),
CHAN_BOND_SEQ_1_3_0 => ("0000000000"),
CHAN_BOND_SEQ_1_4_0 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0000000000"),
CHAN_BOND_SEQ_2_2_0 => ("0000000000"),
CHAN_BOND_SEQ_2_3_0 => ("0000000000"),
CHAN_BOND_SEQ_2_4_0 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (false),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (true),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (false),
CHAN_BOND_SEQ_1_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2_1 => ("0000000000"),
CHAN_BOND_SEQ_1_3_1 => ("0000000000"),
CHAN_BOND_SEQ_1_4_1 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_3_1 => ("0000000000"),
CHAN_BOND_SEQ_2_4_1 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (false),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (true),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (false),
RX_EN_IDLE_HOLD_CDR_0 => (false),
RX_EN_IDLE_RESET_FR_0 => (true),
RX_EN_IDLE_RESET_PH_0 => (true),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (false),
RX_EN_IDLE_HOLD_CDR_1 => (false),
RX_EN_IDLE_RESET_FR_1 => (true),
RX_EN_IDLE_RESET_PH_1 => (true),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (9),
SATA_MAX_INIT_0 => (27),
SATA_MAX_WAKE_0 => (9),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (15),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (9),
SATA_MAX_INIT_1 => (27),
SATA_MAX_WAKE_1 => (9),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (15),
SATA_MIN_WAKE_1 => (5)
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => LOOPBACK0_IN,
LOOPBACK1 => LOOPBACK1_IN,
RXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
RXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
--------------------------------- PLL Ports --------------------------------
CLK00 => CLK00_IN,
CLK01 => CLK01_IN,
CLK10 => CLK10_IN,
CLK11 => CLK11_IN,
CLKINEAST0 => tied_to_ground_i,
CLKINEAST1 => tied_to_ground_i,
CLKINWEST0 => tied_to_ground_i,
CLKINWEST1 => tied_to_ground_i,
GCLK00 => tied_to_ground_i,
GCLK01 => tied_to_ground_i,
GCLK10 => tied_to_ground_i,
GCLK11 => tied_to_ground_i,
GTPRESET0 => GTPRESET0_IN,
GTPRESET1 => GTPRESET1_IN,
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => tied_to_vcc_i,
INTDATAWIDTH1 => tied_to_vcc_i,
PLLCLK00 => tied_to_ground_i,
PLLCLK01 => tied_to_ground_i,
PLLCLK10 => tied_to_ground_i,
PLLCLK11 => tied_to_ground_i,
PLLLKDET0 => PLLLKDET0_OUT,
PLLLKDET1 => PLLLKDET1_OUT,
PLLLKDETEN0 => tied_to_vcc_i,
PLLLKDETEN1 => tied_to_vcc_i,
PLLPOWERDOWN0 => tied_to_ground_i,
PLLPOWERDOWN1 => tied_to_ground_i,
REFCLKOUT0 => REFCLKOUT0_OUT,
REFCLKOUT1 => REFCLKOUT1_OUT,
REFCLKPLL0 => open,
REFCLKPLL1 => open,
REFCLKPWRDNB0 => tied_to_vcc_i,
REFCLKPWRDNB1 => tied_to_vcc_i,
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
RESETDONE0 => RESETDONE0_OUT,
RESETDONE1 => RESETDONE1_OUT,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN0 => tied_to_ground_vec_i(11 downto 0),
TSTIN1 => tied_to_ground_vec_i(11 downto 0),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0(3 downto 1) => rxcharisk0_float_i,
RXCHARISK0(0) => RXCHARISK0_OUT,
RXCHARISK1(3 downto 1) => rxcharisk1_float_i,
RXCHARISK1(0) => RXCHARISK1_OUT,
RXDEC8B10BUSE0 => tied_to_vcc_i,
RXDEC8B10BUSE1 => tied_to_vcc_i,
RXDISPERR0(3 downto 1) => rxdisperr0_float_i,
RXDISPERR0(0) => RXDISPERR0_OUT,
RXDISPERR1(3 downto 1) => rxdisperr1_float_i,
RXDISPERR1(0) => RXDISPERR1_OUT,
RXNOTINTABLE0(3 downto 1) => rxnotintable0_float_i,
RXNOTINTABLE0(0) => RXNOTINTABLE0_OUT,
RXNOTINTABLE1(3 downto 1) => rxnotintable1_float_i,
RXNOTINTABLE1(0) => RXNOTINTABLE1_OUT,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
USRCODEERR0 => tied_to_ground_i,
USRCODEERR1 => tied_to_ground_i,
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER0 => tied_to_ground_i,
RXCHBONDMASTER1 => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE0 => tied_to_ground_i,
RXCHBONDSLAVE1 => tied_to_ground_i,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => RXBYTEISALIGNED0_OUT,
RXBYTEISALIGNED1 => RXBYTEISALIGNED1_OUT,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => RXCOMMADET0_OUT,
RXCOMMADET1 => RXCOMMADET1_OUT,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => tied_to_ground_i,
RXENMCOMMAALIGN1 => tied_to_ground_i,
RXENPCOMMAALIGN0 => tied_to_ground_i,
RXENPCOMMAALIGN1 => tied_to_ground_i,
RXSLIDE0 => RXSLIDE0_IN,
RXSLIDE1 => RXSLIDE1_IN,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i,
RXDATA1 => rxdata1_i,
RXDATAWIDTH0 => "00",
RXDATAWIDTH1 => "00",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => tied_to_ground_i,
RXRESET1 => tied_to_ground_i,
RXUSRCLK0 => RXUSRCLK0_IN,
RXUSRCLK1 => RXUSRCLK1_IN,
RXUSRCLK20 => RXUSRCLK20_IN,
RXUSRCLK21 => RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => tied_to_ground_i,
GATERXELECIDLE1 => tied_to_ground_i,
IGNORESIGDET0 => tied_to_ground_i,
IGNORESIGDET1 => tied_to_ground_i,
RCALINEAST => tied_to_ground_vec_i(4 downto 0),
RCALINWEST => tied_to_ground_vec_i(4 downto 0),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => RXCDRRESET0_IN,
RXCDRRESET1 => RXCDRRESET1_IN,
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXEQMIX0 => "00",
RXEQMIX1 => "00",
RXN0 => RXN0_IN,
RXN1 => RXN1_IN,
RXP0 => RXP0_IN,
RXP1 => RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXENPMAPHASEALIGN0 => tied_to_ground_i,
RXENPMAPHASEALIGN1 => tied_to_ground_i,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => tied_to_ground_i,
RXPOLARITY1 => tied_to_ground_i,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => GTPCLKFBEAST_OUT,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => GTPCLKFBWEST_OUT,
GTPCLKOUT0 => GTPCLKOUT0_OUT,
GTPCLKOUT1 => GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE0(0) => TXCHARDISPMODE0_IN,
TXCHARDISPMODE0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPMODE1(0) => TXCHARDISPMODE1_IN,
TXCHARDISPMODE1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPVAL0(0) => TXCHARDISPVAL0_IN,
TXCHARDISPVAL0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPVAL1(0) => TXCHARDISPVAL1_IN,
TXCHARDISPVAL1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK0(0) => TXCHARISK0_IN,
TXCHARISK1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK1(0) => TXCHARISK1_IN,
TXENC8B10BUSE0 => tied_to_vcc_i,
TXENC8B10BUSE1 => tied_to_vcc_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => TXRUNDISP0_OUT,
TXRUNDISP1 => TXRUNDISP1_OUT,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
TXENPMAPHASEALIGN0 => TXENPMAPHASEALIGN0_IN,
TXENPMAPHASEALIGN1 => TXENPMAPHASEALIGN1_IN,
TXPMASETPHASE0 => TXPMASETPHASE0_IN,
TXPMASETPHASE1 => TXPMASETPHASE1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i,
TXDATA1 => txdata1_i,
TXDATAWIDTH0 => "00",
TXDATAWIDTH1 => "00",
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => tied_to_ground_i,
TXRESET1 => tied_to_ground_i,
TXUSRCLK0 => TXUSRCLK0_IN,
TXUSRCLK1 => TXUSRCLK1_IN,
TXUSRCLK20 => TXUSRCLK20_IN,
TXUSRCLK21 => TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => "0110",
TXDIFFCTRL1 => "0110",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => TXN0_OUT,
TXN1 => TXN1_OUT,
TXP0 => TXP0_OUT,
TXP1 => TXP1_OUT,
TXPREEMPHASIS0 => "000",
TXPREEMPHASIS1 => "000",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR0 => tied_to_ground_i,
TXPRBSFORCEERR1 => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => tied_to_ground_i,
TXDETECTRX1 => tied_to_ground_i,
TXELECIDLE0 => tied_to_ground_i,
TXELECIDLE1 => tied_to_ground_i,
TXPDOWNASYNCH0 => tied_to_ground_i,
TXPDOWNASYNCH1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end RTL;
hdl/golden/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd deleted 100644 → 0
View file @ a465c3cc
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity WHITERABBITGTP_WRAPPER_TILE is
generic
(
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 4;
TILE_CLK25_DIVIDER_1 : integer := 4;
TILE_PLL_DIVSEL_FB_0 : integer := 5;
TILE_PLL_DIVSEL_FB_1 : integer := 5;
TILE_PLL_DIVSEL_REF_0 : integer := 2;
TILE_PLL_DIVSEL_REF_1 : integer := 2;
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
CLK10_IN : in std_logic;
CLK11_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
RXDISPERR1_OUT : out std_logic;
RXNOTINTABLE0_OUT : out std_logic;
RXNOTINTABLE1_OUT : out std_logic;
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT : out std_logic;
RXBYTEISALIGNED1_OUT : out std_logic;
RXCOMMADET0_OUT : out std_logic;
RXCOMMADET1_OUT : out std_logic;
RXSLIDE0_IN : in std_logic;
RXSLIDE1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(7 downto 0);
RXDATA1_OUT : out std_logic_vector(7 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN : in std_logic;
RXCDRRESET1_IN : in std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN : in std_logic;
TXCHARISK1_IN : in std_logic;
TXRUNDISP0_OUT : out std_logic_vector(3 downto 0);
TXRUNDISP1_OUT : out std_logic_vector(3 downto 0);
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN : in std_logic;
TXENPMAPHASEALIGN1_IN : in std_logic;
TXPMASETPHASE0_IN : in std_logic;
TXPMASETPHASE1_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(7 downto 0);
TXDATA1_IN : in std_logic_vector(7 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic
);
end WHITERABBITGTP_WRAPPER_TILE;
architecture RTL of WHITERABBITGTP_WRAPPER_TILE is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
-- RX Datapath signals
signal rxdata0_i : std_logic_vector(31 downto 0);
signal rxchariscomma0_float_i : std_logic_vector(2 downto 0);
signal rxcharisk0_float_i : std_logic_vector(2 downto 0);
signal rxdisperr0_float_i : std_logic_vector(2 downto 0);
signal rxnotintable0_float_i : std_logic_vector(2 downto 0);
signal rxrundisp0_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata0_i : std_logic_vector(31 downto 0);
signal txkerr0_float_i : std_logic_vector(2 downto 0);
signal txrundisp0_float_i : std_logic_vector(2 downto 0);
-- RX Datapath signals
signal rxdata1_i : std_logic_vector(31 downto 0);
signal rxchariscomma1_float_i : std_logic_vector(2 downto 0);
signal rxcharisk1_float_i : std_logic_vector(2 downto 0);
signal rxdisperr1_float_i : std_logic_vector(2 downto 0);
signal rxnotintable1_float_i : std_logic_vector(2 downto 0);
signal rxrundisp1_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata1_i : std_logic_vector(31 downto 0);
signal txkerr1_float_i : std_logic_vector(2 downto 0);
signal txrundisp1_float_i : std_logic_vector(2 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
------------------- GTP Datapath byte mapping -----------------
RXDATA0_OUT <= rxdata0_i(7 downto 0);
txdata0_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA0_IN);
RXDATA1_OUT <= rxdata1_i(7 downto 0);
txdata1_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA1_IN);
----------------------------- GTPA1_DUAL Instance --------------------------
gtpa1_dual_i : GTPA1_DUAL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (true),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_REFCLK0_SOURCE => ("000"),
SIM_REFCLK1_SOURCE => ("000"),
SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP),
CLK25_DIVIDER_0 => (TILE_CLK25_DIVIDER_0),
CLK25_DIVIDER_1 => (TILE_CLK25_DIVIDER_1),
PLL_DIVSEL_FB_0 => (TILE_PLL_DIVSEL_FB_0),
PLL_DIVSEL_FB_1 => (TILE_PLL_DIVSEL_FB_1),
PLL_DIVSEL_REF_0 => (TILE_PLL_DIVSEL_REF_0),
PLL_DIVSEL_REF_1 => (TILE_PLL_DIVSEL_REF_1),
--PLL Attributes
CLKINDC_B_0 => (true),
CLKRCV_TRST_0 => (true),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (2),
PLL_SATA_0 => (false),
PLL_SOURCE_0 => (TILE_PLL_SOURCE_0),
PLL_TXDIVSEL_OUT_0 => (2),
PLLLKDET_CFG_0 => ("111"),
--
CLKINDC_B_1 => (true),
CLKRCV_TRST_1 => (true),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (2),
PLL_SATA_1 => (false),
PLL_SOURCE_1 => (TILE_PLL_SOURCE_1),
PLL_TXDIVSEL_OUT_1 => (2),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"000008000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
TX_TDCC_CFG_0 => ("00"),
CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
TX_TDCC_CFG_1 => ("00"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"80082"),
TX_BUFFER_USE_0 => (false),
TX_XCLK_SEL_0 => ("TXUSR"),
TXRX_INVERT_0 => ("111"),
PMA_TX_CFG_1 => (x"80082"),
TX_BUFFER_USE_1 => (false),
TX_XCLK_SEL_1 => ("TXUSR"),
TXRX_INVERT_1 => ("111"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("011"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("011"),
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (true),
OOBDETECT_THRESHOLD_0 => ("110"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce048"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (false),
RCV_TERM_VTTRX_0 => (true),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (false),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (true),
OOBDETECT_THRESHOLD_1 => ("110"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce048"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (false),
RCV_TERM_VTTRX_1 => (true),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (false),
TX_DETECT_RX_CFG_1 => (x"1832"),
--PRBS Detection Attributes
RXPRBSERR_LOOPBACK_0 => ('0'),
RXPRBSERR_LOOPBACK_1 => ('0'),
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => ("1111111111"),
DEC_MCOMMA_DETECT_0 => (false),
DEC_PCOMMA_DETECT_0 => (false),
DEC_VALID_COMMA_ONLY_0 => (true),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (true),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (true),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => ("1111111111"),
DEC_MCOMMA_DETECT_1 => (false),
DEC_PCOMMA_DETECT_1 => (false),
DEC_VALID_COMMA_ONLY_1 => (true),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (true),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (true),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (false),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (false),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (true),
RX_EN_IDLE_RESET_BUF_0 => (true),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (true),
RX_EN_IDLE_RESET_BUF_1 => (true),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (false),
CLK_COR_KEEP_IDLE_0 => (false),
CLK_COR_MAX_LAT_0 => (18),
CLK_COR_MIN_LAT_0 => (16),
CLK_COR_PRECEDENCE_0 => (true),
CLK_COR_REPEAT_WAIT_0 => (0),
CLK_COR_SEQ_1_1_0 => ("0100000000"),
CLK_COR_SEQ_1_2_0 => ("0000000000"),
CLK_COR_SEQ_1_3_0 => ("0000000000"),
CLK_COR_SEQ_1_4_0 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_1_0 => ("0100000000"),
CLK_COR_SEQ_2_2_0 => ("0000000000"),
CLK_COR_SEQ_2_3_0 => ("0000000000"),
CLK_COR_SEQ_2_4_0 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_USE_0 => (false),
CLK_CORRECT_USE_0 => (false),
RX_DECODE_SEQ_MATCH_0 => (true),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (false),
CLK_COR_KEEP_IDLE_1 => (false),
CLK_COR_MAX_LAT_1 => (18),
CLK_COR_MIN_LAT_1 => (16),
CLK_COR_PRECEDENCE_1 => (true),
CLK_COR_REPEAT_WAIT_1 => (0),
CLK_COR_SEQ_1_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2_1 => ("0000000000"),
CLK_COR_SEQ_1_3_1 => ("0000000000"),
CLK_COR_SEQ_1_4_1 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_1_1 => ("0100000000"),
CLK_COR_SEQ_2_2_1 => ("0000000000"),
CLK_COR_SEQ_2_3_1 => ("0000000000"),
CLK_COR_SEQ_2_4_1 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_USE_1 => (false),
CLK_CORRECT_USE_1 => (false),
RX_DECODE_SEQ_MATCH_1 => (true),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (false),
CHAN_BOND_SEQ_1_1_0 => ("0000000000"),
CHAN_BOND_SEQ_1_2_0 => ("0000000000"),
CHAN_BOND_SEQ_1_3_0 => ("0000000000"),
CHAN_BOND_SEQ_1_4_0 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0000000000"),
CHAN_BOND_SEQ_2_2_0 => ("0000000000"),
CHAN_BOND_SEQ_2_3_0 => ("0000000000"),
CHAN_BOND_SEQ_2_4_0 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (false),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (true),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (false),
CHAN_BOND_SEQ_1_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2_1 => ("0000000000"),
CHAN_BOND_SEQ_1_3_1 => ("0000000000"),
CHAN_BOND_SEQ_1_4_1 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_3_1 => ("0000000000"),
CHAN_BOND_SEQ_2_4_1 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (false),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (true),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (false),
RX_EN_IDLE_HOLD_CDR_0 => (false),
RX_EN_IDLE_RESET_FR_0 => (true),
RX_EN_IDLE_RESET_PH_0 => (true),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (false),
RX_EN_IDLE_HOLD_CDR_1 => (false),
RX_EN_IDLE_RESET_FR_1 => (true),
RX_EN_IDLE_RESET_PH_1 => (true),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (9),
SATA_MAX_INIT_0 => (27),
SATA_MAX_WAKE_0 => (9),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (15),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (9),
SATA_MAX_INIT_1 => (27),
SATA_MAX_WAKE_1 => (9),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (15),
SATA_MIN_WAKE_1 => (5)
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => LOOPBACK0_IN,
LOOPBACK1 => LOOPBACK1_IN,
RXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
RXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
--------------------------------- PLL Ports --------------------------------
CLK00 => CLK00_IN,
CLK01 => CLK01_IN,
CLK10 => CLK10_IN,
CLK11 => CLK11_IN,
CLKINEAST0 => tied_to_ground_i,
CLKINEAST1 => tied_to_ground_i,
CLKINWEST0 => tied_to_ground_i,
CLKINWEST1 => tied_to_ground_i,
GCLK00 => tied_to_ground_i,
GCLK01 => tied_to_ground_i,
GCLK10 => tied_to_ground_i,
GCLK11 => tied_to_ground_i,
GTPRESET0 => GTPRESET0_IN,
GTPRESET1 => GTPRESET1_IN,
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => tied_to_vcc_i,
INTDATAWIDTH1 => tied_to_vcc_i,
PLLCLK00 => tied_to_ground_i,
PLLCLK01 => tied_to_ground_i,
PLLCLK10 => tied_to_ground_i,
PLLCLK11 => tied_to_ground_i,
PLLLKDET0 => PLLLKDET0_OUT,
PLLLKDET1 => PLLLKDET1_OUT,
PLLLKDETEN0 => tied_to_vcc_i,
PLLLKDETEN1 => tied_to_vcc_i,
PLLPOWERDOWN0 => tied_to_ground_i,
PLLPOWERDOWN1 => tied_to_ground_i,
REFCLKOUT0 => open,
REFCLKOUT1 => open,
REFCLKPLL0 => open,
REFCLKPLL1 => open,
REFCLKPWRDNB0 => tied_to_vcc_i,
REFCLKPWRDNB1 => tied_to_vcc_i,
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
RESETDONE0 => RESETDONE0_OUT,
RESETDONE1 => RESETDONE1_OUT,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN0 => tied_to_ground_vec_i(11 downto 0),
TSTIN1 => tied_to_ground_vec_i(11 downto 0),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0(3 downto 1) => rxcharisk0_float_i,
RXCHARISK0(0) => RXCHARISK0_OUT,
RXCHARISK1(3 downto 1) => rxcharisk1_float_i,
RXCHARISK1(0) => RXCHARISK1_OUT,
RXDEC8B10BUSE0 => tied_to_vcc_i,
RXDEC8B10BUSE1 => tied_to_vcc_i,
RXDISPERR0(3 downto 1) => rxdisperr0_float_i,
RXDISPERR0(0) => RXDISPERR0_OUT,
RXDISPERR1(3 downto 1) => rxdisperr1_float_i,
RXDISPERR1(0) => RXDISPERR1_OUT,
RXNOTINTABLE0(3 downto 1) => rxnotintable0_float_i,
RXNOTINTABLE0(0) => RXNOTINTABLE0_OUT,
RXNOTINTABLE1(3 downto 1) => rxnotintable1_float_i,
RXNOTINTABLE1(0) => RXNOTINTABLE1_OUT,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
USRCODEERR0 => tied_to_ground_i,
USRCODEERR1 => tied_to_ground_i,
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER0 => tied_to_ground_i,
RXCHBONDMASTER1 => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE0 => tied_to_ground_i,
RXCHBONDSLAVE1 => tied_to_ground_i,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => RXBYTEISALIGNED0_OUT,
RXBYTEISALIGNED1 => RXBYTEISALIGNED1_OUT,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => RXCOMMADET0_OUT,
RXCOMMADET1 => RXCOMMADET1_OUT,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => tied_to_ground_i,
RXENMCOMMAALIGN1 => tied_to_ground_i,
RXENPCOMMAALIGN0 => tied_to_ground_i,
RXENPCOMMAALIGN1 => tied_to_ground_i,
RXSLIDE0 => RXSLIDE0_IN,
RXSLIDE1 => RXSLIDE1_IN,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i,
RXDATA1 => rxdata1_i,
RXDATAWIDTH0 => "00",
RXDATAWIDTH1 => "00",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => tied_to_ground_i,
RXRESET1 => tied_to_ground_i,
RXUSRCLK0 => RXUSRCLK0_IN,
RXUSRCLK1 => RXUSRCLK1_IN,
RXUSRCLK20 => RXUSRCLK20_IN,
RXUSRCLK21 => RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => tied_to_ground_i,
GATERXELECIDLE1 => tied_to_ground_i,
IGNORESIGDET0 => tied_to_ground_i,
IGNORESIGDET1 => tied_to_ground_i,
RCALINEAST => tied_to_ground_vec_i(4 downto 0),
RCALINWEST => tied_to_ground_vec_i(4 downto 0),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => RXCDRRESET0_IN,
RXCDRRESET1 => RXCDRRESET1_IN,
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXEQMIX0 => "00",
RXEQMIX1 => "00",
RXN0 => RXN0_IN,
RXN1 => RXN1_IN,
RXP0 => RXP0_IN,
RXP1 => RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXENPMAPHASEALIGN0 => tied_to_ground_i,
RXENPMAPHASEALIGN1 => tied_to_ground_i,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => tied_to_ground_i,
RXPOLARITY1 => tied_to_ground_i,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => GTPCLKFBEAST_OUT,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => GTPCLKFBWEST_OUT,
GTPCLKOUT0 => GTPCLKOUT0_OUT,
GTPCLKOUT1 => GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE0 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL0 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL1 => tied_to_ground_vec_i(3 downto 0),
TXCHARISK0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK0(0) => TXCHARISK0_IN,
TXCHARISK1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK1(0) => TXCHARISK1_IN,
TXENC8B10BUSE0 => tied_to_vcc_i,
TXENC8B10BUSE1 => tied_to_vcc_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => TXRUNDISP0_OUT,
TXRUNDISP1 => TXRUNDISP1_OUT,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
TXENPMAPHASEALIGN0 => TXENPMAPHASEALIGN0_IN,
TXENPMAPHASEALIGN1 => TXENPMAPHASEALIGN1_IN,
TXPMASETPHASE0 => TXPMASETPHASE0_IN,
TXPMASETPHASE1 => TXPMASETPHASE1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i,
TXDATA1 => txdata1_i,
TXDATAWIDTH0 => "00",
TXDATAWIDTH1 => "00",
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => tied_to_ground_i,
TXRESET1 => tied_to_ground_i,
TXUSRCLK0 => TXUSRCLK0_IN,
TXUSRCLK1 => TXUSRCLK1_IN,
TXUSRCLK20 => TXUSRCLK20_IN,
TXUSRCLK21 => TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => "0110",
TXDIFFCTRL1 => "0110",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => TXN0_OUT,
TXN1 => TXN1_OUT,
TXP0 => TXP0_OUT,
TXP1 => TXP1_OUT,
TXPREEMPHASIS0 => "000",
TXPREEMPHASIS1 => "000",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR0 => tied_to_ground_i,
TXPRBSFORCEERR1 => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => tied_to_ground_i,
TXDETECTRX1 => tied_to_ground_i,
TXELECIDLE0 => tied_to_ground_i,
TXELECIDLE1 => tied_to_ground_i,
TXPDOWNASYNCH0 => tied_to_ground_i,
TXPDOWNASYNCH1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end RTL;
hdl/golden/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd deleted 100644 → 0
View file @ a465c3cc
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.7
-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
-- / / Filename : whiterabbitgtx_wrapper_gtx.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module WHITERABBITGTX_WRAPPER_GTX (a GTX Wrapper)
-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
--***************************** Entity Declaration ****************************
entity WHITERABBITGTX_WRAPPER_GTX is
generic
(
-- Simulation attributes
GTX_SIM_GTXRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
-- Share RX PLL parameter
GTX_TX_CLK_SOURCE : string := "TXPLL";
-- Save power parameter
GTX_POWER_SAVE : bit_vector := "0000000000"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK_IN : in std_logic_vector(2 downto 0);
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK_OUT : out std_logic_vector(1 downto 0);
RXDISPERR_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED_OUT : out std_logic;
RXCOMMADET_OUT : out std_logic;
RXSLIDE_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT : out std_logic_vector(15 downto 0);
RXRECCLK_OUT : out std_logic;
RXUSRCLK2_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET_IN : in std_logic;
RXN_IN : in std_logic;
RXP_IN : in std_logic;
------------------------ Receive Ports - RX PLL Ports ----------------------
GTXRXRESET_IN : in std_logic;
MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
PLLRXRESET_IN : in std_logic;
RXPLLLKDET_OUT : out std_logic;
RXRESETDONE_OUT : out std_logic;
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARISK_IN : in std_logic_vector(1 downto 0);
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST_IN : in std_logic_vector(12 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN : in std_logic_vector(15 downto 0);
TXOUTCLK_OUT : out std_logic;
TXUSRCLK2_IN : in std_logic;
TXRUNDISP_OUT : out std_logic_vector(1 downto 0);
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXN_OUT : out std_logic;
TXP_OUT : out std_logic;
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE_IN : in std_logic;
TXDLYALIGNMONENB_IN : in std_logic;
TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
TXDLYALIGNRESET_IN : in std_logic;
TXENPMAPHASEALIGN_IN : in std_logic;
TXPMASETPHASE_IN : in std_logic;
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTXTXRESET_IN : in std_logic;
MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
PLLTXRESET_IN : in std_logic;
TXPLLLKDET_OUT : out std_logic;
TXRESETDONE_OUT : out std_logic
);
end WHITERABBITGTX_WRAPPER_GTX;
architecture RTL of WHITERABBITGTX_WRAPPER_GTX is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
-- RX Datapath signals
signal rxdata_i : std_logic_vector(31 downto 0);
signal rxchariscomma_float_i : std_logic_vector(1 downto 0);
signal rxcharisk_float_i : std_logic_vector(1 downto 0);
signal rxdisperr_float_i : std_logic_vector(1 downto 0);
signal rxnotintable_float_i : std_logic_vector(1 downto 0);
signal rxrundisp_float_i : std_logic_vector(1 downto 0);
-- TX Datapath signals
signal txdata_i : std_logic_vector(31 downto 0);
signal txkerr_float_i : std_logic_vector(1 downto 0);
signal txrundisp_int : std_logic_vector(3 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
------------------- GTX Datapath byte mapping -----------------
-- The GTX provides little endian data (first byte received on RXDATA(7 downto 0))
RXDATA_OUT <= rxdata_i(15 downto 0);
txdata_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA_IN);
----------------------------- GTX Instance --------------------------
gtxe1_i : GTXE1
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (true),
SIM_GTXRESET_SPEEDUP => (GTX_SIM_GTXRESET_SPEEDUP),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_TXREFCLK_SOURCE => ("000"),
SIM_RXREFCLK_SOURCE => ("000"),
----------------------------TX PLL----------------------------
TX_CLK_SOURCE => (GTX_TX_CLK_SOURCE),
TX_OVERSAMPLE_MODE => (false),
TXPLL_COM_CFG => (x"21680a"),
TXPLL_CP_CFG => (x"0D"),
TXPLL_DIVSEL_FB => (4),
TXPLL_DIVSEL_OUT => (2),
TXPLL_DIVSEL_REF => (1),
TXPLL_DIVSEL45_FB => (5),
TXPLL_LKDET_CFG => ("111"),
TX_CLK25_DIVIDER => (3),
TXPLL_SATA => ("00"),
TX_TDCC_CFG => ("00"),
PMA_CAS_CLK_EN => (false),
POWER_SAVE => (GTX_POWER_SAVE),
-------------------------TX Interface-------------------------
GEN_TXUSRCLK => (true),
TX_DATA_WIDTH => (20),
TX_USRCLK_CFG => (x"00"),
TXOUTCLK_CTRL => ("TXPLLREFCLK_DIV2"),
TXOUTCLK_DLY => ("0000000000"),
--------------TX Buffering and Phase Alignment----------------
TX_PMADATA_OPT => ('1'),
PMA_TX_CFG => (x"80082"),
TX_BUFFER_USE => (false),
TX_BYTECLK_CFG => (x"00"),
TX_EN_RATE_RESET_BUF => (true),
TX_XCLK_SEL => ("TXUSR"),
TX_DLYALIGN_CTRINC => ("0100"),
TX_DLYALIGN_LPFINC => ("0110"),
TX_DLYALIGN_MONSEL => ("000"),
TX_DLYALIGN_OVRDSETTING => ("10000000"),
-------------------------TX Gearbox---------------------------
GEARBOX_ENDEC => ("000"),
TXGEARBOX_USE => (false),
----------------TX Driver and OOB Signalling------------------
TX_DRIVE_MODE => ("DIRECT"),
TX_IDLE_ASSERT_DELAY => ("100"),
TX_IDLE_DEASSERT_DELAY => ("010"),
TXDRIVE_LOOPBACK_HIZ => (false),
TXDRIVE_LOOPBACK_PD => (false),
--------------TX Pipe Control for PCI Express/SATA------------
COM_BURST_VAL => ("1111"),
------------------TX Attributes for PCI Express---------------
TX_DEEMPH_0 => ("11010"),
TX_DEEMPH_1 => ("10000"),
TX_MARGIN_FULL_0 => ("1001110"),
TX_MARGIN_FULL_1 => ("1001001"),
TX_MARGIN_FULL_2 => ("1000101"),
TX_MARGIN_FULL_3 => ("1000010"),
TX_MARGIN_FULL_4 => ("1000000"),
TX_MARGIN_LOW_0 => ("1000110"),
TX_MARGIN_LOW_1 => ("1000100"),
TX_MARGIN_LOW_2 => ("1000010"),
TX_MARGIN_LOW_3 => ("1000000"),
TX_MARGIN_LOW_4 => ("1000000"),
----------------------------RX PLL----------------------------
RX_OVERSAMPLE_MODE => (false),
RXPLL_COM_CFG => (x"21680a"),
RXPLL_CP_CFG => (x"0D"),
RXPLL_DIVSEL_FB => (4),
RXPLL_DIVSEL_OUT => (2),
RXPLL_DIVSEL_REF => (1),
RXPLL_DIVSEL45_FB => (5),
RXPLL_LKDET_CFG => ("111"),
RX_CLK25_DIVIDER => (3),
-------------------------RX Interface-------------------------
GEN_RXUSRCLK => (true),
RX_DATA_WIDTH => (20),
RXRECCLK_CTRL => ("RXRECCLKPMA_DIV2"),
RXRECCLK_DLY => ("0000000000"),
RXUSRCLK_DLY => (x"0000"),
----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
AC_CAP_DIS => (true),
CDR_PH_ADJ_TIME => ("10100"),
OOBDETECT_THRESHOLD => ("011"),
PMA_CDR_SCAN => (x"640404C"),
PMA_RX_CFG => (x"05ce008"),
RCV_TERM_GND => (false),
RCV_TERM_VTTRX => (true),
RX_EN_IDLE_HOLD_CDR => (false),
RX_EN_IDLE_RESET_FR => (false),
RX_EN_IDLE_RESET_PH => (false),
TX_DETECT_RX_CFG => (x"1832"),
TERMINATION_CTRL => ("00000"),
TERMINATION_OVRD => (false),
CM_TRIM => ("01"),
PMA_RXSYNC_CFG => (x"00"),
PMA_CFG => (x"0040000040000000003"),
BGTEST_CFG => ("00"),
BIAS_CFG => (x"00000"),
--------------RX Decision Feedback Equalizer(DFE)-------------
DFE_CAL_TIME => ("01100"),
DFE_CFG => ("00011011"),
RX_EN_IDLE_HOLD_DFE => (true),
RX_EYE_OFFSET => (x"4C"),
RX_EYE_SCANMODE => ("00"),
-------------------------PRBS Detection-----------------------
RXPRBSERR_LOOPBACK => ('0'),
------------------Comma Detection and Alignment---------------
ALIGN_COMMA_WORD => (2),
COMMA_10B_ENABLE => ("0001111111"),
COMMA_DOUBLE => (false),
DEC_MCOMMA_DETECT => (false),
DEC_PCOMMA_DETECT => (false),
DEC_VALID_COMMA_ONLY => (true),
MCOMMA_10B_VALUE => ("1010000011"),
MCOMMA_DETECT => (true),
PCOMMA_10B_VALUE => ("0101111100"),
PCOMMA_DETECT => (true),
RX_DECODE_SEQ_MATCH => (true),
RX_SLIDE_AUTO_WAIT => (5),
RX_SLIDE_MODE => ("PCS"),
-- SHOW_REALIGN_COMMA => (TRUE),
SHOW_REALIGN_COMMA => (false),
-----------------RX Loss-of-sync State Machine----------------
RX_LOS_INVALID_INCR => (8),
RX_LOS_THRESHOLD => (128),
RX_LOSS_OF_SYNC_FSM => (false),
-------------------------RX Gearbox---------------------------
RXGEARBOX_USE => (false),
-------------RX Elastic Buffer and Phase alignment------------
RX_BUFFER_USE => (true),
RX_EN_IDLE_RESET_BUF => (false),
RX_EN_MODE_RESET_BUF => (true),
RX_EN_RATE_RESET_BUF => (true),
RX_EN_REALIGN_RESET_BUF => (false),
RX_EN_REALIGN_RESET_BUF2 => (false),
RX_FIFO_ADDR_MODE => ("FULL"),
RX_IDLE_HI_CNT => ("1000"),
RX_IDLE_LO_CNT => ("0000"),
RX_XCLK_SEL => ("RXREC"),
RX_DLYALIGN_CTRINC => ("1110"),
RX_DLYALIGN_EDGESET => ("00010"),
RX_DLYALIGN_LPFINC => ("1110"),
RX_DLYALIGN_MONSEL => ("000"),
RX_DLYALIGN_OVRDSETTING => ("10000000"),
------------------------Clock Correction----------------------
CLK_COR_ADJ_LEN => (1),
CLK_COR_DET_LEN => (1),
CLK_COR_INSERT_IDLE_FLAG => (false),
CLK_COR_KEEP_IDLE => (false),
CLK_COR_MAX_LAT => (16),
CLK_COR_MIN_LAT => (14),
CLK_COR_PRECEDENCE => (true),
CLK_COR_REPEAT_WAIT => (0),
CLK_COR_SEQ_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2 => ("0100000000"),
CLK_COR_SEQ_1_3 => ("0100000000"),
CLK_COR_SEQ_1_4 => ("0100000000"),
CLK_COR_SEQ_1_ENABLE => ("1111"),
CLK_COR_SEQ_2_1 => ("0100000000"),
CLK_COR_SEQ_2_2 => ("0100000000"),
CLK_COR_SEQ_2_3 => ("0100000000"),
CLK_COR_SEQ_2_4 => ("0100000000"),
CLK_COR_SEQ_2_ENABLE => ("1111"),
CLK_COR_SEQ_2_USE => (false),
CLK_CORRECT_USE => (false),
------------------------Channel Bonding----------------------
CHAN_BOND_1_MAX_SKEW => (1),
CHAN_BOND_2_MAX_SKEW => (1),
CHAN_BOND_KEEP_ALIGN => (false),
CHAN_BOND_SEQ_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2 => ("0000000000"),
CHAN_BOND_SEQ_1_3 => ("0000000000"),
CHAN_BOND_SEQ_1_4 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2 => ("0000000000"),
CHAN_BOND_SEQ_2_3 => ("0000000000"),
CHAN_BOND_SEQ_2_4 => ("0000000000"),
CHAN_BOND_SEQ_2_CFG => ("00000"),
CHAN_BOND_SEQ_2_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_USE => (false),
CHAN_BOND_SEQ_LEN => (1),
PCI_EXPRESS_MODE => (false),
-------------RX Attributes for PCI Express/SATA/SAS----------
SAS_MAX_COMSAS => (52),
SAS_MIN_COMSAS => (40),
SATA_BURST_VAL => ("100"),
SATA_IDLE_VAL => ("100"),
SATA_MAX_BURST => (9),
SATA_MAX_INIT => (27),
SATA_MAX_WAKE => (9),
SATA_MIN_BURST => (5),
SATA_MIN_INIT => (15),
SATA_MIN_WAKE => (5),
TRANS_TIME_FROM_P2 => (x"03c"),
TRANS_TIME_NON_P2 => (x"19"),
TRANS_TIME_RATE => (x"ff"),
TRANS_TIME_TO_P2 => (x"064")
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK => LOOPBACK_IN,
RXPOWERDOWN => "00",
TXPOWERDOWN => "00",
-------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
RXDATAVALID => open,
RXGEARBOXSLIP => tied_to_ground_i,
RXHEADER => open,
RXHEADERVALID => open,
RXSTARTOFSEQ => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA => open,
RXCHARISK(3 downto 2) => rxcharisk_float_i,
RXCHARISK(1 downto 0) => RXCHARISK_OUT,
RXDEC8B10BUSE => tied_to_vcc_i,
RXDISPERR(3 downto 2) => rxdisperr_float_i,
RXDISPERR(1 downto 0) => RXDISPERR_OUT,
RXNOTINTABLE(3 downto 2) => rxnotintable_float_i,
RXNOTINTABLE(1 downto 0) => RXNOTINTABLE_OUT,
RXRUNDISP => open,
USRCODEERR => tied_to_ground_i,
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ => open,
RXCHBONDI => tied_to_ground_vec_i(3 downto 0),
RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE => tied_to_ground_i,
RXENCHANSYNC => tied_to_ground_i,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED => RXBYTEISALIGNED_OUT,
RXBYTEREALIGN => open,
RXCOMMADET => RXCOMMADET_OUT,
RXCOMMADETUSE => tied_to_vcc_i,
RXENMCOMMAALIGN => tied_to_ground_i,
RXENPCOMMAALIGN => tied_to_ground_i,
RXSLIDE => RXSLIDE_IN,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET => tied_to_ground_i,
RXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA => rxdata_i,
RXRECCLK => RXRECCLK_OUT,
RXRECCLKPCS => open,
RXRESET => tied_to_ground_i,
RXUSRCLK => tied_to_ground_i,
RXUSRCLK2 => RXUSRCLK2_IN,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DFECLKDLYADJ => tied_to_ground_vec_i(5 downto 0),
DFECLKDLYADJMON => open,
DFEDLYOVRD => tied_to_vcc_i,
DFEEYEDACMON => open,
DFESENSCAL => open,
DFETAP1 => tied_to_ground_vec_i(4 downto 0),
DFETAP1MONITOR => open,
DFETAP2 => tied_to_ground_vec_i(4 downto 0),
DFETAP2MONITOR => open,
DFETAP3 => tied_to_ground_vec_i(3 downto 0),
DFETAP3MONITOR => open,
DFETAP4 => tied_to_ground_vec_i(3 downto 0),
DFETAP4MONITOR => open,
DFETAPOVRD => tied_to_vcc_i,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE => tied_to_vcc_i,
IGNORESIGDET => tied_to_vcc_i,
RXCDRRESET => RXCDRRESET_IN,
RXELECIDLE => open,
RXEQMIX => "0000000000",
RXN => RXN_IN,
RXP => RXP_IN,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET => tied_to_ground_i,
RXBUFSTATUS => open,
RXCHANISALIGNED => open,
RXCHANREALIGN => open,
RXDLYALIGNDISABLE => tied_to_ground_i,
RXDLYALIGNMONENB => tied_to_ground_i,
RXDLYALIGNMONITOR => open,
RXDLYALIGNOVERRIDE => tied_to_vcc_i,
RXDLYALIGNRESET => tied_to_ground_i,
RXDLYALIGNSWPPRECURB => tied_to_vcc_i,
RXDLYALIGNUPDSW => tied_to_ground_i,
RXENPMAPHASEALIGN => tied_to_ground_i,
RXPMASETPHASE => tied_to_ground_i,
RXSTATUS => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC => open,
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN => tied_to_ground_i,
RXOVERSAMPLEERR => open,
------------------------ Receive Ports - RX PLL Ports ----------------------
GREFCLKRX => tied_to_ground_i,
GTXRXRESET => GTXRXRESET_IN,
MGTREFCLKRX => MGTREFCLKRX_IN,
NORTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
PERFCLKRX => tied_to_ground_i,
PLLRXRESET => PLLRXRESET_IN,
RXPLLLKDET => RXPLLLKDET_OUT,
RXPLLLKDETEN => tied_to_vcc_i,
RXPLLPOWERDOWN => tied_to_ground_i,
RXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
RXRATE => tied_to_ground_vec_i(1 downto 0),
RXRATEDONE => open,
RXRESETDONE => RXRESETDONE_OUT,
SOUTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS => open,
RXVALID => open,
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY => tied_to_ground_i,
--------------------- Receive Ports - RX Ports for SATA --------------------
COMINITDET => open,
COMSASDET => open,
COMWAKEDET => open,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
-------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
TXGEARBOXREADY => open,
TXHEADER => tied_to_ground_vec_i(2 downto 0),
TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
TXSTARTSEQ => tied_to_ground_i,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL => tied_to_ground_vec_i(3 downto 0),
TXCHARISK(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARISK(1 downto 0) => TXCHARISK_IN,
TXENC8B10BUSE => tied_to_vcc_i,
TXKERR => open,
TXRUNDISP => txrundisp_int,
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST => GTXTEST_IN,
MGTREFCLKFAB => open,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN => "11111111111111111111",
TSTOUT => open,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA => txdata_i,
TXOUTCLK => TXOUTCLK_OUT,
TXOUTCLKPCS => open,
TXRESET => tied_to_ground_i,
TXUSRCLK => tied_to_ground_i,
TXUSRCLK2 => TXUSRCLK2_IN,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXBUFDIFFCTRL => "100",
TXDIFFCTRL => "1101",
TXINHIBIT => tied_to_ground_i,
TXN => TXN_OUT,
TXP => TXP_OUT,
TXPOSTEMPHASIS => "00000",
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXPREEMPHASIS => "0000",
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS => open,
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE => TXDLYALIGNDISABLE_IN,
TXDLYALIGNMONENB => TXDLYALIGNMONENB_IN,
TXDLYALIGNMONITOR => TXDLYALIGNMONITOR_OUT,
TXDLYALIGNOVERRIDE => tied_to_ground_i,
TXDLYALIGNRESET => TXDLYALIGNRESET_IN,
TXDLYALIGNUPDSW => tied_to_ground_i,
TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_IN,
TXPMASETPHASE => TXPMASETPHASE_IN,
----------------------- Transmit Ports - TX PLL Ports ----------------------
GREFCLKTX => tied_to_ground_i,
GTXTXRESET => GTXTXRESET_IN,
MGTREFCLKTX => MGTREFCLKTX_IN,
NORTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
PERFCLKTX => tied_to_ground_i,
PLLTXRESET => PLLTXRESET_IN,
SOUTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
TXPLLLKDET => TXPLLLKDET_OUT,
TXPLLLKDETEN => tied_to_vcc_i,
TXPLLPOWERDOWN => tied_to_ground_i,
TXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
TXRATE => tied_to_ground_vec_i(1 downto 0),
TXRATEDONE => open,
TXRESETDONE => TXRESETDONE_OUT,
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDEEMPH => tied_to_ground_i,
TXDETECTRX => tied_to_ground_i,
TXELECIDLE => tied_to_ground_i,
TXMARGIN => tied_to_ground_vec_i(2 downto 0),
TXPDOWNASYNCH => tied_to_ground_i,
TXSWING => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
COMFINISH => open,
TXCOMINIT => tied_to_ground_i,
TXCOMSAS => tied_to_ground_i,
TXCOMWAKE => tied_to_ground_i
);
TXRUNDISP_OUT <= txrundisp_int(1 downto 0);
end RTL;
hdl/golden/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd deleted 100644 → 0
View file @ a465c3cc
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - Spartan-6 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gtp_phy_spartan6.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2012-04-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual channel wrapper for Xilinx Spartan-6 GTP adapted for
-- deterministic delays at 1.25 Gbps.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN / Tomasz Wlostowski
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Initial release
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP (single channel only)
-- 2011-05-15 0.6 twlostow Added reference clock output
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.all;
library work;
use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
entity wr_gtp_phy_spartan6 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 1;
g_force_disparity : integer := 0
);
port (
-- Port 0
-- dedicated GTP clock input
gtp_clk_i: in std_logic;
-- TX path, synchronous to ch0_ref_clk_i
ch0_ref_clk_i : in std_logic;
-- data input (8 bits, not 8b10b-encoded)
ch0_tx_data_i : in std_logic_vector(7 downto 0);
-- 1 when tx_data_i contains a control code, 0 when it's a data byte
ch0_tx_k_i : in std_logic;
-- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
-- Necessary for the PCS to generate proper frame termination sequences.
ch0_tx_disparity_o : out std_logic;
-- Encoding error indication (1 = error, 0 = no error)
ch0_tx_enc_err_o : out std_logic;
-- RX path, synchronous to ch0_rx_rbclk_o.
-- RX recovered clock
ch0_rx_rbclk_o : out std_logic;
-- 8b10b-decoded data output. The data output must be kept invalid before
-- the transceiver is locked on the incoming signal to prevent the EP from
-- detecting a false carrier.
ch0_rx_data_o : out std_logic_vector(7 downto 0);
-- 1 when the byte on rx_data_o is a control code
ch0_rx_k_o : out std_logic;
-- encoding error indication
ch0_rx_enc_err_o : out std_logic;
-- RX bitslide indication, indicating the delay of the RX path of the
-- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
-- reset input, active hi
ch0_rst_i : in std_logic;
-- local loopback enable (Tx->Rx), active hi
ch0_loopen_i : in std_logic;
-- Port 1
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
-- Serial I/O
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0'
);
end wr_gtp_phy_spartan6;
architecture rtl of wr_gtp_phy_spartan6 is
component WHITERABBITGTP_WRAPPER_TILE_SPARTAN6
generic (
TILE_SIM_GTPRESET_SPEEDUP : integer;
TILE_CLK25_DIVIDER_0 : integer;
TILE_CLK25_DIVIDER_1 : integer;
TILE_PLL_DIVSEL_FB_0 : integer;
TILE_PLL_DIVSEL_FB_1 : integer;
TILE_PLL_DIVSEL_REF_0 : integer;
TILE_PLL_DIVSEL_REF_1 : integer;
TILE_PLL_SOURCE_0 : string;
TILE_PLL_SOURCE_1 : string);
port (
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
REFCLKOUT0_OUT : out std_logic;
REFCLKOUT1_OUT : out std_logic;
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
CLK10_IN : in std_logic;
CLK11_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
RXDISPERR1_OUT : out std_logic;
RXNOTINTABLE0_OUT : out std_logic;
RXNOTINTABLE1_OUT : out std_logic;
RXBYTEISALIGNED0_OUT : out std_logic;
RXBYTEISALIGNED1_OUT : out std_logic;
RXCOMMADET0_OUT : out std_logic;
RXCOMMADET1_OUT : out std_logic;
RXSLIDE0_IN : in std_logic;
RXSLIDE1_IN : in std_logic;
RXDATA0_OUT : out std_logic_vector(7 downto 0);
RXDATA1_OUT : out std_logic_vector(7 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
RXCDRRESET0_IN : in std_logic;
RXCDRRESET1_IN : in std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
TXCHARISK0_IN : in std_logic;
TXCHARISK1_IN : in std_logic;
TXCHARDISPMODE0_IN : in std_logic;
TXCHARDISPMODE1_IN : in std_logic;
TXCHARDISPVAL0_IN : in std_logic;
TXCHARDISPVAL1_IN : in std_logic;
TXRUNDISP0_OUT : out std_logic_vector(3 downto 0);
TXRUNDISP1_OUT : out std_logic_vector(3 downto 0);
TXENPMAPHASEALIGN0_IN : in std_logic;
TXENPMAPHASEALIGN1_IN : in std_logic;
TXPMASETPHASE0_IN : in std_logic;
TXPMASETPHASE1_IN : in std_logic;
TXDATA0_IN : in std_logic_vector(7 downto 0);
TXDATA1_IN : in std_logic_vector(7 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic);
end component;
component BUFG
port (
O : out std_ulogic;
I : in std_ulogic);
end component;
component BUFIO2
generic (
DIVIDE_BYPASS : boolean := true;
DIVIDE : integer := 1;
I_INVERT : boolean := false;
USE_DOUBLER : boolean := false);
port (
DIVCLK : out std_ulogic;
IOCLK : out std_ulogic;
SERDESSTROBE : out std_ulogic;
I : in std_ulogic);
end component;
component gtp_phase_align
generic(
g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic);
end component;
component gtp_bitslide
generic(
g_simulation : integer;
g_target : string := "spartan6");
port (
gtp_rst_i : in std_logic;
gtp_rx_clk_i : in std_logic;
gtp_rx_comma_det_i : in std_logic;
gtp_rx_byte_is_aligned_i : in std_logic;
serdes_ready_i : in std_logic;
gtp_rx_slide_o : out std_logic;
gtp_rx_cdr_rst_o : out std_logic;
bitslide_o : out std_logic_vector(4 downto 0);
synced_o : out std_logic);
end component;
signal ch0_gtp_reset : std_logic;
signal ch0_gtp_loopback : std_logic_vector(2 downto 0) := "000";
signal ch0_gtp_reset_done : std_logic;
signal ch0_gtp_pll_lockdet : std_logic;
signal ch0_tx_pma_set_phase : std_logic := '0';
signal ch0_tx_rundisp_vec : std_logic_vector(3 downto 0);
signal ch0_tx_en_pma_phase_align : std_logic := '0';
signal ch0_rx_data_int : std_logic_vector(7 downto 0);
signal ch0_rx_k_int : std_logic;
signal ch0_rx_disperr, ch0_rx_invcode : std_logic;
signal ch0_rx_byte_is_aligned : std_logic;
signal ch0_rx_comma_det : std_logic;
signal ch0_rx_cdr_rst : std_logic := '0';
signal ch0_rx_rec_clk_pad : std_logic;
signal ch0_rx_rec_clk : std_logic;
signal ch0_rx_divclk : std_logic;
signal ch0_rx_slide : std_logic := '0';
signal ch0_gtp_locked : std_logic;
signal ch0_align_done : std_logic;
signal ch0_rx_synced : std_logic;
signal ch0_gtp_clkout_int : std_logic_vector(1 downto 0);
signal ch0_rx_enable_output, ch0_rx_enable_output_synced : std_logic;
signal ch1_gtp_reset : std_logic;
signal ch1_gtp_loopback : std_logic_vector(2 downto 0) := "000";
signal ch1_gtp_reset_done : std_logic;
signal ch1_gtp_pll_lockdet : std_logic;
signal ch1_tx_pma_set_phase : std_logic := '0';
signal ch1_tx_rundisp_vec : std_logic_vector(3 downto 0);
signal ch1_tx_en_pma_phase_align : std_logic := '0';
signal ch1_rx_data_int : std_logic_vector(7 downto 0);
signal ch1_rx_k_int : std_logic;
signal ch1_rx_disperr, ch1_rx_invcode : std_logic;
signal ch1_rx_byte_is_aligned : std_logic;
signal ch1_rx_comma_det : std_logic;
signal ch1_rx_cdr_rst : std_logic := '0';
signal ch1_rx_rec_clk_pad : std_logic;
signal ch1_rx_rec_clk : std_logic;
signal ch1_rx_divclk : std_logic;
signal ch1_rx_slide : std_logic := '0';
signal ch1_gtp_locked : std_logic;
signal ch1_align_done : std_logic;
signal ch1_rx_synced : std_logic;
signal ch1_gtp_clkout_int : std_logic_vector(1 downto 0);
signal ch1_rx_enable_output, ch1_rx_enable_output_synced : std_logic;
signal ch0_rst_synced : std_logic;
signal ch0_rst_d0 : std_logic;
signal ch0_reset_counter : unsigned(9 downto 0);
signal ch1_rst_synced : std_logic;
signal ch1_rst_d0 : std_logic;
signal ch1_reset_counter : unsigned(9 downto 0);
signal ch0_rx_bitslide_int : std_logic_vector(4 downto 0);
signal ch1_rx_bitslide_int : std_logic_vector(4 downto 0);
signal ch0_ref_clk_in : std_logic_vector(1 downto 0);
signal ch1_ref_clk_in : std_logic_vector(1 downto 0);
signal ch0_disparity_set : std_logic;
signal ch1_disparity_set : std_logic;
signal ch0_tx_chardispmode : std_logic;
signal ch1_tx_chardispmode : std_logic;
signal ch0_tx_chardispval : std_logic;
signal ch1_tx_chardispval : std_logic;
component enc_8b10b
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ctrl_i : in std_logic;
in_8b_i : in std_logic_vector(7 downto 0);
err_o : out std_logic;
dispar_o : out std_logic;
out_10b_o : out std_logic_vector(9 downto 0));
end component;
signal ch0_rst_n : std_logic;
signal ch1_rst_n : std_logic;
signal ch0_cur_disp : t_8b10b_disparity;
signal ch0_disp_pipe : std_logic_vector(1 downto 0);
signal ch1_cur_disp : t_8b10b_disparity;
signal ch1_disp_pipe : std_logic_vector(1 downto 0);
begin -- rtl
ch0_rst_n <= not ch0_gtp_reset;
ch1_rst_n <= not ch1_gtp_reset;
gen_disp_ch0 : process(ch0_ref_clk_i)
begin
if rising_edge(ch0_ref_clk_i) then
if(ch0_tx_chardispmode = '1' or ch0_rst_n = '0') then
if(g_force_disparity = 0) then
ch0_cur_disp <= RD_MINUS;
else
ch0_cur_disp <= RD_PLUS;
end if;
ch0_disp_pipe <= (others => '0');
else
ch0_cur_disp <= f_next_8b10b_disparity8(ch0_cur_disp, ch0_tx_k_i, ch0_tx_data_i);
ch0_disp_pipe(0) <= to_std_logic(ch0_cur_disp);
ch0_disp_pipe(1) <= ch0_disp_pipe(0);
end if;
end if;
end process;
gen_disp_ch1 : process(ch1_ref_clk_i)
begin
if rising_edge(ch1_ref_clk_i) then
if(ch1_tx_chardispmode = '1' or ch1_rst_n = '0') then
if(g_force_disparity = 0) then
ch1_cur_disp <= RD_MINUS;
else
ch1_cur_disp <= RD_PLUS;
end if;
ch1_disp_pipe <= (others => '0');
else
ch1_cur_disp <= f_next_8b10b_disparity8(ch1_cur_disp, ch1_tx_k_i, ch1_tx_data_i);
ch1_disp_pipe(0) <= to_std_logic(ch1_cur_disp);
ch1_disp_pipe(1) <= ch1_disp_pipe(0);
end if;
end if;
end process;
ch0_tx_disparity_o <= ch0_disp_pipe(0);
ch1_tx_disparity_o <= ch1_disp_pipe(1);
p_gen_reset_ch0 : process(ch0_ref_clk_i)
begin
if rising_edge(ch0_ref_clk_i) then
ch0_rst_d0 <= ch0_rst_i;
ch0_rst_synced <= ch0_rst_d0;
if(ch0_rst_synced = '1') then
ch0_reset_counter <= (others => '0');
else
if(ch0_reset_counter(ch0_reset_counter'left) = '0') then
ch0_reset_counter <= ch0_reset_counter + 1;
end if;
end if;
end if;
end process;
p_gen_reset_ch1 : process(ch1_ref_clk_i)
begin
if rising_edge(ch1_ref_clk_i) then
ch1_rst_d0 <= ch1_rst_i;
ch1_rst_synced <= ch1_rst_d0;
if(ch1_rst_synced = '1') then
ch1_reset_counter <= (others => '0');
else
if(ch1_reset_counter(ch1_reset_counter'left) = '0') then
ch1_reset_counter <= ch1_reset_counter + 1;
end if;
end if;
end if;
end process;
ch0_gtp_reset <= ch0_rst_synced or std_logic(not ch0_reset_counter(ch0_reset_counter'left));
ch1_gtp_reset <= ch1_rst_synced or std_logic(not ch1_reset_counter(ch1_reset_counter'left));
ch0_rx_rec_clk_pad <= ch0_gtp_clkout_int(1);
ch1_rx_rec_clk_pad <= ch1_gtp_clkout_int(1);
ch0_ref_clk_in(0) <= gtp_clk_i;
ch0_ref_clk_in(1) <= '0';
ch1_ref_clk_in(0) <= gtp_clk_i;
ch1_ref_clk_in(1) <= '0';
U_GTP_TILE_INST : WHITERABBITGTP_WRAPPER_TILE_SPARTAN6
generic map
(
TILE_SIM_GTPRESET_SPEEDUP => g_simulation, -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 => 5,
TILE_CLK25_DIVIDER_1 => 5,
TILE_PLL_DIVSEL_FB_0 => 2,
TILE_PLL_DIVSEL_FB_1 => 2,
TILE_PLL_DIVSEL_REF_0 => 1,
TILE_PLL_DIVSEL_REF_1 => 1,
--
TILE_PLL_SOURCE_0 => "PLL0",
TILE_PLL_SOURCE_1 => "PLL1"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN => ch0_gtp_loopback,
LOOPBACK1_IN => ch1_gtp_loopback,
--------------------------------- PLL Ports --------------------------------
REFCLKOUT0_OUT => open,
REFCLKOUT1_OUT => open,
CLK00_IN => ch0_ref_clk_in(0),
CLK01_IN => ch1_ref_clk_in(0),
CLK10_IN => ch0_ref_clk_in(1),
CLK11_IN => ch1_ref_clk_in(1),
GTPRESET0_IN => ch0_gtp_reset,
GTPRESET1_IN => ch1_gtp_reset,
PLLLKDET0_OUT => ch0_gtp_pll_lockdet,
PLLLKDET1_OUT => ch1_gtp_pll_lockdet,
RESETDONE0_OUT => ch0_gtp_reset_done,
RESETDONE1_OUT => ch1_gtp_reset_done,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT => ch0_rx_k_int,
RXCHARISK1_OUT => ch1_rx_k_int,
RXDISPERR0_OUT => ch0_rx_disperr,
RXDISPERR1_OUT => ch1_rx_disperr,
RXNOTINTABLE0_OUT => ch0_rx_invcode,
RXNOTINTABLE1_OUT => ch1_rx_invcode,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT => ch0_rx_byte_is_aligned,
RXBYTEISALIGNED1_OUT => ch1_rx_byte_is_aligned,
RXCOMMADET0_OUT => ch0_rx_comma_det,
RXCOMMADET1_OUT => ch1_rx_comma_det,
RXSLIDE0_IN => ch0_rx_slide,
RXSLIDE1_IN => ch1_rx_slide,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT => ch0_rx_data_int,
RXDATA1_OUT => ch1_rx_data_int,
RXUSRCLK0_IN => ch0_rx_rec_clk,
RXUSRCLK1_IN => ch1_rx_rec_clk,
RXUSRCLK20_IN => ch0_rx_rec_clk,
RXUSRCLK21_IN => ch1_rx_rec_clk,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN => ch0_rx_cdr_rst,
RXCDRRESET1_IN => ch1_rx_cdr_rst,
RXN0_IN => pad_rxn0_i,
RXN1_IN => pad_rxn1_i,
RXP0_IN => pad_rxp0_i,
RXP1_IN => pad_rxp1_i,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT => open,
GTPCLKFBWEST_OUT => open,
GTPCLKOUT0_OUT => ch0_gtp_clkout_int,
GTPCLKOUT1_OUT => ch1_gtp_clkout_int,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN => ch0_tx_k_i,
TXCHARISK1_IN => ch1_tx_k_i,
TXRUNDISP0_OUT => ch0_tx_rundisp_vec,
TXRUNDISP1_OUT => ch1_tx_rundisp_vec,
TXCHARDISPMODE0_IN => ch0_tx_chardispmode,
TXCHARDISPMODE1_IN => ch1_tx_chardispmode,
TXCHARDISPVAL0_IN => ch0_tx_chardispval,
TXCHARDISPVAL1_IN => ch1_tx_chardispval,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN => ch0_tx_en_pma_phase_align,
TXENPMAPHASEALIGN1_IN => ch1_tx_en_pma_phase_align,
TXPMASETPHASE0_IN => ch0_tx_pma_set_phase,
TXPMASETPHASE1_IN => ch1_tx_pma_set_phase,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN => ch0_tx_data_i,
TXDATA1_IN => ch1_tx_data_i,
TXUSRCLK0_IN => ch0_ref_clk_i,
TXUSRCLK1_IN => ch1_ref_clk_i,
TXUSRCLK20_IN => ch0_ref_clk_i,
TXUSRCLK21_IN => ch1_ref_clk_i,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT => pad_txn0_o,
TXN1_OUT => pad_txn1_o,
TXP0_OUT => pad_txp0_o,
TXP1_OUT => pad_txp1_o
);
U_Rbclk_buf_ch0 : BUFIO2
port map (
DIVCLK => ch0_rx_divclk,
IOCLK => open,
SERDESSTROBE => open,
I => ch0_rx_rec_clk_pad);
U_Rbclk_bufg_ch0 : BUFG
port map (
I => ch0_rx_divclk,
O => ch0_rx_rec_clk
);
U_Rbclk_buf_ch1 : BUFIO2
port map (
DIVCLK => ch1_rx_divclk,
IOCLK => open,
SERDESSTROBE => open,
I => ch1_rx_rec_clk_pad);
U_Rbclk_bufg_ch1 : BUFG
port map (
I => ch1_rx_divclk,
O => ch1_rx_rec_clk
);
ch0_gtp_locked <= ch0_gtp_pll_lockdet and ch0_gtp_reset_done;
ch0_tx_enc_err_o <= '0';
ch1_gtp_locked <= ch1_gtp_pll_lockdet and ch1_gtp_reset_done;
ch1_tx_enc_err_o <= '0';
U_align_ch0 : gtp_phase_align
generic map (
g_simulation => g_simulation)
port map (
gtp_rst_i => ch0_gtp_reset,
gtp_tx_clk_i => ch0_ref_clk_i,
gtp_tx_en_pma_phase_align_o => ch0_tx_en_pma_phase_align,
gtp_tx_pma_set_phase_o => ch0_tx_pma_set_phase,
align_en_i => ch0_gtp_locked,
align_done_o => ch0_align_done);
U_align_ch1 : gtp_phase_align
generic map (
g_simulation => g_simulation)
port map (
gtp_rst_i => ch1_gtp_reset,
gtp_tx_clk_i => ch1_ref_clk_i,
gtp_tx_en_pma_phase_align_o => ch1_tx_en_pma_phase_align,
gtp_tx_pma_set_phase_o => ch1_tx_pma_set_phase,
align_en_i => ch1_gtp_locked,
align_done_o => ch1_align_done);
U_bitslide_ch0 : gtp_bitslide
generic map (
g_simulation => g_simulation)
port map (
gtp_rst_i => ch0_gtp_reset,
gtp_rx_clk_i => ch0_rx_rec_clk,
gtp_rx_comma_det_i => ch0_rx_comma_det,
gtp_rx_byte_is_aligned_i => ch0_rx_byte_is_aligned,
serdes_ready_i => ch0_gtp_locked,
gtp_rx_slide_o => ch0_rx_slide,
gtp_rx_cdr_rst_o => ch0_rx_cdr_rst,
bitslide_o => ch0_rx_bitslide_int,
synced_o => ch0_rx_synced);
ch0_rx_bitslide_o <= ch0_rx_bitslide_int(3 downto 0);
U_bitslide_ch1 : gtp_bitslide
generic map (
g_simulation => g_simulation)
port map (
gtp_rst_i => ch1_gtp_reset,
gtp_rx_clk_i => ch1_rx_rec_clk,
gtp_rx_comma_det_i => ch1_rx_comma_det,
gtp_rx_byte_is_aligned_i => ch1_rx_byte_is_aligned,
serdes_ready_i => ch1_gtp_locked,
gtp_rx_slide_o => ch1_rx_slide,
gtp_rx_cdr_rst_o => ch1_rx_cdr_rst,
bitslide_o => ch1_rx_bitslide_int,
synced_o => ch1_rx_synced);
ch1_rx_bitslide_o <= ch1_rx_bitslide_int(3 downto 0);
ch0_rx_enable_output <= ch0_rx_synced and ch0_align_done;
ch1_rx_enable_output <= ch1_rx_synced and ch1_align_done;
U_sync_oen_ch0 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => ch0_rx_rec_clk,
rst_n_i => '1',
data_i => ch0_rx_enable_output,
synced_o => ch0_rx_enable_output_synced,
npulse_o => open,
ppulse_o => open);
U_sync_oen_ch1 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => ch1_rx_rec_clk,
rst_n_i => '1',
data_i => ch1_rx_enable_output,
synced_o => ch1_rx_enable_output_synced,
npulse_o => open,
ppulse_o => open);
p_force_proper_disparity_ch0 : process(ch0_ref_clk_i, ch0_gtp_reset)
begin
if (ch0_gtp_reset = '1') then
ch0_disparity_set <= '0';
ch0_tx_chardispval <= '0';
ch0_tx_chardispmode <= '0';
elsif rising_edge(ch0_ref_clk_i) then
if(ch0_disparity_set = '0' and ch0_tx_k_i = '1' and ch0_tx_data_i = x"bc" and ch0_align_done = '1') then
ch0_disparity_set <= '1';
if(g_force_disparity = 0) then
ch0_tx_chardispval <= '0' ;
else
ch0_tx_chardispval <= '1';
end if;
ch0_tx_chardispmode <= '1';
else
ch0_tx_chardispmode <= '0';
ch0_tx_chardispval <= '0';
end if;
end if;
end process;
p_force_proper_disparity_ch1 : process(ch1_ref_clk_i, ch1_gtp_reset)
begin
if (ch1_gtp_reset = '1') then
ch1_disparity_set <= '0';
ch1_tx_chardispval <= '0';
ch1_tx_chardispmode <= '0';
elsif rising_edge(ch1_ref_clk_i) then
if(ch1_disparity_set = '0' and ch1_tx_k_i = '1' and ch1_tx_data_i = x"bc" and ch1_align_done = '1') then
ch1_disparity_set <= '1';
if(g_force_disparity = 0) then
ch1_tx_chardispval <= '0';
else
ch1_tx_chardispval <= '1';
end if;
ch1_tx_chardispmode <= '1';
else
ch1_tx_chardispmode <= '0';
ch1_tx_chardispval <= '0';
end if;
end if;
end process;
p_gen_output_ch0 : process(ch0_rx_rec_clk, ch0_gtp_reset)
begin
if(ch0_gtp_reset = '1') then
ch0_rx_data_o <= (others => '0');
ch0_rx_k_o <= '0';
ch0_rx_enc_err_o <= '0';
elsif rising_edge(ch0_rx_rec_clk) then
if(ch0_rx_enable_output_synced = '0') then
-- make sure the output data is invalid when the link is down and that it will
-- trigger the sync loss detection
ch0_rx_data_o <= (others => '0');
ch0_rx_k_o <= '1';
ch0_rx_enc_err_o <= '1';
else
ch0_rx_data_o <= ch0_rx_data_int;
ch0_rx_k_o <= ch0_rx_k_int;
ch0_rx_enc_err_o <= ch0_rx_disperr or ch0_rx_invcode;
end if;
end if;
end process;
p_gen_output_ch1 : process(ch1_rx_rec_clk, ch1_rst_i)
begin
if(ch1_rst_i = '1') then
ch1_rx_data_o <= (others => '0');
ch1_rx_k_o <= '0';
ch1_rx_enc_err_o <= '0';
elsif rising_edge(ch1_rx_rec_clk) then
if(ch1_rx_enable_output_synced = '0') then
-- make sure the output data is invalid when the link is down and that it will
-- trigger the sync loss detection
ch1_rx_data_o <= (others => '0');
ch1_rx_k_o <= '1';
ch1_rx_enc_err_o <= '1';
else
ch1_rx_data_o <= ch1_rx_data_int;
ch1_rx_k_o <= ch1_rx_k_int;
ch1_rx_enc_err_o <= ch1_rx_disperr or ch1_rx_invcode;
end if;
end if;
end process;
-- drive the recovered clock output
ch0_rx_rbclk_o <= ch0_rx_rec_clk;
-- ch0_tx_disparity_o <= ch0_tx_rundisp_vec(0);
ch1_rx_rbclk_o <= ch1_rx_rec_clk;
-- ch1_tx_disparity_o <= ch1_tx_rundisp_vec(0);
end rtl;
hdl/golden/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd deleted 100644 → 0
View file @ a465c3cc
library ieee;
use ieee.std_logic_1164.all;
entity wr_gtp_phy_spec_wrapper is
generic (
g_simulation : integer := 0);
port(
sfp_ref_clk_i : in std_logic;
sfp_ref_clk_o : out std_logic;
sfp_tx_data_i : in std_logic_vector(7 downto 0);
sfp_tx_k_i : in std_logic;
sfp_tx_disparity_o : out std_logic;
sfp_tx_enc_err_o : out std_logic;
sfp_rx_rbclk_o : out std_logic;
sfp_rx_data_o : out std_logic_vector(7 downto 0);
sfp_rx_k_o : out std_logic;
sfp_rx_enc_err_o : out std_logic;
sfp_rx_bitslide_o : out std_logic_vector(3 downto 0);
sfp_rst_i : in std_logic;
sfp_loopen_i : in std_logic;
sfp_txn_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_rxn_i : in std_logic;
sfp_rxp_i : in std_logic;
sata0_ref_clk_i : in std_logic;
sata0_ref_clk_o : out std_logic;
sata0_tx_data_i : in std_logic_vector(7 downto 0);
sata0_tx_k_i : in std_logic;
sata0_tx_disparity_o : out std_logic;
sata0_tx_enc_err_o : out std_logic;
sata0_rx_rbclk_o : out std_logic;
sata0_rx_data_o : out std_logic_vector(7 downto 0);
sata0_rx_k_o : out std_logic;
sata0_rx_enc_err_o : out std_logic;
sata0_rx_bitslide_o : out std_logic_vector(3 downto 0);
sata0_rst_i : in std_logic;
sata0_loopen_i : in std_logic;
sata0_txn_o : out std_logic;
sata0_txp_o : out std_logic;
sata0_rxn_i : in std_logic;
sata0_rxp_i : in std_logic;
sata1_ref_clk_i : in std_logic;
sata1_ref_clk_o : out std_logic;
sata1_tx_data_i : in std_logic_vector(7 downto 0);
sata1_tx_k_i : in std_logic;
sata1_tx_disparity_o : out std_logic;
sata1_tx_enc_err_o : out std_logic;
sata1_rx_rbclk_o : out std_logic;
sata1_rx_data_o : out std_logic_vector(7 downto 0);
sata1_rx_k_o : out std_logic;
sata1_rx_enc_err_o : out std_logic;
sata1_rx_bitslide_o : out std_logic_vector(3 downto 0);
sata1_rst_i : in std_logic;
sata1_loopen_i : in std_logic;
sata1_txn_o : out std_logic;
sata1_txp_o : out std_logic;
sata1_rxn_i : in std_logic;
sata1_rxp_i : in std_logic;
fmc_ref_clk_i : in std_logic;
fmc_ref_clk_o : out std_logic;
fmc_tx_data_i : in std_logic_vector(7 downto 0);
fmc_tx_k_i : in std_logic;
fmc_tx_disparity_o : out std_logic;
fmc_tx_enc_err_o : out std_logic;
fmc_rx_rbclk_o : out std_logic;
fmc_rx_data_o : out std_logic_vector(7 downto 0);
fmc_rx_k_o : out std_logic;
fmc_rx_enc_err_o : out std_logic;
fmc_rx_bitslide_o : out std_logic_vector(3 downto 0);
fmc_rst_i : in std_logic;
fmc_loopen_i : in std_logic;
fmc_txn_o : out std_logic;
fmc_txp_o : out std_logic;
fmc_rxn_i : in std_logic;
fmc_rxp_i : in std_logic
);
end wr_gtp_phy_spec_wrapper;
architecture rtl of wr_gtp_phy_spec_wrapper is
component wr_gtp_phy_spartan6
generic (
g_simulation : integer);
port (
ch0_ref_clk_i : in std_logic;
ch0_ref_clk_o : out std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_ref_clk_o : out std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
begin -- rtl
U_GTP1 : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation)
port map (
ch0_ref_clk_i => fmc_ref_clk_i,
ch0_ref_clk_o => fmc_ref_clk_o,
ch0_tx_data_i => fmc_tx_data_i,
ch0_tx_k_i => fmc_tx_k_i,
ch0_tx_disparity_o => fmc_tx_disparity_o,
ch0_tx_enc_err_o => fmc_tx_enc_err_o,
ch0_rx_rbclk_o => fmc_rx_rbclk_o,
ch0_rx_data_o => fmc_rx_data_o,
ch0_rx_k_o => fmc_rx_k_o,
ch0_rx_enc_err_o => fmc_rx_enc_err_o,
ch0_rx_bitslide_o => fmc_rx_bitslide_o,
ch0_rst_i => fmc_rst_i,
ch0_loopen_i => fmc_loopen_i,
ch1_ref_clk_i => sata0_ref_clk_i,
ch1_ref_clk_o => sata0_ref_clk_o,
ch1_tx_data_i => sata0_tx_data_i,
ch1_tx_k_i => sata0_tx_k_i,
ch1_tx_disparity_o => sata0_tx_disparity_o,
ch1_tx_enc_err_o => sata0_tx_enc_err_o,
ch1_rx_data_o => sata0_rx_data_o,
ch1_rx_rbclk_o => sata0_rx_rbclk_o,
ch1_rx_k_o => sata0_rx_k_o,
ch1_rx_enc_err_o => sata0_rx_enc_err_o,
ch1_rx_bitslide_o => sata0_rx_bitslide_o,
ch1_rst_i => sata0_rst_i,
ch1_loopen_i => sata0_loopen_i,
pad_txn0_o => fmc_txn_o,
pad_txp0_o => fmc_txp_o,
pad_rxn0_i => fmc_rxn_i,
pad_rxp0_i => fmc_rxp_i,
pad_txn1_o => sata0_txn_o,
pad_txp1_o => sata0_txp_o,
pad_rxn1_i => sata0_rxn_i,
pad_rxp1_i => sata0_rxp_i);
U_GTP2 : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation)
port map (
ch0_ref_clk_i => sata1_ref_clk_i,
ch0_ref_clk_o => sata1_ref_clk_o,
ch0_tx_data_i => sata1_tx_data_i,
ch0_tx_k_i => sata1_tx_k_i,
ch0_tx_disparity_o => sata1_tx_disparity_o,
ch0_tx_enc_err_o => sata1_tx_enc_err_o,
ch0_rx_rbclk_o => sata1_rx_rbclk_o,
ch0_rx_data_o => sata1_rx_data_o,
ch0_rx_k_o => sata1_rx_k_o,
ch0_rx_enc_err_o => sata1_rx_enc_err_o,
ch0_rx_bitslide_o => sata1_rx_bitslide_o,
ch0_rst_i => sata1_rst_i,
ch0_loopen_i => sata1_loopen_i,
ch1_ref_clk_i => sfp_ref_clk_i,
ch1_ref_clk_o => sfp_ref_clk_o,
ch1_tx_data_i => sfp_tx_data_i,
ch1_tx_k_i => sfp_tx_k_i,
ch1_tx_disparity_o => sfp_tx_disparity_o,
ch1_tx_enc_err_o => sfp_tx_enc_err_o,
ch1_rx_data_o => sfp_rx_data_o,
ch1_rx_rbclk_o => sfp_rx_rbclk_o,
ch1_rx_k_o => sfp_rx_k_o,
ch1_rx_enc_err_o => sfp_rx_enc_err_o,
ch1_rx_bitslide_o => sfp_rx_bitslide_o,
ch1_rst_i => sfp_rst_i,
ch1_loopen_i => sfp_loopen_i,
pad_txn0_o => sata1_txn_o,
pad_txp0_o => sata1_txp_o,
pad_rxn0_i => sata1_rxn_i,
pad_rxp0_i => sata1_rxp_i,
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
end rtl;
hdl/golden/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd deleted 100644 → 0
View file @ a465c3cc
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - Spartan-6 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gtp_phy_spartan6.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2012-03-29
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual channel wrapper for Xilinx Spartan-6 GTP adapted for
-- deterministic delays at 1.25 Gbps.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN / Tomasz Wlostowski
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Initial release
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP (single channel only)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
entity wr_gtx_phy_virtex6 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 0;
g_use_slave_tx_clock : integer := 0
);
port (
-- Reference 62.5 MHz clock input for the TX/RX logic (not the GTX itself)
clk_ref_i : in std_logic;
-- Reference 62.5 MHz clock for the GTX transceiver
clk_gtx_i : in std_logic;
-- TX path, clk_ref_i - synchronous:
-- data input (8 bits, not 8b10b-encoded)
tx_data_i : in std_logic_vector(15 downto 0);
-- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_k_i : in std_logic_vector(1 downto 0);
-- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
-- Necessary for the PCS to generate proper frame termination sequences.
-- Generated for the 2nd byte (LSB) of tx_data_i.
tx_disparity_o : out std_logic;
-- Encoding error indication (1 = error, 0 = no error)
tx_enc_err_o : out std_logic;
-- RX path, synchronous to ch0_rx_rbclk_o.
-- RX recovered clock
rx_rbclk_o : out std_logic;
-- 8b10b-decoded data output. The data output must be kept invalid before
-- the transceiver is locked on the incoming signal to prevent the EP from
-- detecting a false carrier.
rx_data_o : out std_logic_vector(15 downto 0);
-- 1 when the byte on rx_data_o is a control code
rx_k_o : out std_logic_vector(1 downto 0);
-- encoding error indication
rx_enc_err_o : out std_logic;
-- RX bitslide indication, indicating the delay of the RX path of the
-- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
rx_bitslide_o : out std_logic_vector(4 downto 0);
-- reset input, active hi
rst_i : in std_logic;
loopen_i : in std_logic;
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0'
);
end wr_gtx_phy_virtex6;
architecture rtl of wr_gtx_phy_virtex6 is
component WHITERABBITGTX_WRAPPER_GTX
generic (
GTX_SIM_GTXRESET_SPEEDUP : integer;
GTX_TX_CLK_SOURCE : string;
GTX_POWER_SAVE : bit_vector);
port (
LOOPBACK_IN : in std_logic_vector(2 downto 0);
RXCHARISK_OUT : out std_logic_vector(1 downto 0);
RXDISPERR_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
RXBYTEISALIGNED_OUT : out std_logic;
RXCOMMADET_OUT : out std_logic;
RXSLIDE_IN : in std_logic;
RXDATA_OUT : out std_logic_vector(15 downto 0);
RXRECCLK_OUT : out std_logic;
RXUSRCLK2_IN : in std_logic;
RXCDRRESET_IN : in std_logic;
RXN_IN : in std_logic;
RXP_IN : in std_logic;
GTXRXRESET_IN : in std_logic;
MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
PLLRXRESET_IN : in std_logic;
RXPLLLKDET_OUT : out std_logic;
RXRESETDONE_OUT : out std_logic;
TXCHARISK_IN : in std_logic_vector(1 downto 0);
GTXTEST_IN : in std_logic_vector(12 downto 0);
TXDATA_IN : in std_logic_vector(15 downto 0);
TXOUTCLK_OUT : out std_logic;
TXUSRCLK2_IN : in std_logic;
TXRUNDISP_OUT : out std_logic_vector(1 downto 0);
TXN_OUT : out std_logic;
TXP_OUT : out std_logic;
TXDLYALIGNDISABLE_IN : in std_logic;
TXDLYALIGNMONENB_IN : in std_logic;
TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
TXDLYALIGNRESET_IN : in std_logic;
TXENPMAPHASEALIGN_IN : in std_logic;
TXPMASETPHASE_IN : in std_logic;
GTXTXRESET_IN : in std_logic;
MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
PLLTXRESET_IN : in std_logic;
TXPLLLKDET_OUT : out std_logic;
TXRESETDONE_OUT : out std_logic);
end component;
component BUFG
port (
O : out std_ulogic;
I : in std_ulogic);
end component;
component BUFR
generic (
BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "VIRTEX6");
port (
O : out std_ulogic;
CE : in std_ulogic := '1';
CLR : in std_ulogic := '0';
I : in std_ulogic);
end component;
component gtp_phase_align_virtex6
generic (
g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
gtp_tx_dly_align_disable_o : out std_logic;
gtp_tx_dly_align_reset_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic);
end component;
component gtp_bitslide
generic (
g_simulation : integer;
g_target : string := "virtex6");
port (
gtp_rst_i : in std_logic;
gtp_rx_clk_i : in std_logic;
gtp_rx_comma_det_i : in std_logic;
gtp_rx_byte_is_aligned_i : in std_logic;
serdes_ready_i : in std_logic;
gtp_rx_slide_o : out std_logic;
gtp_rx_cdr_rst_o : out std_logic;
bitslide_o : out std_logic_vector(4 downto 0);
synced_o : out std_logic);
end component;
component gtx_reset
port (
clk_tx_i : in std_logic;
rst_i : in std_logic;
txpll_lockdet_i : in std_logic;
gtx_test_o : out std_logic_vector(12 downto 0));
end component;
signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
signal gtx_rst : std_logic;
signal gtx_loopback : std_logic_vector(2 downto 0) := "000";
signal gtx_reset_done : std_logic;
signal gtx_pll_lockdet : std_logic;
signal rst_synced : std_logic;
signal rst_d0 : std_logic;
signal reset_counter : unsigned(9 downto 0);
signal gtx_test : std_logic_vector(12 downto 0);
signal rx_rec_clk_bufin : std_logic;
signal rx_rec_clk : std_logic;
signal rx_comma_det : std_logic;
signal rx_byte_is_aligned : std_logic;
signal tx_dly_align_disable : std_logic;
signal tx_dly_align_reset : std_logic;
signal tx_en_pma_phase_align : std_logic;
signal tx_pma_set_phase : std_logic;
signal align_enable : std_logic;
signal align_done : std_logic;
signal tx_rst_done, rx_rst_done : std_logic;
signal txpll_lockdet, rxpll_lockdet : std_logic;
signal pll_lockdet : std_logic;
signal serdes_ready : std_logic;
signal rx_slide : std_logic;
signal rx_cdr_rst : std_logic;
signal rx_synced : std_logic;
signal rst_done : std_logic;
signal everything_ready : std_logic;
signal mgtrefclk_in : std_logic_vector(1 downto 0);
signal rx_k_int : std_logic_vector(1 downto 0);
signal rx_data_int : std_logic_vector(15 downto 0);
signal rx_disp_err, rx_code_err : std_logic_vector(1 downto 0);
signal tx_is_k_swapped : std_logic_vector(1 downto 0);
signal tx_data_swapped : std_logic_vector(15 downto 0);
signal cur_disp : t_8b10b_disparity;
signal tx_rundisp_v6 : std_logic_vector(1 downto 0);
begin -- rtl
tx_enc_err_o <= '0';
p_gen_reset : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
rst_d0 <= rst_i;
rst_synced <= rst_d0;
if(rst_synced = '1') then
reset_counter <= (others => '0');
else
if(reset_counter(reset_counter'left) = '0') then
reset_counter <= reset_counter + 1;
end if;
end if;
end if;
end process;
gtx_rst <= rst_synced or std_logic(not reset_counter(reset_counter'left));
U_Twice_Reset_Gen : gtx_reset
port map (
clk_tx_i => clk_ref_i,
rst_i => gtx_rst,
txpll_lockdet_i => txpll_lockdet,
gtx_test_o => gtx_test);
U_BUF_RxRecClk : BUFG
port map (
I => rx_rec_clk_bufin,
O => rx_rec_clk);
rx_rbclk_o <= rx_rec_clk;
tx_is_k_swapped <= tx_k_i(0) & tx_k_i(1);
tx_data_swapped <= tx_data_i(7 downto 0) & tx_data_i(15 downto 8);
U_GTX_INST : WHITERABBITGTX_WRAPPER_GTX
generic map (
GTX_SIM_GTXRESET_SPEEDUP => 1,
GTX_TX_CLK_SOURCE => "TXPLL",
GTX_POWER_SAVE => "0000110000")
port map (
LOOPBACK_IN => gtx_loopback,
RXCHARISK_OUT => rx_k_int,
RXDISPERR_OUT => rx_disp_err,
RXNOTINTABLE_OUT => rx_code_err,
RXBYTEISALIGNED_OUT => rx_byte_is_aligned,
RXCOMMADET_OUT => rx_comma_det,
RXSLIDE_IN => rx_slide,
RXDATA_OUT => rx_data_int,
RXRECCLK_OUT => rx_rec_clk_bufin,
RXUSRCLK2_IN => rx_rec_clk,
RXCDRRESET_IN => rx_cdr_rst,
RXN_IN => pad_rxn_i,
RXP_IN => pad_rxp_i,
GTXRXRESET_IN => gtx_rst,
MGTREFCLKRX_IN => mgtrefclk_in,
PLLRXRESET_IN => '0',
RXPLLLKDET_OUT => rxpll_lockdet,
RXRESETDONE_OUT => rx_rst_done,
TXCHARISK_IN => tx_is_k_swapped,
GTXTEST_IN => gtx_test,
TXDATA_IN => tx_data_swapped,
TXOUTCLK_OUT => open,
TXUSRCLK2_IN => clk_ref_i,
TXRUNDISP_OUT => tx_rundisp_v6,
TXN_OUT => pad_txn_o,
TXP_OUT => pad_txp_o,
TXDLYALIGNDISABLE_IN => tx_dly_align_disable,
TXDLYALIGNMONENB_IN => '1',
TXDLYALIGNMONITOR_OUT => open,
TXDLYALIGNRESET_IN => tx_dly_align_reset,
TXENPMAPHASEALIGN_IN => tx_en_pma_phase_align,
TXPMASETPHASE_IN => tx_pma_set_phase,
GTXTXRESET_IN => gtx_rst,
MGTREFCLKTX_IN => mgtrefclk_in,
PLLTXRESET_IN => '0',
TXPLLLKDET_OUT => txpll_lockdet,
TXRESETDONE_OUT => tx_rst_done);
mgtrefclk_in <= '0' & clk_gtx_i;
U_Phase_Align : gtp_phase_align_virtex6
generic map (
g_simulation => g_simulation)
port map (
gtp_rst_i => gtx_rst,
gtp_tx_clk_i => clk_ref_i,
gtp_tx_en_pma_phase_align_o => tx_en_pma_phase_align,
gtp_tx_pma_set_phase_o => tx_pma_set_phase,
gtp_tx_dly_align_disable_o => tx_dly_align_disable,
gtp_tx_dly_align_reset_o => tx_dly_align_reset,
align_en_i => align_enable,
align_done_o => align_done);
U_Bitslide : gtp_bitslide
generic map (
g_simulation => g_simulation,
g_target => "virtex6")
port map (
gtp_rst_i => gtx_rst,
gtp_rx_clk_i => rx_rec_clk,
gtp_rx_comma_det_i => rx_comma_det,
gtp_rx_byte_is_aligned_i => rx_byte_is_aligned,
serdes_ready_i => everything_ready,
gtp_rx_slide_o => rx_slide,
gtp_rx_cdr_rst_o => rx_cdr_rst,
bitslide_o => rx_bitslide_o,
synced_o => rx_synced);
rst_done <= rx_rst_done and tx_rst_done;
pll_lockdet <= txpll_lockdet and rxpll_lockdet;
serdes_ready <= rst_done and pll_lockdet;
align_enable <= serdes_ready;
everything_ready <= serdes_ready and align_done;
trig2(3) <= rx_rst_done;
trig2(4) <= tx_rst_done;
trig2(5) <= txpll_lockdet;
trig2(6) <= rxpll_lockdet;
trig2(7) <= align_done;
p_gen_rx_outputs : process(rx_rec_clk, gtx_rst)
begin
if(gtx_rst = '1') then
rx_data_o <= (others => '0');
rx_k_o <= (others => '0');
rx_enc_err_o <= '0';
elsif rising_edge(rx_rec_clk) then
if(everything_ready = '1' and rx_synced = '1') then
rx_data_o <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
rx_k_o <= rx_k_int(0) & rx_k_int(1);
rx_enc_err_o <= rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
else
rx_data_o <= (others => '1');
rx_k_o <= (others => '1');
rx_enc_err_o <= '1';
end if;
end if;
end process;
p_gen_tx_disparity : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if gtx_rst = '1' then
cur_disp <= RD_MINUS;
else
cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
end if;
end if;
end process;
tx_disparity_o <= to_std_logic(cur_disp);
end rtl;
hdl/golden/platform/xilinx/wr_xilinx_pkg.vhd deleted 100644 → 0
View file @ a465c3cc
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
package wr_xilinx_pkg is
component wr_gtp_phy_spartan6
generic (
g_simulation : integer);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
end wr_xilinx_pkg;
hdl/golden/syn/Makefile deleted 100644 → 0
View file @ a465c3cc
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := spec_init.xise
ISE_CRAP := *.b spec_init_summary.html *.tcl spec_init.bld spec_init.cmd_log *.drc spec_init.lso *.ncd spec_init.ngc spec_init.ngd spec_init.ngr spec_init.pad spec_init.par spec_init.pcf spec_init.prj spec_init.ptwx spec_init.stx spec_init.syr spec_init.twr spec_init.twx spec_init.gise spec_init.unroutes spec_init.ut spec_init.xpi spec_init.xst spec_init_bitgen.xwbt spec_init_envsettings.html spec_init_guide.ncd spec_init_map.map spec_init_map.mrp spec_init_map.ncd spec_init_map.ngm spec_init_map.xrpt spec_init_ngdbuild.xrpt spec_init_pad.csv spec_init_pad.txt spec_init_par.xrpt spec_init_summary.xml spec_init_usage.xml spec_init_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
hdl/golden/syn/Manifest.py deleted 100644 → 0
View file @ a465c3cc
target = "xilinx"
action = "synthesis"
fetchto = "../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_init.xise"
syn_tool = "ise"
syn_top = "spec_init"
modules = { "local" : "../top",
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git::proposed_master",
"git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
"git://ohwr.org/hdl-core-lib/gn4124-core.git::proposed_master" ]
}
hdl/golden/syn/spec_init.xise deleted 100644 → 0
View file @ a465c3cc
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_init" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_init" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spec_init" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_init_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_init_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_init_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_init_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="spec_init" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-20T23:41:13" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E0496400DE2980DA4D056936A6C620B6" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</libraries>
<files>
<file xil_pn:name="../top/spec_init.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="221"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="222"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="223"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="224"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="225"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="226"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="227"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="229"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="230"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="232"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="233"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="234"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="235"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="236"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="237"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="238"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="239"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="240"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="241"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="242"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="243"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="244"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="245"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="246"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="247"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="248"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="249"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="250"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="251"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="252"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="253"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="254"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="255"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="256"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="257"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="258"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="259"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="260"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="261"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="262"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="263"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="264"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="265"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="266"/>
</file>
<file xil_pn:name="../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="267"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="268"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="269"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="270"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="271"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="272"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="273"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="274"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="275"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="276"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
</project>
hdl/golden/top/Manifest.py deleted 100644 → 0
View file @ a465c3cc
files = ["spec_init.vhd", "spec_init.ucf"]
hdl/golden/top/spec_init.ucf deleted 100644 → 0
View file @ a465c3cc
#bank 0
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "SFP_MOD_DEF1_b" LOC = C17;
NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_b" LOC = G15;
NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF2_b" LOC = G16;
NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_b" LOC = H14;
NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_FAULT_i" LOC = A17;
NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_DISABLE_o" LOC = F17;
NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
NET "SFP_LOS_i" LOC = D18;
NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
NET "FPGA_SCL_B" LOC = F7;
NET "FPGA_SCL_B" IOSTANDARD = "LVCMOS25";
NET "FPGA_SDA_B" LOC = F8;
NET "FPGA_SDA_B" IOSTANDARD = "LVCMOS25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "SPI_NCS_O" LOC = AA3;
NET "SPI_NCS_O" IOSTANDARD = "LVCMOS25";
NET "SPI_SCLK_O" LOC = Y20;
NET "SPI_SCLK_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MOSI_O" LOC = AB20;
NET "SPI_MOSI_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MISO_I" LOC = AA20;
NET "SPI_MISO_I" IOSTANDARD = "LVCMOS25";
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
#---------------------------------------------------------------------------------------------
# False Path
#---------------------------------------------------------------------------------------------
# GN4124
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
hdl/golden/top/spec_init.vhd deleted 100644 → 0
View file @ a465c3cc
-------------------------------------------------------------------------------
-- Title : SPEC Golden Binary
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : spec_init.vhd
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-07-17
-- Last update: 2012-11-20
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Copyright (c) 2012 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-07-17 1.0 greg.d Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_xilinx_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
entity spec_init is
generic
(
TAR_ADDR_WDTH : integer := 13 -- not used for this project
);
port
(
-- Global ports
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-- Font panel LEDs
LED_RED : out std_logic;
LED_GREEN : out std_logic;
fpga_scl_b : inout std_logic;
fpga_sda_b : inout std_logic;
button1_i : in std_logic;
button2_i : in std_logic;
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
-------------------------------------------------------------------------
-- SFP pins
-------------------------------------------------------------------------
sfp_mod_def0_b : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_b : inout std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic
);
end spec_init;
architecture rtl of spec_init is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal pllout_clk_sys : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_sys : std_logic;
signal wrc_scl_o : std_logic;
signal wrc_scl_i : std_logic;
signal wrc_sda_o : std_logic;
signal wrc_sda_i : std_logic;
signal sfp_scl_o : std_logic;
signal sfp_scl_i : std_logic;
signal sfp_sda_o : std_logic;
signal sfp_sda_i : std_logic;
signal genum_wb_out : t_wishbone_master_out;
signal genum_wb_in : t_wishbone_master_in;
signal wb_adr : std_logic_vector(31 downto 0); --c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
constant c_sdb_address : t_wishbone_address := x"00000100";
constant c_layout : t_sdb_record := f_sdb_embed_device(c_wrc_periph0_sdb, x"00000000");
------------------------------------
signal periph_slv_in : t_wishbone_slave_in_array(0 to 2);
signal periph_slv_out: t_wishbone_slave_out_array(0 to 2);
begin
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => L_RST_N,
status_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
-- L2P Control
l2p_edb_o => L2P_EDB,
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => GPIO(0),
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => clk_sys,
dma_reg_adr_i => (others=>'0'),
dma_reg_dat_i => (others=>'0'),
dma_reg_sel_i => (others=>'0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0',
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => clk_sys,
csr_adr_o => wb_adr,
csr_dat_o => genum_wb_out.dat,
csr_sel_o => genum_wb_out.sel,
csr_stb_o => genum_wb_out.stb,
csr_we_o => genum_wb_out.we,
csr_cyc_o => genum_wb_out.cyc,
csr_dat_i => genum_wb_in.dat,
csr_ack_i => genum_wb_in.ack,
csr_stall_i => genum_wb_in.stall,
csr_err_i => genum_wb_in.err,
csr_rty_i => genum_wb_in.rty,
csr_int_i => genum_wb_in.int,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
dma_clk_i => clk_sys,
dma_dat_i => (others=>'0'),
dma_ack_i => '1',
dma_stall_i => '0',
dma_err_i => '0',
dma_rty_i => '0',
dma_int_i => '0');
genum_wb_out.adr( 1 downto 0) <= (others => '0');
genum_wb_out.adr(18 downto 2) <= wb_adr(16 downto 0);
genum_wb_out.adr(31 downto 19) <= (others => '0');
fpga_scl_b <= '0' when wrc_scl_o = '0' else 'Z';
fpga_sda_b <= '0' when wrc_sda_o = '0' else 'Z';
wrc_scl_i <= fpga_scl_b;
wrc_sda_i <= fpga_sda_b;
sfp_mod_def1_b <= '0' when sfp_scl_o = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_o = '0' else 'Z';
sfp_scl_i <= sfp_mod_def1_b;
sfp_sda_i <= sfp_mod_def2_b;
PERIPH: wrc_periph
generic map(
g_phys_uart => false,
g_virtual_uart => true
)
port map(
clk_sys_i => clk_sys,
rst_n_i => L_RST_N,
led_red_o => LED_RED,
led_green_o => LED_GREEN,
scl_o => wrc_scl_o,
scl_i => wrc_scl_i,
sda_o => wrc_sda_o,
sda_i => wrc_sda_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_mod_def0_b,
memsize_i => "0000",
btn1_i => button1_i,
btn2_i => button2_i,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
slave_i => periph_slv_in,
slave_o => periph_slv_out,
uart_rxd_i => '0',
owr_i => (others=>'1')
);
periph_slv_in(1).cyc <= '0';
periph_slv_in(1).stb <= '0';
periph_slv_in(1).we <= '0';
periph_slv_in(1).adr <= (others=>'0');
periph_slv_in(1).sel <= (others=>'0');
periph_slv_in(1).dat <= (others=>'0');
periph_slv_in(2).cyc <= '0';
periph_slv_in(2).stb <= '0';
periph_slv_in(2).we <= '0';
periph_slv_in(2).adr <= (others=>'0');
periph_slv_in(2).sel <= (others=>'0');
periph_slv_in(2).dat <= (others=>'0');
---------------------
WB_CON: xwb_sdb_crossbar
generic map(
g_num_masters => 1,
g_num_slaves => 1,
g_registered => true,
g_wraparound => true,
g_layout(0) => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => L_RST_N,
slave_i(0) => genum_wb_out,
slave_o(0) => genum_wb_in,
master_i(0) => periph_slv_out(0),
master_o(0) => periph_slv_in(0)
);
sfp_tx_disable_o <= '0';
end rtl;
hdl/rtl/Manifest.py 0 → 100644
View file @ 204ff681
files = ["spec_base_regs.vhd", "spec_base_wr.vhd"]
hdl/rtl/spec_base_regs.cheby 0 → 100644
View file @ 204ff681
memory-map:
name: spec_base_regs
bus: wb-32-be
size: 0x2000
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
size: 0x40
interface: sram
- block:
name: csr
description: carrier and fmc status and control
address: 0x40
children:
- reg:
name: app_offset
description: offset to the application metadata
access: ro
width: 32
- reg:
name: resets
description: global and application resets
access: rw
width: 32
children:
- field:
name: global
range: 0
- field:
name: appl
range: 1
- reg:
name: fmc_presence
description: presence lines for the fmcs
access: ro
width: 32
- reg:
name: gn4124_status
description: status of gennum
access: ro
width: 32
# field 0: pll locked.
- reg:
name: ddr_status
description: status of the ddr3 controller
access: ro
width: 32
children:
- field:
description: Set when calibration is done.
name: calib_done
range: 0
- reg:
name: pcb_rev
description: pcb revision
access: ro
width: 32
children:
- field:
name: rev
range: 3-0
- submap:
name: therm_id
description: Thermometer and unique id
address: 0x70
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: fmc_i2c
description: i2c controllers to the fmcs
address: 0x80
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: flash_spi
description: spi controller to the flash
address: 0xa0
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: dma
description: dma registers for the gennum core
address: 0xc0
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: vic
description: vector interrupt controller
address: 0x100
size: 0x100
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: buildinfo
description: a ROM containing build information
size: 0x100
interface: sram
- submap:
name: wrc_regs
address: 0x1000
description: white-rabbit core registers
size: 0x1000
interface: wb-32-be
x-hdl:
busgroup: True
hdl/rtl/spec_base_regs.vhd 0 → 100644
View file @ 204ff681
-- Do not edit; this file was generated by Cheby using these options:
-- --gen-hdl=spec_base_regs.vhd -i spec_base_regs.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_base_regs is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_adr_i : in std_logic_vector(12 downto 2);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_dat_i : in std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(31 downto 0);
-- a ROM containing the carrier metadata
metadata_addr_o : out std_logic_vector(5 downto 2);
metadata_data_i : in std_logic_vector(31 downto 0);
metadata_data_o : out std_logic_vector(31 downto 0);
metadata_wr_o : out std_logic;
-- offset to the application metadata
csr_app_offset_i : in std_logic_vector(31 downto 0);
csr_resets_global_o : out std_logic;
csr_resets_appl_o : out std_logic;
-- presence lines for the fmcs
csr_fmc_presence_i : in std_logic_vector(31 downto 0);
-- status of gennum
csr_gn4124_status_i : in std_logic_vector(31 downto 0);
-- Set when calibration is done.
csr_ddr_status_calib_done_i : in std_logic;
csr_pcb_rev_rev_i : in std_logic_vector(3 downto 0);
-- Thermometer and unique id
therm_id_i : in t_wishbone_master_in;
therm_id_o : out t_wishbone_master_out;
-- i2c controllers to the fmcs
fmc_i2c_i : in t_wishbone_master_in;
fmc_i2c_o : out t_wishbone_master_out;
-- spi controller to the flash
flash_spi_i : in t_wishbone_master_in;
flash_spi_o : out t_wishbone_master_out;
-- dma registers for the gennum core
dma_i : in t_wishbone_master_in;
dma_o : out t_wishbone_master_out;
-- vector interrupt controller
vic_i : in t_wishbone_master_in;
vic_o : out t_wishbone_master_out;
-- a ROM containing build information
buildinfo_addr_o : out std_logic_vector(7 downto 2);
buildinfo_data_i : in std_logic_vector(31 downto 0);
buildinfo_data_o : out std_logic_vector(31 downto 0);
buildinfo_wr_o : out std_logic;
-- white-rabbit core registers
wrc_regs_i : in t_wishbone_master_in;
wrc_regs_o : out t_wishbone_master_out
);
end spec_base_regs;
architecture syn of spec_base_regs is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_rack : std_logic;
signal metadata_re : std_logic;
signal csr_resets_global_reg : std_logic;
signal csr_resets_appl_reg : std_logic;
signal therm_id_re : std_logic;
signal therm_id_wt : std_logic;
signal therm_id_rt : std_logic;
signal therm_id_tr : std_logic;
signal therm_id_wack : std_logic;
signal therm_id_rack : std_logic;
signal fmc_i2c_re : std_logic;
signal fmc_i2c_wt : std_logic;
signal fmc_i2c_rt : std_logic;
signal fmc_i2c_tr : std_logic;
signal fmc_i2c_wack : std_logic;
signal fmc_i2c_rack : std_logic;
signal flash_spi_re : std_logic;
signal flash_spi_wt : std_logic;
signal flash_spi_rt : std_logic;
signal flash_spi_tr : std_logic;
signal flash_spi_wack : std_logic;
signal flash_spi_rack : std_logic;
signal dma_re : std_logic;
signal dma_wt : std_logic;
signal dma_rt : std_logic;
signal dma_tr : std_logic;
signal dma_wack : std_logic;
signal dma_rack : std_logic;
signal vic_re : std_logic;
signal vic_wt : std_logic;
signal vic_rt : std_logic;
signal vic_tr : std_logic;
signal vic_wack : std_logic;
signal vic_rack : std_logic;
signal buildinfo_rack : std_logic;
signal buildinfo_re : std_logic;
signal wrc_regs_re : std_logic;
signal wrc_regs_wt : std_logic;
signal wrc_regs_rt : std_logic;
signal wrc_regs_tr : std_logic;
signal wrc_regs_wack : std_logic;
signal wrc_regs_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_cyc_i and wb_stb_i;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_we_i)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_we_i) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_we_i)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_we_i) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_ack_o <= ack_int;
wb_stall_o <= not ack_int and wb_en;
wb_rty_o <= '0';
wb_err_o <= '0';
-- Assign outputs
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rack <= '0';
else
metadata_rack <= metadata_re and not metadata_rack;
end if;
end if;
end process;
metadata_data_o <= wb_dat_i;
metadata_addr_o <= wb_adr_i(5 downto 2);
csr_resets_global_o <= csr_resets_global_reg;
csr_resets_appl_o <= csr_resets_appl_reg;
-- Assignments for submap therm_id
therm_id_tr <= therm_id_wt or therm_id_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
therm_id_rt <= '0';
else
therm_id_rt <= (therm_id_rt or therm_id_re) and not therm_id_rack;
end if;
end if;
end process;
therm_id_o.cyc <= therm_id_tr;
therm_id_o.stb <= therm_id_tr;
therm_id_wack <= therm_id_i.ack and therm_id_wt;
therm_id_rack <= therm_id_i.ack and therm_id_rt;
therm_id_o.adr <= ((27 downto 0 => '0') & wb_adr_i(3 downto 2)) & (1 downto 0 => '0');
therm_id_o.sel <= (others => '1');
therm_id_o.we <= therm_id_wt;
therm_id_o.dat <= wb_dat_i;
-- Assignments for submap fmc_i2c
fmc_i2c_tr <= fmc_i2c_wt or fmc_i2c_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_i2c_rt <= '0';
else
fmc_i2c_rt <= (fmc_i2c_rt or fmc_i2c_re) and not fmc_i2c_rack;
end if;
end if;
end process;
fmc_i2c_o.cyc <= fmc_i2c_tr;
fmc_i2c_o.stb <= fmc_i2c_tr;
fmc_i2c_wack <= fmc_i2c_i.ack and fmc_i2c_wt;
fmc_i2c_rack <= fmc_i2c_i.ack and fmc_i2c_rt;
fmc_i2c_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
fmc_i2c_o.sel <= (others => '1');
fmc_i2c_o.we <= fmc_i2c_wt;
fmc_i2c_o.dat <= wb_dat_i;
-- Assignments for submap flash_spi
flash_spi_tr <= flash_spi_wt or flash_spi_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
flash_spi_rt <= '0';
else
flash_spi_rt <= (flash_spi_rt or flash_spi_re) and not flash_spi_rack;
end if;
end if;
end process;
flash_spi_o.cyc <= flash_spi_tr;
flash_spi_o.stb <= flash_spi_tr;
flash_spi_wack <= flash_spi_i.ack and flash_spi_wt;
flash_spi_rack <= flash_spi_i.ack and flash_spi_rt;
flash_spi_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
flash_spi_o.sel <= (others => '1');
flash_spi_o.we <= flash_spi_wt;
flash_spi_o.dat <= wb_dat_i;
-- Assignments for submap dma
dma_tr <= dma_wt or dma_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dma_rt <= '0';
else
dma_rt <= (dma_rt or dma_re) and not dma_rack;
end if;
end if;
end process;
dma_o.cyc <= dma_tr;
dma_o.stb <= dma_tr;
dma_wack <= dma_i.ack and dma_wt;
dma_rack <= dma_i.ack and dma_rt;
dma_o.adr <= ((25 downto 0 => '0') & wb_adr_i(5 downto 2)) & (1 downto 0 => '0');
dma_o.sel <= (others => '1');
dma_o.we <= dma_wt;
dma_o.dat <= wb_dat_i;
-- Assignments for submap vic
vic_tr <= vic_wt or vic_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
vic_rt <= '0';
else
vic_rt <= (vic_rt or vic_re) and not vic_rack;
end if;
end if;
end process;
vic_o.cyc <= vic_tr;
vic_o.stb <= vic_tr;
vic_wack <= vic_i.ack and vic_wt;
vic_rack <= vic_i.ack and vic_rt;
vic_o.adr <= ((23 downto 0 => '0') & wb_adr_i(7 downto 2)) & (1 downto 0 => '0');
vic_o.sel <= (others => '1');
vic_o.we <= vic_wt;
vic_o.dat <= wb_dat_i;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
buildinfo_rack <= '0';
else
buildinfo_rack <= buildinfo_re and not buildinfo_rack;
end if;
end if;
end process;
buildinfo_data_o <= wb_dat_i;
buildinfo_addr_o <= wb_adr_i(7 downto 2);
-- Assignments for submap wrc_regs
wrc_regs_tr <= wrc_regs_wt or wrc_regs_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wrc_regs_rt <= '0';
else
wrc_regs_rt <= (wrc_regs_rt or wrc_regs_re) and not wrc_regs_rack;
end if;
end if;
end process;
wrc_regs_o.cyc <= wrc_regs_tr;
wrc_regs_o.stb <= wrc_regs_tr;
wrc_regs_wack <= wrc_regs_i.ack and wrc_regs_wt;
wrc_regs_rack <= wrc_regs_i.ack and wrc_regs_rt;
wrc_regs_o.adr <= ((19 downto 0 => '0') & wb_adr_i(11 downto 2)) & (1 downto 0 => '0');
wrc_regs_o.sel <= (others => '1');
wrc_regs_o.we <= wrc_regs_wt;
wrc_regs_o.dat <= wb_dat_i;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
metadata_wr_o <= '0';
csr_resets_global_reg <= '0';
csr_resets_appl_reg <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
dma_wt <= '0';
vic_wt <= '0';
buildinfo_wr_o <= '0';
wrc_regs_wt <= '0';
else
wr_ack_int <= '0';
metadata_wr_o <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
dma_wt <= '0';
vic_wt <= '0';
buildinfo_wr_o <= '0';
wrc_regs_wt <= '0';
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
-- Submap metadata
metadata_wr_o <= wr_int;
wr_ack_int <= wr_int;
when "01" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- Register csr_app_offset
when "01" =>
-- Register csr_resets
if wr_int = '1' then
csr_resets_global_reg <= wb_dat_i(0);
csr_resets_appl_reg <= wb_dat_i(1);
end if;
wr_ack_int <= wr_int;
when "10" =>
-- Register csr_fmc_presence
when "11" =>
-- Register csr_gn4124_status
when others =>
wr_ack_int <= wr_int;
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- Register csr_ddr_status
when "01" =>
-- Register csr_pcb_rev
when others =>
wr_ack_int <= wr_int;
end case;
when "11" =>
-- Submap therm_id
therm_id_wt <= (therm_id_wt or wr_int) and not therm_id_wack;
wr_ack_int <= therm_id_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
-- Submap fmc_i2c
fmc_i2c_wt <= (fmc_i2c_wt or wr_int) and not fmc_i2c_wack;
wr_ack_int <= fmc_i2c_wack;
when "1" =>
-- Submap flash_spi
flash_spi_wt <= (flash_spi_wt or wr_int) and not flash_spi_wack;
wr_ack_int <= flash_spi_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "11" =>
-- Submap dma
dma_wt <= (dma_wt or wr_int) and not dma_wack;
wr_ack_int <= dma_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "0001" =>
-- Submap vic
vic_wt <= (vic_wt or wr_int) and not vic_wack;
wr_ack_int <= vic_wack;
when "0010" =>
-- Submap buildinfo
buildinfo_wr_o <= wr_int;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
when "1" =>
-- Submap wrc_regs
wrc_regs_wt <= (wrc_regs_wt or wr_int) and not wrc_regs_wack;
wr_ack_int <= wrc_regs_wack;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
when "01" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_app_offset
reg_rdat_int <= csr_app_offset_i;
rd_ack1_int <= rd_int;
when "01" =>
-- csr_resets
reg_rdat_int(0) <= csr_resets_global_reg;
reg_rdat_int(1) <= csr_resets_appl_reg;
rd_ack1_int <= rd_int;
when "10" =>
-- csr_fmc_presence
reg_rdat_int <= csr_fmc_presence_i;
rd_ack1_int <= rd_int;
when "11" =>
-- csr_gn4124_status
reg_rdat_int <= csr_gn4124_status_i;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_ddr_status
reg_rdat_int(0) <= csr_ddr_status_calib_done_i;
rd_ack1_int <= rd_int;
when "01" =>
-- csr_pcb_rev
reg_rdat_int(3 downto 0) <= csr_pcb_rev_rev_i;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "11" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
when "1" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "11" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "0001" =>
when "0010" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "1" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
end process;
-- Process for read requests.
process (wb_adr_i, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_data_i, metadata_rack, rd_int, therm_id_i.dat, therm_id_rack, therm_id_rt, rd_int, fmc_i2c_i.dat, fmc_i2c_rack, fmc_i2c_rt, rd_int, flash_spi_i.dat, flash_spi_rack, flash_spi_rt, rd_int, dma_i.dat, dma_rack, dma_rt, rd_int, vic_i.dat, vic_rack, vic_rt, rd_int, buildinfo_data_i, buildinfo_rack, rd_int, wrc_regs_i.dat, wrc_regs_rack, wrc_regs_rt) begin
-- By default ack read requests
wb_dat_o <= (others => '0');
metadata_re <= '0';
therm_id_re <= '0';
fmc_i2c_re <= '0';
flash_spi_re <= '0';
dma_re <= '0';
vic_re <= '0';
buildinfo_re <= '0';
wrc_regs_re <= '0';
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
-- Submap metadata
wb_dat_o <= metadata_data_i;
rd_ack_int <= metadata_rack;
metadata_re <= rd_int;
when "01" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_app_offset
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- csr_resets
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "10" =>
-- csr_fmc_presence
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "11" =>
-- csr_gn4124_status
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_ddr_status
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- csr_pcb_rev
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "11" =>
-- Submap therm_id
therm_id_re <= rd_int;
wb_dat_o <= therm_id_i.dat;
rd_ack_int <= therm_id_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
-- Submap fmc_i2c
fmc_i2c_re <= rd_int;
wb_dat_o <= fmc_i2c_i.dat;
rd_ack_int <= fmc_i2c_rack;
when "1" =>
-- Submap flash_spi
flash_spi_re <= rd_int;
wb_dat_o <= flash_spi_i.dat;
rd_ack_int <= flash_spi_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "11" =>
-- Submap dma
dma_re <= rd_int;
wb_dat_o <= dma_i.dat;
rd_ack_int <= dma_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "0001" =>
-- Submap vic
vic_re <= rd_int;
wb_dat_o <= vic_i.dat;
rd_ack_int <= vic_rack;
when "0010" =>
-- Submap buildinfo
wb_dat_o <= buildinfo_data_i;
rd_ack_int <= buildinfo_rack;
buildinfo_re <= rd_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "1" =>
-- Submap wrc_regs
wrc_regs_re <= rd_int;
wb_dat_o <= wrc_regs_i.dat;
rd_ack_int <= wrc_regs_rack;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
hdl/rtl/spec_base_wr.vhd 0 → 100644
View file @ 204ff681
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_base_wr
--
-- description: SPEC carrier base.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.ddr3_ctrl_pkg.all;
use work.gn4124_core_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
use work.buildinfo_pkg.all;
use work.wr_fabric_pkg.all;
use work.streamers_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity spec_base_wr is
generic (
-- If true, instantiate a VIC/ONEWIRE/SPI/WR/DDRAM+DMA.
g_WITH_VIC : boolean := True;
g_WITH_ONEWIRE : boolean := True;
g_WITH_SPI : boolean := True;
g_WITH_WR : boolean := True;
g_WITH_DDR : boolean := True;
-- Size of the DDR data port in bits (32 or 64)
g_DDR_DATA_SIZE : natural := 64;
-- Address of the application meta-data. 0 if none.
g_APP_OFFSET : std_logic_vector(31 downto 0) := x"0000_0000";
-- Number of user interrupts
g_NUM_USER_IRQ : natural := 1;
-- WR PTP firmware.
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Number of aux clocks syntonized by WRPC to WR timebase
g_AUX_CLKS : integer := 0;
-- Fabric interface selection for WR Core:
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_FABRIC_IFACE : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_STREAMERS_OP_MODE : t_streamers_op_mode := TX_AND_RX;
g_TX_STREAMER_PARAMS : t_tx_streamer_params := c_TX_STREAMER_PARAMS_DEFAUT;
g_RX_STREAMER_PARAMS : t_rx_streamer_params := c_RX_STREAMER_PARAMS_DEFAUT;
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := False;
-- Increase information messages during simulation
g_VERBOSE : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- 125 MHz PLL reference
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
-- 20MHz VCXO clock (for WR)
clk_20m_vcxo_i : in std_logic := '0';
-- 125 MHz GTP reference
clk_125m_gtp_n_i : in std_logic := '0';
clk_125m_gtp_p_i : in std_logic := '0';
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_AUX_CLKS-1 downto 0) := (others => '0');
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- Presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Miscellanous SPEC pins
---------------------------------------------------------------------------
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '0';
sfp_mod_def0_i : in std_logic := '0'; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
------------------------------------------
-- DDR (bank 3)
------------------------------------------
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic;
------------------------------------------
-- User part
------------------------------------------
-- Direct access to the DDR-3
-- Classic wishbone
ddr_dma_clk_i : in std_logic := '0';
ddr_dma_rst_n_i : in std_logic := '0';
ddr_dma_wb_cyc_i : in std_logic := '0';
ddr_dma_wb_stb_i : in std_logic := '0';
ddr_dma_wb_adr_i : in std_logic_vector(31 downto 0) := (others => '0');
ddr_dma_wb_sel_i : in std_logic_vector((g_DDR_DATA_SIZE / 8) - 1 downto 0) := (others => '0');
ddr_dma_wb_we_i : in std_logic := '0';
ddr_dma_wb_dat_i : in std_logic_vector(g_DDR_DATA_SIZE - 1 downto 0) := (others => '0');
ddr_dma_wb_ack_o : out std_logic;
ddr_dma_wb_stall_o : out std_logic;
ddr_dma_wb_dat_o : out std_logic_vector(g_DDR_DATA_SIZE - 1 downto 0);
-- DDR FIFO empty flag
ddr_wr_fifo_empty_o : out std_logic;
-- Clocks and reset.
clk_62m5_sys_o : out std_logic;
rst_62m5_sys_n_o : out std_logic;
clk_125m_ref_o : out std_logic;
rst_125m_ref_n_o : out std_logic;
-- Interrupts
irq_user_i : in std_logic_vector(g_NUM_USER_IRQ + 5 downto 6) := (others => '0');
-- WR fabric interface (when g_fabric_iface = "plain")
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_DUMMY_SRC_IN;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_DUMMY_SNK_IN;
-- WR streamers (when g_fabric_iface = "streamers")
wrs_tx_data_i : in std_logic_vector(g_TX_STREAMER_PARAMS.DATA_WIDTH-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_TX_STREAMER_CFG_DEFAULT;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_RX_STREAMER_CFG_DEFAULT;
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
-- Timecode I/F
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
-- Aux clocks control
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_AUX_CLKS-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_AUX_CLKS-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_AUX_CLKS-1 downto 0);
-- PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic;
-- The wishbone bus from the gennum/host to the application
-- Addresses 0-0x1fff are not available (used by the carrier).
-- This is a pipelined wishbone with byte granularity.
app_wb_o : out t_wishbone_master_out;
app_wb_i : in t_wishbone_master_in
);
end entity spec_base_wr;
architecture top of spec_base_wr is
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
signal clk_62m5_sys : std_logic; -- 62.5Mhz
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
-- DDR
signal clk_333m_ddr : std_logic;
signal rst_333m_ddr_n : std_logic := '0';
signal ddr_rst : std_logic := '1';
signal ddr_status : std_logic_vector(31 downto 0);
signal ddr_calib_done : std_logic;
-- GN4124 core DMA port to DDR wishbone bus
signal gn_wb_ddr_in : t_wishbone_master_in;
signal gn_wb_ddr_out : t_wishbone_master_out;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
-- The wishbone bus to the carrier part.
signal carrier_wb_out : t_wishbone_slave_out;
signal carrier_wb_in : t_wishbone_slave_in;
signal gennum_status : std_logic_vector(31 downto 0);
signal metadata_addr : std_logic_vector(5 downto 2);
signal metadata_data : std_logic_vector(31 downto 0);
signal buildinfo_addr : std_logic_vector(7 downto 2);
signal buildinfo_data : std_logic_vector(31 downto 0);
signal therm_id_in : t_wishbone_master_in;
signal therm_id_out : t_wishbone_master_out;
-- i2c controllers to the fmcs
signal fmc_i2c_in : t_wishbone_master_in;
signal fmc_i2c_out : t_wishbone_master_out;
-- dma registers for the gennum core
signal dma_in : t_wishbone_master_in;
signal dma_out : t_wishbone_master_out;
-- spi controller to the flash
signal flash_spi_in : t_wishbone_master_in;
signal flash_spi_out : t_wishbone_master_out;
-- vector interrupt controller
signal vic_in : t_wishbone_master_in;
signal vic_out : t_wishbone_master_out;
-- white-rabbit core
signal wrc_in : t_wishbone_master_in;
signal wrc_out : t_wishbone_master_out;
signal wrc_out_sh : t_wishbone_master_out;
signal csr_rst_gbl : std_logic;
signal csr_rst_app : std_logic;
signal rst_csr_app_n : std_logic;
signal rst_csr_app_sync_n : std_logic;
signal rst_gbl_n : std_logic;
signal fmc0_scl_out, fmc0_sda_out : std_logic;
signal fmc0_scl_oen, fmc0_sda_oen : std_logic;
signal fmc_presence : std_logic_vector(31 downto 0);
signal irq_master : std_logic;
constant num_interrupts : natural := 6 + g_NUM_USER_IRQ;
signal irqs : std_logic_vector(num_interrupts - 1 downto 0);
-- clock and reset
signal rst_62m5_sys_n : std_logic;
signal rst_125m_ref_n : std_logic;
signal clk_125m_ref : std_logic;
signal clk_10m_ext : std_logic;
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
signal eeprom_sda_out : std_logic;
signal eeprom_scl_in : std_logic;
signal eeprom_scl_out : std_logic;
-- SFP
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- LEDs and GPIO
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
attribute keep : string;
attribute keep of clk_62m5_sys : signal is "TRUE";
attribute keep of clk_125m_ref : signal is "TRUE";
attribute keep of clk_333m_ddr : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE";
begin -- architecture top
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
gn_gpio_b(1) <= 'Z';
cmp_gn4124_core : entity work.xwb_gn4124_core
generic map (
g_WITH_DMA => g_WITH_DDR,
g_WBM_TO_WB_FIFO_SIZE => 16,
g_WBM_TO_WB_FIFO_FULL_THRES => 12,
g_WBM_FROM_WB_FIFO_SIZE => 16,
g_WBM_FROM_WB_FIFO_FULL_THRES => 12,
g_P2L_FIFO_SIZE => 256,
g_P2L_FIFO_FULL_THRES => 175,
g_L2P_ADDR_FIFO_FULL_SIZE => 256,
g_L2P_ADDR_FIFO_FULL_THRES => 175,
g_L2P_DATA_FIFO_FULL_SIZE => 256,
g_L2P_DATA_FIFO_FULL_THRES => 175
)
port map (
---------------------------------------------------------
-- Control and status
rst_n_a_i => gn_rst_n_i,
status_o => gennum_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
-- P2L Control
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
vc_rdy_i => gn_vc_rdy_i,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => gn_l2p_clk_p_o,
l2p_clk_n_o => gn_l2p_clk_n_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
-- L2P Control
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
---------------------------------------------------------
-- Interrupt interface
-- Note: the dma_irq are synchronized with the wb_master_clk clock
-- inside the gn4124 core.
dma_irq_o => irqs(2),
-- Note: this is a simple assignment.
irq_p_i => irq_master,
irq_p_o => gn_gpio_b(0),
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
wb_dma_cfg_clk_i => clk_62m5_sys,
wb_dma_cfg_rst_n_i => rst_62m5_sys_n,
wb_dma_cfg_i => dma_out,
wb_dma_cfg_o => dma_in,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
wb_master_clk_i => clk_62m5_sys,
wb_master_rst_n_i => rst_62m5_sys_n,
wb_master_o => gn_wb_out,
wb_master_i => gn_wb_in,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
wb_dma_dat_clk_i => clk_62m5_sys,
wb_dma_dat_rst_n_i => rst_gbl_n,
wb_dma_dat_o => gn_wb_ddr_out,
wb_dma_dat_i => gn_wb_ddr_in
);
-- Mini-crossbar from gennum to carrier and application bus.
inst_split: entity work.xwb_split
generic map (
g_mask => x"ffff_e000"
)
port map (
clk_sys_i => clk_62m5_sys,
rst_n_i => rst_62m5_sys_n,
slave_i => gn_wb_out,
slave_o => gn_wb_in,
master_i (0) => carrier_wb_out,
master_i (1) => app_wb_i,
master_o (0) => carrier_wb_in,
master_o (1) => app_wb_o
);
inst_devs: entity work.spec_base_regs
port map (
rst_n_i => rst_62m5_sys_n,
clk_i => clk_62m5_sys,
wb_cyc_i => carrier_wb_in.cyc,
wb_stb_i => carrier_wb_in.stb,
wb_adr_i => carrier_wb_in.adr (12 downto 2), -- Bytes address from gennum
wb_sel_i => carrier_wb_in.sel,
wb_we_i => carrier_wb_in.we,
wb_dat_i => carrier_wb_in.dat,
wb_ack_o => carrier_wb_out.ack,
wb_err_o => carrier_wb_out.err,
wb_rty_o => carrier_wb_out.rty,
wb_stall_o => carrier_wb_out.stall,
wb_dat_o => carrier_wb_out.dat,
-- a ROM containing the carrier metadata
metadata_addr_o => metadata_addr,
metadata_data_i => metadata_data,
metadata_data_o => open,
-- offset to the application metadata
csr_app_offset_i => g_APP_OFFSET,
csr_resets_global_o => csr_rst_gbl,
csr_resets_appl_o => csr_rst_app,
-- presence lines for the fmcs
csr_fmc_presence_i => fmc_presence,
csr_gn4124_status_i => gennum_status,
csr_ddr_status_calib_done_i => ddr_calib_done,
csr_pcb_rev_rev_i => pcbrev_i,
-- Thermometer and unique id
therm_id_i => therm_id_in,
therm_id_o => therm_id_out,
-- i2c controllers to the fmcs
fmc_i2c_i => fmc_i2c_in,
fmc_i2c_o => fmc_i2c_out,
-- dma registers for the gennum core
dma_i => dma_in,
dma_o => dma_out,
-- spi controller to the flash
flash_spi_i => flash_spi_in,
flash_spi_o => flash_spi_out,
-- vector interrupt controller
vic_i => vic_in,
vic_o => vic_out,
-- a ROM containing build info
buildinfo_addr_o => buildinfo_addr,
buildinfo_data_i => buildinfo_data,
buildinfo_data_o => open,
-- white-rabbit core
wrc_regs_i => wrc_in,
wrc_regs_o => wrc_out
);
fmc_presence (0) <= not fmc0_prsnt_m2c_n_i;
fmc_presence (31 downto 1) <= (others => '0');
-- Metadata
p_metadata: process (clk_62m5_sys) is
begin
if rising_edge(clk_62m5_sys) then
case metadata_addr is
when x"0" =>
-- Vendor ID
metadata_data <= x"000010dc";
when x"1" =>
-- Device ID
metadata_data <= x"53504543";
when x"2" =>
-- Version
metadata_data <= x"01040000";
when x"3" =>
-- BOM
metadata_data <= x"fffe0000";
when x"4" | x"5" | x"6" | x"7" =>
-- source id
metadata_data <= x"00000000";
when x"8" =>
-- capability mask
metadata_data <= x"00000000";
if g_WITH_VIC then
metadata_data(0) <= '1';
end if;
if g_WITH_ONEWIRE and not g_WITH_WR then
metadata_data(1) <= '1';
end if;
if g_WITH_SPI and not g_WITH_WR then
metadata_data(2) <= '1';
end if;
if g_WITH_WR then
metadata_data(3) <= '1';
end if;
-- Buildinfo
metadata_data(4) <= '1';
if g_WITH_DDR then
metadata_data(5) <= '1';
end if;
when others =>
metadata_data <= x"00000000";
end case;
end if;
end process;
-- Build information
p_buildinfo: process (clk_62m5_sys) is
variable addr : natural;
variable b : std_logic_vector(7 downto 0);
begin
if rising_edge(clk_62m5_sys) then
addr := to_integer(unsigned(buildinfo_addr)) * 4;
for i in 0 to 3 loop
if addr + i < buildinfo'length then
b := std_logic_vector(to_unsigned(character'pos(
buildinfo(buildinfo'left + addr + i)), 8));
else
b := x"00";
end if;
buildinfo_data (7 + i * 8 downto i * 8) <= b;
end loop;
end if;
end process;
rst_gbl_n <= rst_62m5_sys_n and (not csr_rst_gbl);
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
ddr_rst <= not rst_333m_ddr_n or csr_rst_gbl;
rst_csr_app_n <= not (csr_rst_gbl or csr_rst_app);
rst_62m5_sys_n_o <= rst_62m5_sys_n and rst_csr_app_n;
clk_62m5_sys_o <= clk_62m5_sys;
inst_rst_csr_app_sync : gc_sync_ffs
port map (
clk_i => clk_125m_ref,
rst_n_i => '1',
data_i => rst_csr_app_n,
synced_o => rst_csr_app_sync_n);
rst_125m_ref_n_o <= rst_125m_ref_n and rst_csr_app_sync_n;
clk_125m_ref_o <= clk_125m_ref;
inst_i2c: entity work.xwb_i2c_master
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_interfaces => 1)
port map (
clk_sys_i => clk_62m5_sys,
rst_n_i => rst_gbl_n,
slave_i => fmc_i2c_out,
slave_o => fmc_i2c_in,
desc_o => open,
int_o => irqs(0),
scl_pad_i (0) => fmc0_scl_b,
scl_pad_o (0) => fmc0_scl_out,
scl_padoen_o (0) => fmc0_scl_oen,
sda_pad_i (0) => fmc0_sda_b,
sda_pad_o (0) => fmc0_sda_out,
sda_padoen_o (0) => fmc0_sda_oen
);
fmc0_scl_b <= fmc0_scl_out when fmc0_scl_oen = '0' else 'Z';
fmc0_sda_b <= fmc0_sda_out when fmc0_sda_oen = '0' else 'Z';
gen_user_irq: if g_NUM_USER_IRQ > 0 generate
irqs(irq_user_i'range) <= irq_user_i;
end generate gen_user_irq;
gen_vic: if g_with_vic generate
inst_vic: entity work.xwb_vic
generic map (
g_address_granularity => BYTE,
g_num_interrupts => num_interrupts,
g_FIXED_POLARITY => True,
g_POLARITY => '1'
)
port map (
clk_sys_i => clk_62m5_sys,
rst_n_i => rst_gbl_n,
slave_i => vic_out,
slave_o => vic_in,
irqs_i => irqs,
irq_master_o => irq_master
);
end generate;
gen_no_vic: if not g_with_vic generate
vic_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
irq_master <= '0';
end generate;
irqs(3) <= '0';
irqs(4) <= '0';
irqs(5) <= '0';
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master #2 (Etherbone))
-----------------------------------------------------------------------------
gen_wr: if g_WITH_WR generate
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
begin
-- Remap WR registers.
wrc_out_sh <= (cyc => wrc_out.cyc, stb => wrc_out.stb,
adr => wrc_out.adr or x"00020000",
sel => wrc_out.sel, we => wrc_out.we, dat => wrc_out.dat);
cmp_xwrc_board_spec : xwrc_board_spec
generic map (
g_simulation => boolean'pos(g_SIMULATION),
g_VERBOSE => g_VERBOSE,
g_with_external_clock_input => TRUE,
g_dpram_initf => g_DPRAM_INITF,
g_AUX_CLKS => g_AUX_CLKS,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG,
g_STREAMERS_OP_MODE => g_STREAMERS_OP_MODE,
g_TX_STREAMER_PARAMS => g_TX_STREAMER_PARAMS,
g_RX_STREAMER_PARAMS => g_RX_STREAMER_PARAMS,
g_FABRIC_IFACE => g_FABRIC_IFACE)
port map (
areset_n_i => button1_n_i,
areset_edge_n_i => gn_rst_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_aux_i => clk_aux_i,
clk_10m_ext_i => clk_10m_ext,
clk_sys_62m5_o => clk_62m5_sys,
clk_ref_125m_o => clk_125m_ref,
clk_pll_aux_o => clk_pll_aux,
rst_sys_62m5_n_o => rst_62m5_sys_n,
rst_ref_125m_n_o => rst_125m_ref_n,
rst_pll_aux_n_o => rst_pll_aux_n,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_in,
eeprom_sda_o => eeprom_sda_out,
eeprom_scl_i => eeprom_scl_in,
eeprom_scl_o => eeprom_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
-- Uart
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- SPI Flash
flash_sclk_o => spi_sclk_o,
flash_ncs_o => spi_ncs_o,
flash_mosi_o => spi_mosi_o,
flash_miso_i => spi_miso_i,
wb_slave_o => wrc_in,
wb_slave_i => wrc_out_sh,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
wrf_snk_i => wrf_snk_i,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_i,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_i,
wb_eth_master_o => wb_eth_master_o,
wb_eth_master_i => wb_eth_master_i,
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => wrc_abscal_rxts_out,
tm_link_up_o => tm_link_up_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o,
led_link_o => led_link_o,
led_act_o => led_act_o);
clk_333m_ddr <= clk_pll_aux(0);
rst_333m_ddr_n <= rst_pll_aux_n(0);
clk_10m_ext <= '0';
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- tri-state onewire access
onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= onewire_b;
-- WR means neither onewire nor spi.
assert not g_WITH_ONEWIRE report "WR is not yet compatible with ONEWIRE"
severity failure;
assert not g_WITH_SPI report "WR is not yet compatible with SPI"
severity failure;
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0',
dat => (others => '0'));
flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0',
dat => (others => '0'));
irqs(1) <= '0';
end generate;
gen_no_wr: if not g_WITH_WR generate
signal clk_125m_pllref : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_62m5 : std_logic;
signal pllout_clk_125m : std_logic;
signal pllout_clk_333m : std_logic;
signal pllout_locked : std_logic;
signal rstlogic_arst : std_logic;
begin
-- Input clock
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3, -- 333 MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_62m5,
CLKOUT1 => pllout_clk_125m,
CLKOUT2 => pllout_clk_333m,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => pllout_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_clk_62m5_buf : BUFG
port map (
O => clk_62m5_sys,
I => pllout_clk_62m5);
cmp_clk_125m_buf : BUFG
port map (
O => clk_125m_ref,
I => pllout_clk_125m);
cmp_clk_333m_buf : BUFG
port map (
O => clk_333m_ddr,
I => pllout_clk_333m);
-- logic AND of all async reset sources (active high)
rstlogic_arst <= (not pllout_locked) and (not gn_rst_n_i);
-- Clocks required to have synced resets
cmp_rstlogic_reset : gc_reset_multi_aasd
generic map (
g_CLOCKS => 3,
g_RST_LEN => 16) -- 16 clock cycles
port map (
arst_i => rstlogic_arst,
clks_i (0) => clk_62m5_sys,
clks_i (1) => clk_125m_ref,
clks_i (2) => clk_333m_ddr,
rst_n_o (0) => rst_62m5_sys_n,
rst_n_o (1) => rst_125m_ref_n,
rst_n_o (2) => rst_333m_ddr_n);
-- Not used.
wrc_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
end generate;
gen_onewire: if g_WITH_ONEWIRE and not g_WITH_WR generate
inst_onewire: entity work.xwb_ds182x_readout
generic map (
g_CLOCK_FREQ_KHZ => 62_500,
g_USE_INTERNAL_PPS => True)
port map (
clk_i => clk_62m5_sys,
rst_n_i => rst_gbl_n,
wb_i => therm_id_out,
wb_o => therm_id_in,
pps_p_i => '0',
onewire_b => onewire_b
);
end generate;
gen_no_onewire: if not g_WITH_ONEWIRE and not g_WITH_WR generate
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
onewire_b <= 'Z';
end generate;
gen_spi: if g_WITH_SPI and not g_WITH_WR generate
inst_spi: entity work.xwb_spi
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_divider_len => open,
g_max_char_len => open,
g_num_slaves => 1
)
port map (
clk_sys_i => clk_62m5_sys,
rst_n_i => rst_gbl_n,
slave_i => flash_spi_out,
slave_o => flash_spi_in,
desc_o => open,
int_o => irqs(1),
pad_cs_o(0) => spi_ncs_o,
pad_sclk_o => spi_sclk_o,
pad_mosi_o => spi_mosi_o,
pad_miso_i => spi_miso_i
);
end generate;
gen_no_spi: if not g_WITH_SPI and not g_WITH_WR generate
flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
end generate;
-- DDR3 controller
gen_with_ddr: if g_WITH_DDR generate
cmp_ddr_ctrl_bank3 : entity work.ddr3_ctrl
generic map(
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => "SPEC_BANK3_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => boolean'image(g_SIMULATION),
g_CALIB_SOFT_IP => "TRUE",
g_P0_MASK_SIZE => g_DDR_DATA_SIZE / 8,
g_P0_DATA_PORT_SIZE => g_DDR_DATA_SIZE,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => clk_333m_ddr,
rst_n_i => ddr_rst,
status_o => ddr_status,
ddr3_dq_b => ddr_dq_b,
ddr3_a_o => ddr_a_o,
ddr3_ba_o => ddr_ba_o,
ddr3_ras_n_o => ddr_ras_n_o,
ddr3_cas_n_o => ddr_cas_n_o,
ddr3_we_n_o => ddr_we_n_o,
ddr3_odt_o => ddr_odt_o,
ddr3_rst_n_o => ddr_reset_n_o,
ddr3_cke_o => ddr_cke_o,
ddr3_dm_o => ddr_ldm_o,
ddr3_udm_o => ddr_udm_o,
ddr3_dqs_p_b => ddr_ldqs_p_b,
ddr3_dqs_n_b => ddr_ldqs_n_b,
ddr3_udqs_p_b => ddr_udqs_p_b,
ddr3_udqs_n_b => ddr_udqs_n_b,
ddr3_clk_p_o => ddr_ck_p_o,
ddr3_clk_n_o => ddr_ck_n_o,
ddr3_rzq_b => ddr_rzq_b,
wb0_rst_n_i => ddr_dma_rst_n_i,
wb0_clk_i => ddr_dma_clk_i,
wb0_sel_i => ddr_dma_wb_sel_i,
wb0_cyc_i => ddr_dma_wb_cyc_i,
wb0_stb_i => ddr_dma_wb_stb_i,
wb0_we_i => ddr_dma_wb_we_i,
wb0_addr_i => ddr_dma_wb_adr_i,
wb0_data_i => ddr_dma_wb_dat_i,
wb0_data_o => ddr_dma_wb_dat_o,
wb0_ack_o => ddr_dma_wb_ack_o,
wb0_stall_o => ddr_dma_wb_stall_o,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty_o,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_gbl_n,
wb1_clk_i => clk_62m5_sys,
wb1_sel_i => gn_wb_ddr_out.sel,
wb1_cyc_i => gn_wb_ddr_out.cyc,
wb1_stb_i => gn_wb_ddr_out.stb,
wb1_we_i => gn_wb_ddr_out.we,
wb1_addr_i => gn_wb_ddr_out.adr,
wb1_data_i => gn_wb_ddr_out.dat,
wb1_data_o => gn_wb_ddr_in.dat,
wb1_ack_o => gn_wb_ddr_in.ack,
wb1_stall_o => gn_wb_ddr_in.stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
ddr_calib_done <= ddr_status(0);
-- unused Wishbone signals
gn_wb_ddr_in.err <= '0';
gn_wb_ddr_in.rty <= '0';
end generate gen_with_ddr;
gen_without_ddr : if not g_WITH_DDR generate
ddr_calib_done <= '0';
gn_wb_ddr_in <= c_DUMMY_WB_MASTER_IN;
ddr_a_o <= (others => '0');
ddr_ba_o <= (others => '0');
ddr_dq_b <= (others => 'Z');
ddr_cas_n_o <= '0';
ddr_ck_p_o <= '0';
ddr_ck_n_o <= '0';
ddr_cke_o <= '0';
ddr_ldm_o <= '0';
ddr_ldqs_n_b <= 'Z';
ddr_ldqs_p_b <= 'Z';
ddr_udqs_n_b <= 'Z';
ddr_udqs_p_b <= 'Z';
ddr_odt_o <= '0';
ddr_udm_o <= '0';
ddr_ras_n_o <= '0';
ddr_reset_n_o <= '0';
ddr_we_n_o <= '0';
ddr_rzq_b <= 'Z';
ddr_dma_wb_dat_o <= (others => '0');
ddr_dma_wb_ack_o <= '1';
ddr_dma_wb_stall_o <= '0';
ddr_wr_fifo_empty_o <= '0';
end generate gen_without_ddr;
end architecture top;
hdl/syn/common/Manifest.py 0 → 100644
View file @ 204ff681
files = ["spec_base_common.ucf"]
ucf_dict = {'wr': "spec_base_wr.ucf",
'onewire': "spec_base_onewire.ucf",
'spi': "spec_base_spi.ucf",
'ddr3': "spec_base_ddr3.ucf"}
for p in spec_base_ucf:
f = ucf_dict.get(p, None)
assert f is not None, "unknown name {} in 'spec_base_ucf'".format(p)
files.append(f)
hdl/syn/common/spec_base_common.ucf 0 → 100644
View file @ 204ff681
#===============================================================================
# IO Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# GN4124 PCIe bridge signals
#----------------------------------------
NET "gn_rst_n_i" LOC = N20;
NET "gn_p2l_clk_n_i" LOC = M19;
NET "gn_p2l_clk_p_i" LOC = M20;
NET "gn_p2l_rdy_o" LOC = J16;
NET "gn_p2l_dframe_i" LOC = J22;
NET "gn_p2l_valid_i" LOC = L19;
NET "gn_p2l_data_i[0]" LOC = K20;
NET "gn_p2l_data_i[1]" LOC = H22;
NET "gn_p2l_data_i[2]" LOC = H21;
NET "gn_p2l_data_i[3]" LOC = L17;
NET "gn_p2l_data_i[4]" LOC = K17;
NET "gn_p2l_data_i[5]" LOC = G22;
NET "gn_p2l_data_i[6]" LOC = G20;
NET "gn_p2l_data_i[7]" LOC = K18;
NET "gn_p2l_data_i[8]" LOC = K19;
NET "gn_p2l_data_i[9]" LOC = H20;
NET "gn_p2l_data_i[10]" LOC = J19;
NET "gn_p2l_data_i[11]" LOC = E22;
NET "gn_p2l_data_i[12]" LOC = E20;
NET "gn_p2l_data_i[13]" LOC = F22;
NET "gn_p2l_data_i[14]" LOC = F21;
NET "gn_p2l_data_i[15]" LOC = H19;
NET "gn_p_wr_req_i[0]" LOC = M22;
NET "gn_p_wr_req_i[1]" LOC = M21;
NET "gn_p_wr_rdy_o[0]" LOC = L15;
NET "gn_p_wr_rdy_o[1]" LOC = K16;
NET "gn_rx_error_o" LOC = J17;
NET "gn_l2p_clk_n_o" LOC = K22;
NET "gn_l2p_clk_p_o" LOC = K21;
NET "gn_l2p_dframe_o" LOC = U22;
NET "gn_l2p_valid_o" LOC = T18;
NET "gn_l2p_edb_o" LOC = U20;
NET "gn_l2p_data_o[0]" LOC = P16;
NET "gn_l2p_data_o[1]" LOC = P21;
NET "gn_l2p_data_o[2]" LOC = P18;
NET "gn_l2p_data_o[3]" LOC = T20;
NET "gn_l2p_data_o[4]" LOC = V21;
NET "gn_l2p_data_o[5]" LOC = V19;
NET "gn_l2p_data_o[6]" LOC = W22;
NET "gn_l2p_data_o[7]" LOC = Y22;
NET "gn_l2p_data_o[8]" LOC = P22;
NET "gn_l2p_data_o[9]" LOC = R22;
NET "gn_l2p_data_o[10]" LOC = T21;
NET "gn_l2p_data_o[11]" LOC = T19;
NET "gn_l2p_data_o[12]" LOC = V22;
NET "gn_l2p_data_o[13]" LOC = V20;
NET "gn_l2p_data_o[14]" LOC = W20;
NET "gn_l2p_data_o[15]" LOC = Y21;
NET "gn_l2p_rdy_i" LOC = U19;
NET "gn_l_wr_rdy_i[0]" LOC = R20;
NET "gn_l_wr_rdy_i[1]" LOC = T22;
NET "gn_p_rd_d_rdy_i[0]" LOC = N16;
NET "gn_p_rd_d_rdy_i[1]" LOC = P19;
NET "gn_tx_error_i" LOC = M17;
NET "gn_vc_rdy_i[0]" LOC = B21;
NET "gn_vc_rdy_i[1]" LOC = B22;
NET "gn_gpio_b[0]" LOC = U16; # GPIO8
NET "gn_gpio_b[1]" LOC = AB19; # GPIO9
NET "gn_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_clk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clk_n_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_clk_p_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error_i" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_gpio_b[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Misc
#----------------------------------------
NET "button1_n_i" LOC = C22;
NET "button1_n_i" IOSTANDARD = "LVCMOS18";
NET "pcbrev_i[0]" LOC = P5;
NET "pcbrev_i[1]" LOC = P4;
NET "pcbrev_i[2]" LOC = AA2;
NET "pcbrev_i[3]" LOC = AA1;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_scl_b" LOC = F7;
NET "fmc0_sda_b" LOC = F8;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i*" TIG;
NET "fmc0_prsnt_m2c_n_i" TIG;
#===============================================================================
# Timing Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "gn_p2l_clk_p_i" TNM_NET = "gn_p2l_clk";
NET "gn_p2l_clk_n_i" TNM_NET = "gn_p2l_clk";
TIMESPEC TS_gn_p2l_clk = PERIOD "gn_p2l_clk" 5 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref";
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref";
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_pllref" 8 ns HIGH 50%;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
NET "gn_rst_n_i" TIG;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "inst_spec_base/clk_62m5_sys" TNM_NET = sys_clk;
NET "inst_spec_base/clk_125m_ref" TNM_NET = ref_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_clk;
TIMEGRP "sys_grp" = "sys_clk" "ref_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_grp";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMESPEC TS_sys_sync_ffs = FROM sys_grp TO "sys_sync_ffs" TIG;
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_grp";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
hdl/syn/common/spec_base_ddr3.ucf 0 → 100644
View file @ 204ff681
## DDR-3
NET "ddr_rzq_b" LOC = K7;
NET "ddr_we_n_o" LOC = H2;
NET "ddr_udqs_p_b" LOC = V2;
NET "ddr_udqs_n_b" LOC = V1;
NET "ddr_udm_o" LOC = P3;
NET "ddr_reset_n_o" LOC = E3;
NET "ddr_ras_n_o" LOC = M5;
NET "ddr_odt_o" LOC = L6;
NET "ddr_ldqs_p_b" LOC = N3;
NET "ddr_ldqs_n_b" LOC = N1;
NET "ddr_ldm_o" LOC = N4;
NET "ddr_cke_o" LOC = F2;
NET "ddr_ck_p_o" LOC = K4;
NET "ddr_ck_n_o" LOC = K3;
NET "ddr_cas_n_o" LOC = M4;
NET "ddr_dq_b[15]" LOC = Y1;
NET "ddr_dq_b[14]" LOC = Y2;
NET "ddr_dq_b[13]" LOC = W1;
NET "ddr_dq_b[12]" LOC = W3;
NET "ddr_dq_b[11]" LOC = U1;
NET "ddr_dq_b[10]" LOC = U3;
NET "ddr_dq_b[9]" LOC = T1;
NET "ddr_dq_b[8]" LOC = T2;
NET "ddr_dq_b[7]" LOC = M1;
NET "ddr_dq_b[6]" LOC = M2;
NET "ddr_dq_b[5]" LOC = L1;
NET "ddr_dq_b[4]" LOC = L3;
NET "ddr_dq_b[3]" LOC = P1;
NET "ddr_dq_b[2]" LOC = P2;
NET "ddr_dq_b[1]" LOC = R1;
NET "ddr_dq_b[0]" LOC = R3;
NET "ddr_ba_o[2]" LOC = H1;
NET "ddr_ba_o[1]" LOC = J1;
NET "ddr_ba_o[0]" LOC = J3;
NET "ddr_a_o[13]" LOC = J6;
NET "ddr_a_o[12]" LOC = F1;
NET "ddr_a_o[11]" LOC = E1;
NET "ddr_a_o[10]" LOC = J4;
NET "ddr_a_o[9]" LOC = G1;
NET "ddr_a_o[8]" LOC = G3;
NET "ddr_a_o[7]" LOC = K6;
NET "ddr_a_o[6]" LOC = L4;
NET "ddr_a_o[5]" LOC = M3;
NET "ddr_a_o[4]" LOC = H3;
NET "ddr_a_o[3]" LOC = M6;
NET "ddr_a_o[2]" LOC = K5;
NET "ddr_a_o[1]" LOC = K1;
NET "ddr_a_o[0]" LOC = K2;
# DDR IO standards and terminations
NET "ddr_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_p_b" IN_TERM = NONE;
NET "ddr_ldqs_n_b" IN_TERM = NONE;
NET "ddr_udqs_p_b" IN_TERM = NONE;
NET "ddr_udqs_n_b" IN_TERM = NONE;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "inst_spec_base/*cmp_ddr_ctrl_bank?/*/c?_pll_lock" TIG;
NET "inst_spec_base/*cmp_ddr_ctrl_bank?/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_spec_base/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_base/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
# Ignore async reset to DDR controller
NET "inst_spec_base/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "inst_spec_base/clk_333m_ddr" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
# DDR does not use any sync modules
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
#---------------------------------------
# DMA
#---------------------------------------
NET "inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma.cmp_dma_controller/dma_async_*" TNM = FFS "dma_ffs";
TIMESPEC TS_dma_async_ffs = FROM dma_ffs TO pci_clk 15ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_* (3x multicycle)
NET "*/gc_sync_word_data[*]" TNM = FFS "sync_word";
TIMESPEC TS_sys_sync_word = FROM sync_word TO sys_clk 48ns DATAPATHONLY;
TIMESPEC TS_ref_sync_word = FROM sync_word TO ref_clk 24ns DATAPATHONLY;
# no gc_sync_word used in GN4124
#TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
hdl/syn/common/spec_base_onewire.ucf 0 → 100644
View file @ 204ff681
###########################################################################
## Onewire interface -> thermometer
###########################################################################
NET "onewire_b" LOC = D4;
NET "onewire_b" IOSTANDARD = "LVCMOS25";
hdl/syn/common/spec_base_spi.ucf 0 → 100644
View file @ 204ff681
###########################################################################
## Flash memory SPI interface
###########################################################################
NET "spi_ncs_o" LOC = AA3;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS25";
NET "spi_sclk_o" LOC = Y20;
NET "spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "spi_mosi_o" LOC = AB20;
NET "spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "spi_miso_i" LOC = AA20;
NET "spi_miso_i" IOSTANDARD = "LVCMOS25";
hdl/syn/common/spec_base_wr.ucf 0 → 100644
View file @ 204ff681
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "plldac_sclk_o" LOC = A4;
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" LOC = C4;
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "pll25dac_cs_n_o" LOC = A3;
NET "pll25dac_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_cs_n_o" LOC = B3;
NET "pll20dac_cs_n_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_txp_o" LOC= B16;
NET "sfp_txn_o" LOC= A16;
NET "sfp_rxp_i" LOC= D15;
NET "sfp_rxn_i" LOC= C15;
NET "sfp_mod_def0_i" LOC = G15;
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" LOC = B18;
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_los_i" LOC = D18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD="LVCMOS25";
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD="LVCMOS25";
#----------------------------------------
# SFP LEDs
#----------------------------------------
NET "led_act_o" LOC = D5;
NET "led_act_o" IOSTANDARD = "LVCMOS25";
NET "led_link_o" LOC = E5;
NET "led_link_o" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
NET "clk_125m_gtp_p_i" TNM_NET = "clk_125m_gtp";
NET "clk_125m_gtp_n_i" TNM_NET = "clk_125m_gtp";
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "inst_spec_base/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int[1]" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
#-------------------------------------------------------------
# Constrain the phase between input and sampling clock in DMTD
#-------------------------------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1.25 ns DATAPATHONLY;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "*cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "*cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
# no gc_sync_reg for DMTD
#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
# no gc_sync_word for DMTD or PHY
#TIMESPEC TS_dmtd_sync_word = FROM sync_word TO clk_dmtd 48ns DATAPATHONLY;
#TIMESPEC TS_phy_sync_word = FROM sync_word TO phy_clk 24ns DATAPATHONLY;
hdl/syn/full/.gitignore 0 → 100644
View file @ 204ff681
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/full/Manifest.py 0 → 100644
View file @ 204ff681
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_full.xise"
syn_tool = "ise"
syn_top = "spec_full"
spec_base_ucf = ['wr', 'onewire', 'spi', 'ddr3']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/full", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/full/syn_extra_steps.tcl 0 → 100644
View file @ 204ff681
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/syn/golden/Manifest.py 0 → 100644
View file @ 204ff681
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden.xise"
syn_tool = "ise"
syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/golden/syn_extra_steps.tcl 0 → 100644
View file @ 204ff681
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/syn/golden_wr-150T/.gitignore 0 → 100644
View file @ 204ff681
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/golden_wr-150T/Manifest.py 0 → 100644
View file @ 204ff681
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/golden_wr-150T/syn_extra_steps.tcl 0 → 100644
View file @ 204ff681
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/syn/golden_wr/.gitignore 0 → 100644
View file @ 204ff681
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/golden_wr/Manifest.py 0 → 100644
View file @ 204ff681
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/golden_wr/syn_extra_steps.tcl 0 → 100644
View file @ 204ff681
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/test_ddr/rtl/Manifest.py deleted 100644 → 0
View file @ a465c3cc
files = ["spec_ddr_test.vhd",
"gpio_regs.vhd"]
modules = {"svn" : ["http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl",
"http://svn.ohwr.org/gn4124-core/trunk/hdl/common/rtl",
"http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl"],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git"}
fetchto = "../ip_cores"
hdl/test_ddr/rtl/gpio_regs.vhd deleted 100644 → 0
View file @ a465c3cc
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/gpio_regs.vhd
-- Author : auto-generated by wbgen2 from gpio_regs.wb
-- Created : Thu Feb 3 17:14:27 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE gpio_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gpio_regs is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'Status register' in reg: 'Status'
gpio_stat_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Control register 1' in reg: 'Control_1'
gpio_ctrl_1_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Control register 2' in reg: 'Control_2'
gpio_ctrl_2_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Control register 3' in reg: 'Control_3'
gpio_ctrl_3_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Register for front panel LED control' in reg: 'LED_control'
gpio_led_ctrl_o : out std_logic_vector(31 downto 0)
);
end gpio_regs;
architecture syn of gpio_regs is
signal gpio_ctrl_1_int : std_logic_vector(31 downto 0);
signal gpio_ctrl_2_int : std_logic_vector(31 downto 0);
signal gpio_ctrl_3_int : std_logic_vector(31 downto 0);
signal gpio_led_ctrl_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
gpio_ctrl_1_int <= "00000000000000000000000000000000";
gpio_ctrl_2_int <= "00000000000000000000000000000000";
gpio_ctrl_3_int <= "00000000000000000000000000000000";
gpio_led_ctrl_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= gpio_stat_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
gpio_ctrl_1_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= gpio_ctrl_1_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
gpio_ctrl_2_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= gpio_ctrl_2_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
gpio_ctrl_3_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= gpio_ctrl_3_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
gpio_led_ctrl_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= gpio_led_ctrl_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- Status register
-- Control register 1
gpio_ctrl_1_o <= gpio_ctrl_1_int;
-- Control register 2
gpio_ctrl_2_o <= gpio_ctrl_2_int;
-- Control register 3
gpio_ctrl_3_o <= gpio_ctrl_3_int;
-- Register for front panel LED control
gpio_led_ctrl_o <= gpio_led_ctrl_int;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/test_ddr/rtl/spec_ddr_test.vhd deleted 100644 → 0
View file @ a465c3cc
--------------------------------------------------------------------------------
--
-- CERN BE-CO-HT Top level entity for Simple PCIe FMC Carrier
-- http://www.ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_ddr_test_top (spec_ddr_test_top.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 03-02-2011
--
-- version: 0.1
--
-- description: Top entity for SPEC board.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_ddr_test is
generic(
g_SIMULATION : string := "FALSE";
g_CALIB_SOFT_IP : string := "TRUE");
port
(
-- Global ports
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
--clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
--clk_125m_pllref_n_i : in std_logic;
-- From GN4124 Local bus
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-- Font panel LEDs
LED_RED_O : out std_logic;
LED_GREEN_O : out std_logic;
-- Auxiliary pins
AUX_LEDS_O : out std_logic_vector(3 downto 0);
AUX_BUTTONS_I : in std_logic_vector(1 downto 0);
-- DDR3 interface
DDR3_CAS_N : out std_logic;
DDR3_CK_N : out std_logic;
DDR3_CK_P : out std_logic;
DDR3_CKE : out std_logic;
DDR3_LDM : out std_logic;
DDR3_LDQS_N : inout std_logic;
DDR3_LDQS_P : inout std_logic;
DDR3_ODT : out std_logic;
DDR3_RAS_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_UDM : out std_logic;
DDR3_UDQS_N : inout std_logic;
DDR3_UDQS_P : inout std_logic;
DDR3_WE_N : out std_logic;
DDR3_DQ : inout std_logic_vector(15 downto 0);
DDR3_A : out std_logic_vector(13 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_ZIO : inout std_logic;
DDR3_RZQ : inout std_logic
);
end spec_ddr_test;
architecture rtl of spec_ddr_test is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component gn4124_core
port
(
---------------------------------------------------------
-- Control and status
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
dma_reg_sel_i : in std_logic_vector(3 downto 0);
dma_reg_stb_i : in std_logic;
dma_reg_we_i : in std_logic;
dma_reg_cyc_i : in std_logic;
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i : in std_logic;
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_sel_o : out std_logic_vector(3 downto 0);
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0);
dma_ack_i : in std_logic;
dma_stall_i : in std_logic
);
end component; -- gn4124_core
component wb_addr_decoder
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end component wb_addr_decoder;
component ddr3_ctrl
generic(
g_BANK_PORT_SELECT : string := "BANK3_32B_32B";
g_MEMCLK_PERIOD : integer := 3200; -- in ps
g_SIMULATION : string := "FALSE";
g_CALIB_SOFT_IP : string := "TRUE";
g_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- BANK_ROW_COLUMN or ROW_BANK_COLUMN
g_NUM_DQ_PINS : integer := 16;
g_MEM_ADDR_WIDTH : integer := 14;
g_MEM_BANKADDR_WIDTH : integer := 3;
g_P0_MASK_SIZE : integer := 4;
g_P0_DATA_PORT_SIZE : integer := 32;
g_P0_BYTE_ADDR_WIDTH : integer := 30;
g_P1_MASK_SIZE : integer := 4;
g_P1_DATA_PORT_SIZE : integer := 32;
g_P1_BYTE_ADDR_WIDTH : integer := 30
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
status_o : out std_logic_vector(31 downto 0);
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_odt_o : out std_logic;
ddr3_rst_n_o : out std_logic;
ddr3_cke_o : out std_logic;
ddr3_dm_o : out std_logic;
ddr3_udm_o : out std_logic;
ddr3_dqs_p_b : inout std_logic;
ddr3_dqs_n_b : inout std_logic;
ddr3_udqs_p_b : inout std_logic;
ddr3_udqs_n_b : inout std_logic;
ddr3_clk_p_o : out std_logic;
ddr3_clk_n_o : out std_logic;
ddr3_rzq_b : inout std_logic;
ddr3_zio_b : inout std_logic;
wb0_clk_i : in std_logic;
wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
wb0_cyc_i : in std_logic;
wb0_stb_i : in std_logic;
wb0_we_i : in std_logic;
wb0_addr_i : in std_logic_vector(31 downto 0);
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_ack_o : out std_logic;
wb0_stall_o : out std_logic;
wb1_clk_i : in std_logic;
wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
wb1_cyc_i : in std_logic;
wb1_stb_i : in std_logic;
wb1_we_i : in std_logic;
wb1_addr_i : in std_logic_vector(31 downto 0);
wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
wb1_ack_o : out std_logic;
wb1_stall_o : out std_logic
);
end component ddr3_ctrl;
component gpio_regs
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
gpio_stat_i : in std_logic_vector(31 downto 0);
gpio_ctrl_1_o : out std_logic_vector(31 downto 0);
gpio_ctrl_2_o : out std_logic_vector(31 downto 0);
gpio_ctrl_3_o : out std_logic_vector(31 downto 0);
gpio_led_ctrl_o : out std_logic_vector(31 downto 0)
);
end component gpio_regs;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address
constant c_CSR_WB_SLAVES_NB : integer := 2;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- System clock
signal sys_clk_in : std_logic;
signal sys_clk_50_buf : std_logic;
signal sys_clk_200_buf : std_logic;
signal sys_clk_50 : std_logic;
signal sys_clk_200 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- P2L clock PLL status
signal p2l_pll_locked : std_logic;
-- Reset
signal rst : std_logic;
-- CSR wishbone bus (master)
signal wbm_adr : std_logic_vector(31 downto 0);
signal wbm_dat_i : std_logic_vector(31 downto 0);
signal wbm_dat_o : std_logic_vector(31 downto 0);
signal wbm_sel : std_logic_vector(3 downto 0);
signal wbm_cyc : std_logic;
signal wbm_stb : std_logic;
signal wbm_we : std_logic;
signal wbm_ack : std_logic;
signal wbm_stall : std_logic;
-- CSR wishbone bus (slaves)
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
-- DMA wishbone bus
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector(31 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic;
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic;
signal dma_stall : std_logic;
-- Interrupts stuff
signal irq_sources : std_logic_vector(1 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_sources_2_led : std_logic_vector(1 downto 0);
-- CSR whisbone slaves for test
signal gpio_stat : std_logic_vector(31 downto 0);
signal gpio_ctrl_1 : std_logic_vector(31 downto 0);
signal gpio_ctrl_2 : std_logic_vector(31 downto 0);
signal gpio_ctrl_3 : std_logic_vector(31 downto 0);
signal gpio_led_ctrl : std_logic_vector(31 downto 0);
-- DDR3
signal ddr3_status : std_logic_vector(31 downto 0);
signal ddr3_calib_done : std_logic;
-- Gennum core
signal gn4124_status : std_logic_vector(31 downto 0);
-- LED
signal led_cnt1 : unsigned(22 downto 0);
signal led_cnt2 : unsigned(24 downto 0);
signal led_en : std_logic;
begin
------------------------------------------------------------------------------
-- Clocks distribution from 20MHz TCXO
-- 50.000 MHz system clock
-- 200.000 MHz fast system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
cmp_sys_clk_buf : IBUFG
port map (
I => clk_20m_vcxo_i,
O => sys_clk_in);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 20,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 5,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 40.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => sys_clk_fb,
CLKOUT0 => sys_clk_50_buf,
CLKOUT1 => sys_clk_200_buf,
CLKOUT2 => ddr_clk_buf,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_clk_pll_locked,
RST => '0',
CLKFBIN => sys_clk_fb,
CLKIN => sys_clk_in);
cmp_clk_50_buf : BUFG
port map (
O => sys_clk_50,
I => sys_clk_50_buf);
cmp_clk_200_buf : BUFG
port map (
O => sys_clk_200,
I => sys_clk_200_buf);
-- Note that the IBUFG have to be removed from the generated ddr core (memc3_infrastructure.vhd)
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
cmp_l_clk_buf : IBUFDS
generic map (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => l_clk, -- Buffer output
I => L_CLKp, -- Diff_p buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
rst <= not(L_RST_N);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => L_RST_N,
status_o => gn4124_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
l2p_edb_o => L2P_EDB,
-- L2P Control
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => irq_sources,
irq_p_i => irq_to_gn4124,
irq_p_o => GPIO(0),
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => sys_clk_50,
dma_reg_adr_i => wb_adr,
dma_reg_dat_i => wb_dat_o,
dma_reg_sel_i => wb_sel,
dma_reg_stb_i => wb_stb,
dma_reg_we_i => wb_we,
dma_reg_cyc_i => wb_cyc(0),
dma_reg_dat_o => wb_dat_i(31 downto 0),
dma_reg_ack_o => wb_ack(0),
dma_reg_stall_o => wb_stall(0),
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk_50,
csr_adr_o => wbm_adr,
csr_dat_o => wbm_dat_o,
csr_sel_o => wbm_sel,
csr_stb_o => wbm_stb,
csr_we_o => wbm_we,
csr_cyc_o => wbm_cyc,
csr_dat_i => wbm_dat_i,
csr_ack_i => wbm_ack,
csr_stall_i => wbm_stall,
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_clk_i => sys_clk_50,
dma_adr_o => dma_adr,
dma_dat_o => dma_dat_o,
dma_sel_o => dma_sel,
dma_stb_o => dma_stb,
dma_we_o => dma_we,
dma_cyc_o => dma_cyc,
dma_dat_i => dma_dat_i,
dma_ack_i => dma_ack,
dma_stall_i => dma_stall
);
p2l_pll_locked <= gn4124_status(0);
------------------------------------------------------------------------------
-- CSR wishbone address decoder
------------------------------------------------------------------------------
cmp_csr_wb_addr_decoder : wb_addr_decoder
generic map (
g_WINDOW_SIZE => c_BAR0_APERTURE,
g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB
)
port map (
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => sys_clk_50,
rst_n_i => L_RST_N,
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i => wbm_adr,
wbm_dat_i => wbm_dat_o,
wbm_sel_i => wbm_sel,
wbm_stb_i => wbm_stb,
wbm_we_i => wbm_we,
wbm_cyc_i => wbm_cyc,
wbm_dat_o => wbm_dat_i,
wbm_ack_o => wbm_ack,
wbm_stall_o => wbm_stall,
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
wb_stall_i => wb_stall
);
------------------------------------------------------------------------------
-- CSR wishbone bus slaves
-- 0 -> DMA control and status registers (inside gn4124 core)
-- 1 -> gpio registers
------------------------------------------------------------------------------
cmp_gpio_regs : gpio_regs
port map(
rst_n_i => L_RST_N,
wb_clk_i => sys_clk_50,
wb_addr_i => wb_adr(2 downto 0),
wb_data_i => wb_dat_o,
wb_data_o => wb_dat_i(63 downto 32),
wb_cyc_i => wb_cyc(1),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(1),
gpio_stat_i => gpio_stat,
gpio_ctrl_1_o => gpio_ctrl_1,
gpio_ctrl_2_o => gpio_ctrl_2,
gpio_ctrl_3_o => gpio_ctrl_3,
gpio_led_ctrl_o => gpio_led_ctrl);
wb_stall(1) <= '0';
gpio_stat <= X"DEAD000"
& '0'
& ddr3_calib_done
& sys_clk_pll_locked
& p2l_pll_locked;
p_led_mono_1 : process (L_RST_N, sys_clk_50)
begin
if L_RST_N = '0' then
led_cnt1 <= (others => '0');
elsif rising_edge(sys_clk_50) then
if irq_sources(0) = '1' then
led_cnt1 <= (others => '1');
irq_sources_2_led(0) <= '1';
elsif led_cnt1 = 0 then
irq_sources_2_led(0) <= '0';
else
led_cnt1 <= led_cnt1 - 1;
end if;
end if;
end process p_led_mono_1;
p_led_cnt : process (L_RST_N, sys_clk_50)
begin
if L_RST_N = '0' then
led_cnt2 <= (others => '1');
led_en <= '1';
elsif rising_edge(sys_clk_50) then
led_cnt2 <= led_cnt2 - 1;
led_en <= led_cnt2(24);
end if;
end process p_led_cnt;
LED_RED_O <= gpio_led_ctrl(0) or irq_sources_2_led(0);
LED_GREEN_O <= gpio_led_ctrl(1) or led_en;
AUX_LEDS_O(0) <= not(led_en);
AUX_LEDS_O(1) <= not(sys_clk_pll_locked);
AUX_LEDS_O(2) <= not(p2l_pll_locked);
AUX_LEDS_O(3) <= not(ddr3_calib_done);
------------------------------------------------------------------------------
-- Interrupt stuff
------------------------------------------------------------------------------
-- just forward irq pulses for test
irq_to_gn4124 <= irq_sources(1) or irq_sources(0);
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
------------------------------------------------------------------------------
cmp_ddr_ctrl : ddr3_ctrl
generic map(
g_BANK_PORT_SELECT => "BANK3_32B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => g_SIMULATION,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 4,
g_P0_DATA_PORT_SIZE => 32,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => ddr_clk,
rst_n_i => L_RST_N,
status_o => ddr3_status,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
ddr3_ba_o => DDR3_BA,
ddr3_ras_n_o => DDR3_RAS_N,
ddr3_cas_n_o => DDR3_CAS_N,
ddr3_we_n_o => DDR3_WE_N,
ddr3_odt_o => DDR3_ODT,
ddr3_rst_n_o => DDR3_RESET_N,
ddr3_cke_o => DDR3_CKE,
ddr3_dm_o => DDR3_LDM,
ddr3_udm_o => DDR3_UDM,
ddr3_dqs_p_b => DDR3_LDQS_P,
ddr3_dqs_n_b => DDR3_LDQS_N,
ddr3_udqs_p_b => DDR3_UDQS_P,
ddr3_udqs_n_b => DDR3_UDQS_N,
ddr3_clk_p_o => DDR3_CK_P,
ddr3_clk_n_o => DDR3_CK_N,
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_clk_i => sys_clk_50, --'0',
wb0_sel_i => X"F",
wb0_cyc_i => '0', --wb_cyc(2), --'0',
wb0_stb_i => '0', --wb_stb, --'0',
wb0_we_i => '0', --wb_we, --'0',
wb0_addr_i => X"00000000",
wb0_data_i => X"00000000", --wb_dat_o, --X"00000000",
wb0_data_o => open, --wb_dat_i(95 downto 64), --open,
wb0_ack_o => open, --wb_ack(2), --open,
wb0_stall_o => open,
wb1_clk_i => sys_clk_50,
wb1_sel_i => dma_sel,
wb1_cyc_i => dma_cyc,
wb1_stb_i => dma_stb,
wb1_we_i => dma_we,
wb1_addr_i => dma_adr,
wb1_data_i => dma_dat_o,
wb1_data_o => dma_dat_i,
wb1_ack_o => dma_ack,
wb1_stall_o => dma_stall);
ddr3_calib_done <= ddr3_status(0);
------------------------------------------------------------------------------
-- Assign unused outputs
------------------------------------------------------------------------------
GPIO(1) <= '0';
end rtl;
hdl/test_ddr/spec_ddr_test.ucf deleted 100644 → 0
View file @ a465c3cc
#===============================================================================
# The IO Location Constraints
#===============================================================================
#----------------------------------------
# Clock inputs
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12; # CLK25_VCXO
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
#NET "clk_125m_pllref_n_i" LOC = F10;
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_pllref_p_i" LOC = G9;
#NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
# !! SFP_TX_DISABLE and SFP_MOD_DEF1 are swapped in V1.1 schematics for control signals
#----------------------------------------
#NET "SFPRX_123_N" LOC = C15;
#NET "SFPRX_123_N" IOSTANDARD = "LVCMOS25";
#NET "SFPRX_123_P" LOC = D15;
#NET "SFPRX_123_P" IOSTANDARD = "LVCMOS25";
#NET "SFPTX_123_N" LOC = A16;
#NET "SFPTX_123_N" IOSTANDARD = "LVCMOS25";
#NET "SFPTX_123_P" LOC = B16;
#NET "SFPTX_123_P" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_FAULT" LOC = B18;
#NET "SFP_TX_FAULT" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_DISABLE" LOC = F17;
#NET "SFP_TX_DISABLE" IOSTANDARD = "LVCMOS25";
#NET "SFP_LOS" LOC = D18;
#NET "SFP_LOS" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF1" LOC = C17;
#NET "SFP_MOD_DEF1" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF0" LOC = G15;
#NET "SFP_MOD_DEF0" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF2" LOC = G16;
#NET "SFP_MOD_DEF2" IOSTANDARD = "LVCMOS25";
#NET "SFP_RATE_SELECT" LOC = H14;
#NET "SFP_RATE_SELECT" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DAC interface (for VCXO)
#----------------------------------------
#NET "PLL25DAC1_SYNC_N" LOC = A3;
#NET "PLL25DAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
#NET "PLL25DAC2_SYNC_N" LOC = B3;
#NET "PLL25DAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
#NET "PLL25DAC_DIN" LOC = C4;
#NET "PLL25DAC_DIN" IOSTANDARD = "LVCMOS25";
#NET "PLL25DAC_SCLK" LOC = A4;
#NET "PLL25DAC_SCLK" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
#NET "THERMO_ID" LOC = D4;
#NET "THERMO_ID" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# I2C interface
#----------------------------------------
#NET "FPGA_SCL" LOC = F7;
#NET "FPGA_SCL" IOSTANDARD = "LVCMOS25";
#NET "FPGA_SDA" LOC = F8;
#NET "FPGA_SDA" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L_CLKN" LOC = N19;
NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L_CLKP" LOC = P20;
NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "GPIO[0]" LOC = U16;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "GPIO[1]" LOC = AB19;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot
#----------------------------------------
#NET "ext_trigger_n_i" LOC = AB13; # LA17_N
#NET "ext_trigger_n_i" IOSTANDARD = "LVDS_25";
#NET "ext_trigger_p_i" LOC = Y13; # LA17_P
#NET "ext_trigger_p_i" IOSTANDARD = "LVDS_25";
# dco_p and dco_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
#NET "adc_dco_n_i" LOC = AB11; # LA00_N
#NET "adc_dco_n_i" IOSTANDARD = "LVDS_25";
#NET "adc_dco_p_i" LOC = Y11; # LA00_P
#NET "adc_dco_p_i" IOSTANDARD = "LVDS_25";
# fr_p and fr_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
#NET "adc_fr_n_i" LOC = AB12; # LA01_N
#NET "adc_fr_n_i" IOSTANDARD = "LVDS_25";
#NET "adc_fr_p_i" LOC = AA12; # LA01_P
#NET "adc_fr_p_i" IOSTANDARD = "LVDS_25";
#NET "adc_outa_n_i[0]" LOC = AB4; # LA14_N
#NET "adc_outa_n_i[0]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_p_i[0]" LOC = AA4; # LA14_P
#NET "adc_outa_p_i[0]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_n_i[0]" LOC = W11; # LA15_N
#NET "adc_outb_n_i[0]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_p_i[0]" LOC = V11; # LA15_P
#NET "adc_outb_p_i[0]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_n_i[1]" LOC = Y12; # LA16_N
#NET "adc_outa_n_i[1]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_p_i[1]" LOC = W12; # LA16_P
#NET "adc_outa_p_i[1]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_n_i[1]" LOC = AB9; # LA13_N
#NET "adc_outb_n_i[1]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_p_i[1]" LOC = Y9; # LA13_P
#NET "adc_outb_p_i[1]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_n_i[2]" LOC = AB8; # LA10_N
#NET "adc_outa_n_i[2]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_p_i[2]" LOC = AA8; # LA10_P
#NET "adc_outa_p_i[2]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_n_i[2]" LOC = AB7; # LA09_N
#NET "adc_outb_n_i[2]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_p_i[2]" LOC = Y7; # LA09_P
#NET "adc_outb_p_i[2]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_n_i[3]" LOC = V9; # LA07_N
#NET "adc_outa_n_i[3]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_p_i[3]" LOC = U9; # LA07_P
#NET "adc_outa_p_i[3]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_n_i[3]" LOC = AB6; # LA05_N
#NET "adc_outb_n_i[3]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_p_i[3]" LOC = AA6; # LA05_P
#NET "adc_outb_p_i[3]" IOSTANDARD = "LVDS_25";
#NET "spi_din_i" LOC = T15; # LA25_P
#NET "spi_din_i" IOSTANDARD = "LVCMOS25";
#NET "spi_dout_o" LOC = C18; # LA31_N
#NET "spi_dout_o" IOSTANDARD = "LVCMOS25";
#NET "spi_sck_o" LOC = D17; # LA31_P
#NET "spi_sck_o" IOSTANDARD = "LVCMOS25";
#NET "spi_cs_adc_n_o" LOC = V17; # LA30_P
#NET "spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
#NET "spi_cs_dac1_n_o" LOC = B20; # LA32_P
#NET "spi_cs_dac1_n_o" IOSTANDARD = "LVCMOS25";
#NET "spi_cs_dac2_n_o" LOC = A20; # LA32_N
#NET "spi_cs_dac2_n_o" IOSTANDARD = "LVCMOS25";
#NET "spi_cs_dac3_n_o" LOC = C19; # LA33_P
#NET "spi_cs_dac3_n_o" IOSTANDARD = "LVCMOS25";
#NET "spi_cs_dac4_n_o" LOC = A19; # LA33_N
#NET "spi_cs_dac4_n_o" IOSTANDARD = "LVCMOS25";
#NET "gpio_dac_clr_n_o" LOC = W18; # LA30_N
#NET "gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
#NET "gpio_led_power_o" LOC = W15; # LA28_N
#NET "gpio_led_power_o" IOSTANDARD = "LVCMOS25";
#NET "gpio_led_trigger_o" LOC = Y16; # LA28_P
#NET "gpio_led_trigger_o" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[0]" LOC = Y17; # LA26_P
#NET "gpio_ssr_ch1_o[0]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[1]" LOC = AB17; # LA26_N
#NET "gpio_ssr_ch1_o[1]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[2]" LOC = AB18; # LA27_N
#NET "gpio_ssr_ch1_o[2]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[3]" LOC = U15; # LA25_N
#NET "gpio_ssr_ch1_o[3]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[4]" LOC = W14; # LA24_P
#NET "gpio_ssr_ch1_o[4]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[5]" LOC = Y14; # LA24_N
#NET "gpio_ssr_ch1_o[5]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[6]" LOC = W17; # LA29_P
#NET "gpio_ssr_ch1_o[6]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[0]" LOC = R11; # LA20_P
#NET "gpio_ssr_ch2_o[0]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[1]" LOC = AB15; # LA19_N
#NET "gpio_ssr_ch2_o[1]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[2]" LOC = R13; # LA22_P
#NET "gpio_ssr_ch2_o[2]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[3]" LOC = T14; # LA22_N
#NET "gpio_ssr_ch2_o[3]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[4]" LOC = V13; # LA21_P
#NET "gpio_ssr_ch2_o[4]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[5]" LOC = AA18; # LA27_P
#NET "gpio_ssr_ch2_o[5]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[6]" LOC = W13; # LA21_N
#NET "gpio_ssr_ch2_o[6]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[0]" LOC = R9; # LA08_P
#NET "gpio_ssr_ch3_o[0]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[1]" LOC = R8; # LA08_N
#NET "gpio_ssr_ch3_o[1]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[2]" LOC = T10; # LA12_P
#NET "gpio_ssr_ch3_o[2]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[3]" LOC = U10; # LA12_N
#NET "gpio_ssr_ch3_o[3]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[4]" LOC = W10; # LA11_P
#NET "gpio_ssr_ch3_o[4]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[5]" LOC = Y10; # LA11_N
#NET "gpio_ssr_ch3_o[5]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[6]" LOC = T11; # LA20_N
#NET "gpio_ssr_ch3_o[6]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[0]" LOC = W6; # LA02_P
#NET "gpio_ssr_ch4_o[0]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[1]" LOC = Y6; # LA02_N
#NET "gpio_ssr_ch4_o[1]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[2]" LOC = V7; # LA03_P
#NET "gpio_ssr_ch4_o[2]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[3]" LOC = W8; # LA03_N
#NET "gpio_ssr_ch4_o[3]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[4]" LOC = T8; # LA04_P
#NET "gpio_ssr_ch4_o[4]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[5]" LOC = Y5; # LA06_P
#NET "gpio_ssr_ch4_o[5]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[6]" LOC = U8; # LA04_N
#NET "gpio_ssr_ch4_o[6]" IOSTANDARD = "LVCMOS25";
#NET "gpio_si570_oe_o" LOC = AB5; # LA06_N
#NET "gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
#NET "si570_thermo_scl_b" LOC = U12; # LA18_N
#NET "si570_thermo_scl_b" IOSTANDARD = "LVCMOS25";
#NET "si570_thermo_sda_b" LOC = T12; # LA18_P
#NET "si570_thermo_sda_b" IOSTANDARD = "LVCMOS25";
#NET "prsnt_m2c_n_i" LOC = AB14; # PRSNT_M2C_L
#NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot (unused pins)
#----------------------------------------
#NET "PG_C2M" LOC = AA14;
#NET "PG_C2M" IOSTANDARD = "LVCMOS25";
#NET "LA19_P" LOC = Y15;
#NET "LA19_P" IOSTANDARD = "LVCMOS25";
#NET "LA23_N" LOC = AB16;
#NET "LA23_N" IOSTANDARD = "LVCMOS25";
#NET "LA23_P" LOC = AA16;
#NET "LA23_P" IOSTANDARD = "LVCMOS25";
#NET "LA29_N" LOC = Y18;
#NET "LA29_N" IOSTANDARD = "LVCMOS25";
#NET "TDO_FROM_FMC" LOC = F9;
#NET "TDO_FROM_FMC" IOSTANDARD = "LVCMOS25";
#NET "TCK_TO_FMC" LOC = G8;
#NET "TCK_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TDI_TO_FMC" LOC = H11;
#NET "TDI_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TMS_TO_FMC" LOC = H10;
#NET "TMS_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TRST_TO_FMC" LOC = E6;
#NET "TRST_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_P" LOC = E16;
#NET "CLK0_M2C_P" IOSTANDARD = "LVDS_25";
#NET "CLK0_M2C_N" LOC = F16;
#NET "CLK0_M2C_N" IOSTANDARD = "LVDS_25";
#NET "CLK1_M2C_P" LOC = L20;
#NET "CLK1_M2C_P" IOSTANDARD = "LVDS_18";
#NET "CLK1_M2C_N" LOC = L22;
#NET "CLK1_M2C_N" IOSTANDARD = "LVDS_18";
#----------------------------------------
# SI57x interface
#----------------------------------------
#NET "SI57X_SCL" LOC = A18;
#NET "SI57X_SCL" IOSTANDARD = "LVCMOS25";
#NET "SI57X_SDA" LOC = A17;
#NET "SI57X_SDA" IOSTANDARD = "LVCMOS25";
#NET "SI57X_OE" LOC = H13;
#NET "SI57X_OE" IOSTANDARD = "LVCMOS25";
#NET "SI57X_CLK_N" LOC = F15;
#NET "SI57X_CLK_N" IOSTANDARD = "LVDS_25";
#NET "SI57X_CLK_P" LOC = F14;
#NET "SI57X_CLK_P" IOSTANDARD = "LVDS_25";
#----------------------------------------
# Carrier front panel LEDs
#----------------------------------------
NET "led_red_o" LOC = D5;
NET "led_red_o" IOSTANDARD = "LVCMOS25";
NET "led_green_o" LOC = E5;
NET "led_green_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
#NET "pcb_ver_i[0]" LOC = P5;
#NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
#NET "pcb_ver_i[1]" LOC = P4;
#NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
#NET "pcb_ver_i[2]" LOC = AA2;
#NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
#NET "pcb_ver_i[3]" LOC = AA1;
#NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# DDR3 interface
#----------------------------------------
NET "DDR3_CAS_N" LOC = M4;
NET "DDR3_CAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_CK_N" LOC = K3;
NET "DDR3_CK_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CK_P" LOC = K4;
NET "DDR3_CK_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CKE" LOC = F2;
NET "DDR3_CKE" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDM" LOC = N4;
NET "DDR3_LDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDQS_N" LOC = N1;
NET "DDR3_LDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_LDQS_P" LOC = N3;
NET "DDR3_LDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_ODT" LOC = L6;
NET "DDR3_ODT" IOSTANDARD = "SSTL15_II";
NET "DDR3_RAS_N" LOC = M5;
NET "DDR3_RAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RESET_N" LOC = E3;
NET "DDR3_RESET_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDM" LOC = P3;
NET "DDR3_UDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDQS_N" LOC = V1;
NET "DDR3_UDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_UDQS_P" LOC = V2;
NET "DDR3_UDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_WE_N" LOC = H2;
NET "DDR3_WE_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RZQ" LOC = K7;
NET "DDR3_RZQ" IOSTANDARD = "SSTL15_II";
NET "DDR3_ZIO" LOC = M7;
NET "DDR3_ZIO" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[0]" LOC = K2;
NET "DDR3_A[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[1]" LOC = K1;
NET "DDR3_A[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[2]" LOC = K5;
NET "DDR3_A[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[3]" LOC = M6;
NET "DDR3_A[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[4]" LOC = H3;
NET "DDR3_A[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[5]" LOC = M3;
NET "DDR3_A[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[6]" LOC = L4;
NET "DDR3_A[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[7]" LOC = K6;
NET "DDR3_A[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[8]" LOC = G3;
NET "DDR3_A[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[9]" LOC = G1;
NET "DDR3_A[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[10]" LOC = J4;
NET "DDR3_A[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[11]" LOC = E1;
NET "DDR3_A[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[12]" LOC = F1;
NET "DDR3_A[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[13]" LOC = J6;
NET "DDR3_A[13]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[14]" LOC = H5;
#NET "DDR3_A[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[0]" LOC = J3;
NET "DDR3_BA[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[1]" LOC = J1;
NET "DDR3_BA[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[2]" LOC = H1;
NET "DDR3_BA[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[0]" LOC = R3;
NET "DDR3_DQ[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[1]" LOC = R1;
NET "DDR3_DQ[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[2]" LOC = P2;
NET "DDR3_DQ[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[3]" LOC = P1;
NET "DDR3_DQ[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[4]" LOC = L3;
NET "DDR3_DQ[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[5]" LOC = L1;
NET "DDR3_DQ[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[6]" LOC = M2;
NET "DDR3_DQ[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[7]" LOC = M1;
NET "DDR3_DQ[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[8]" LOC = T2;
NET "DDR3_DQ[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[9]" LOC = T1;
NET "DDR3_DQ[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[10]" LOC = U3;
NET "DDR3_DQ[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[11]" LOC = U1;
NET "DDR3_DQ[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[12]" LOC = W3;
NET "DDR3_DQ[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[13]" LOC = W1;
NET "DDR3_DQ[13]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[14]" LOC = Y2;
NET "DDR3_DQ[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[15]" LOC = Y1;
NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";
#----------------------------------------
# UART
#----------------------------------------
#NET "UART_TXD" LOC = A2; # FPGA input
#NET "UART_TXD" IOSTANDARD = "LVCMOS25";
#NET "UART_RXD" LOC = B2; # FPGA output
#NET "UART_RXD" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Buttons and LEDs
#----------------------------------------
NET "AUX_BUTTONS_I[0]" LOC = C22;
NET "AUX_BUTTONS_I[0]" IOSTANDARD = "LVCMOS18";
NET "AUX_BUTTONS_I[1]" LOC = D21;
NET "AUX_BUTTONS_I[1]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[0]" LOC = G19;
NET "AUX_LEDS_O[0]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[1]" LOC = F20;
NET "AUX_LEDS_O[1]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[2]" LOC = F18;
NET "AUX_LEDS_O[2]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[3]" LOC = C20;
NET "AUX_LEDS_O[3]" IOSTANDARD = "LVCMOS18";
#===============================================================================
# IOBs
#===============================================================================
INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;
#===============================================================================
# Terminations
#===============================================================================
# DDR3
NET "DDR3_DQ[*]" IN_TERM = NONE;
NET "DDR3_LDQS_P" IN_TERM = NONE;
NET "DDR3_LDQS_N" IN_TERM = NONE;
NET "DDR3_UDQS_P" IN_TERM = NONE;
NET "DDR3_UDQS_N" IN_TERM = NONE;
#===============================================================================
# Clock constraints
#===============================================================================
# GN4124
NET "L_CLKp" TNM_NET = "l_clkp_grp";
TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
# System clock
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i_grp";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i_grp" 50 ns HIGH 50%;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_32b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3.0 ns HIGH 50 %;
#===============================================================================
# False Path
#===============================================================================
# GN4124
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_32b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_32b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_32b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_32b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
hdl/test_ddr/syn/Manifest.py deleted 100644 → 0
View file @ a465c3cc
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_ddr_test"
syn_project = "spec_ddr_test.xise"
files = ["../spec_ddr_test.ucf"]
modules = { "local" : "../rtl" }
hdl/test_ddr/syn/spec_ddr_test.xise deleted 100644 → 0
View file @ a465c3cc
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
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<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
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<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_ddr_test_synthesis.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="spec_ddr_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-08-11T18:51:26" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2F499380A7AA04C2CE2D7E89463358AF" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</libraries>
<files>
<file xil_pn:name="../spec_ddr_test.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../rtl/spec_ddr_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/ddr3_ctrl_bank3_32b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/ddr3_ctrl_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
</files>
<bindings>
<binding xil_pn:location="/spec_ddr_test" xil_pn:name="../spec_ddr_test.ucf"/>
</bindings>
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
</project>
hdl/test_ddr/wb_gen/gpio_regs.wb deleted 100644 → 0
View file @ a465c3cc
peripheral {
name = "Control and status registers";
description = "Wishbone slave to test CSR wishbone on SPEC board";
hdl_entity = "gpio_regs";
prefix = "gpio";
reg {
name = "Status";
prefix = "stat";
field {
name = "Status register";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control_1";
prefix = "ctrl_1";
field {
name = "Control register 1";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Control_2";
prefix = "ctrl_2";
field {
name = "Control register 2";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Control_3";
prefix = "ctrl_3";
field {
name = "Control register 3";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "LED_control";
prefix = "led_ctrl";
field {
name = "Register for front panel LED control";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
hdl/top/full/Manifest.py 0 → 100644
View file @ 204ff681
files = ["spec_full.vhd"]
modules = {'local': ["../../rtl"]}
hdl/top/full/spec_full.vhd 0 → 100644
View file @ 204ff681
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_full
--
-- description: SPEC "full" design, with access to all peripherals and features
-- of the carrier board.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_full is
generic (
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Miscellanous SPEC pins
---------------------------------------------------------------------------
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_n_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
-- DDR3
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic
);
end entity spec_full;
architecture top of spec_full is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_spec_base: entity work.spec_base_wr
generic map (
g_with_vic => True,
g_with_onewire => False,
g_with_spi => False,
g_with_ddr => True,
g_dpram_initf => g_dpram_initf,
g_simulation => g_simulation
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end architecture top;
hdl/top/golden/Manifest.py 0 → 100644
View file @ 204ff681
files = ["spec_golden.vhd"]
modules = {'local': ["../../rtl"]}
hdl/top/golden/spec_golden.vhd 0 → 100644
View file @ 204ff681
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_golden
--
-- description: SPEC golden design, without WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
entity spec_golden is
port (
-- Global ports
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
gn_RST_N_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
gn_GPIO_b : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
gn_P2L_RDY_o : out std_logic; -- Rx Buffer Full Flag
gn_P2L_CLK_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_P2L_CLK_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_P2L_DATA_i : in std_logic_vector(15 downto 0); -- Parallel receive data
gn_P2L_DFRAME_i : in std_logic; -- Receive Frame
gn_P2L_VALID_i : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
gn_P_WR_REQ_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_P_WR_RDY_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_RX_ERROR_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_L2P_DATA_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
gn_L2P_DFRAME_o : out std_logic; -- Transmit Data Frame
gn_L2P_VALID_o : out std_logic; -- Transmit Data Valid
gn_L2P_CLK_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_L2P_CLK_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_L2P_EDB_o : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
gn_L2P_RDY_i : in std_logic; -- Tx Buffer Full Flag
gn_L_WR_RDY_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_P_RD_D_RDY_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_TX_ERROR_i : in std_logic; -- Transmit Error
gn_VC_RDY_i : in std_logic_vector(1 downto 0); -- Channel ready
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Font panel LEDs
-- LED_RED : out std_logic;
-- LED_GREEN : out std_logic;
button1_n_i : in std_logic;
-- I2C to the FMC
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
onewire_b : inout std_logic;
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end spec_golden;
architecture rtl of spec_golden is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_spec_base: entity work.spec_base_wr
generic map (
g_WITH_VIC => True,
g_WITH_ONEWIRE => True,
g_WITH_SPI => True,
g_WITH_DDR => False,
g_WITH_WR => False,
g_simulation => False
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end rtl;
hdl/top/golden_wr/Manifest.py 0 → 100644
View file @ 204ff681
files = ["spec_golden_wr.vhd"]
modules = {'local': ["../../rtl"]}
hdl/top/golden_wr/spec_golden_wr.vhd 0 → 100644
View file @ 204ff681
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_golden_wr
--
-- description: SPEC golden design, with WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_golden_wr is
generic (
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Miscellanous SPEC pins
---------------------------------------------------------------------------
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_n_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic
);
end entity spec_golden_wr;
architecture top of spec_golden_wr is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_spec_base: entity work.spec_base_wr
generic map (
g_WITH_VIC => True,
g_WITH_ONEWIRE => False,
g_WITH_SPI => False,
g_WITH_DDR => False,
g_WITH_WR => True,
g_dpram_initf => g_dpram_initf,
g_simulation => g_simulation
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end architecture top;
software/Makefile 0 → 100644
View file @ 204ff681
-include Makefile.specific
# include parent_common.mk for buildsystem's defines
#use absolute path for REPO_PARENT
REPO_PARENT ?= $(shell /bin/pwd)/..
-include $(REPO_PARENT)/parent_common.mk
DIRS = kernel
.PHONY: all clean modules install modules_install $(DIRS)
all clean modules install modules_install: $(DIRS)
clean: TARGET = clean
modules: TARGET = modules
install: TARGET = install
modules_install: TARGET = modules_install
ENV_VAR := CONFIG_FPGA_MGR_BACKPORT_PATH=$(CONFIG_FPGA_MGR_BACKPORT_PATH)
ENV_VAR += CONFIG_FPGA_MGR_BACKPORT=$(CONFIG_FPGA_MGR_BACKPORT)
$(DIRS):
$(MAKE) -C $@ $(ENV_VAR) $(TARGET)
software/kernel/.gitignore 0 → 100644
View file @ 204ff681
spec-core-fpga.h
\ No newline at end of file
software/kernel/Kbuild 0 → 100644
View file @ 204ff681
# add versions of supermodule. It is useful when spec is included as sub-module
# of a bigger project that we want to track
ifdef CONFIG_SUPER_REPO
ifdef CONFIG_SUPER_REPO_VERSION
SUBMODULE_VERSIONS += MODULE_INFO(version_$(CONFIG_SUPER_REPO),\"$(CONFIG_SUPER_REPO_VERSION)\");
endif
endif
# add versions of used submodules
CONFIG_FPGA_MGR_BACKPORT_INCLUDE := -I$(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS)/include
CONFIG_FPGA_MGR_BACKPORT_INCLUDE += -I$(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS)/include/linux
ccflags-y += -DADDITIONAL_VERSIONS="$(SUBMODULE_VERSIONS)"
ccflags-y += -DVERSION=\"$(VERSION)\"
ccflags-y += -Wall -Werror
ccflags-$(CONFIG_FPGA_MGR_BACKPORT) += -DCONFIG_FPGA_MGR_BACKPORT
ccflags-$(CONFIG_FPGA_MGR_BACKPORT) += $(CONFIG_FPGA_MGR_BACKPORT_INCLUDE)
ccflags-y += -I$(FMC_ABS)/include
ccflags-y += -I$(SPI_ABS)/include
# priority to I2C, FMC headers from our sources
LINUXINCLUDE := -I$(FMC_ABS)/include -I$(FMC_ABS)/include/linux -I$(I2C_ABS)/include -I$(I2C_ABS)/include/linux $(LINUXINCLUDE)
ifeq ($(CONFIG_FPGA_MGR_BACKPORT), y)
LINUXINCLUDE := $(CONFIG_FPGA_MGR_BACKPORT_INCLUDE) $(LINUXINCLUDE)
KBUILD_EXTRA_SYMBOLS += $(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS)/drivers/fpga/Module.symvers
endif
KBUILD_EXTRA_SYMBOLS += $(FMC_ABS)/drivers/fmc/Module.symvers
obj-m := spec-fmc-carrier.o
obj-m += gn412x-gpio.o
obj-m += gn412x-fcl.o
obj-m += spec-gn412x-dma.o
spec-fmc-carrier-objs := spec-core.o
spec-fmc-carrier-objs += spec-core-fpga.o
spec-fmc-carrier-objs += spec-compat.o
software/kernel/Makefile 0 → 100644
View file @ 204ff681
-include Makefile.specific
# include parent_common.mk for buildsystem's defines
#use absolute path for REPO_PARENT
REPO_PARENT ?= $(shell /bin/pwd)/../..
-include $(REPO_PARENT)/parent_common.mk
KVERSION ?= $(shell uname -r)
LINUX ?= /lib/modules/$(KVERSION)/build
TOP_DIR ?= $(shell pwd)/../..
HDL_DIR ?= $(TOP_DIR)/hdl
DKMS ?= 0
ifndef (CONFIG_FPGA_MGR_BACKPORT)
ifeq ($(shell test $(shell uname -p) \> "4.4"), 0)
CONFIG_FPGA_MGR_BACKPORT := n
else
CONFIG_FPGA_MGR_BACKPORT := y
endif
endif
ifeq ($(DKMS), 1)
FPGA_MGR_VERSION ?= $(shell basename $(shell ls -d $(DKMSTREE)/fpga_mgr/* | grep -E "\/[0-9]+\.[0-9]+\.[0-9]+" | sort -V | tail -n 1))
FMC_VERSION ?= $(shell basename $(shell ls -d $(DKMSTREE)/fmc/* | grep -E "\/[0-9]+\.[0-9]+\.[0-9]+" | sort -V | tail -n 1))
I2C_VERSION ?= $(shell basename $(shell ls -d $(DKMSTREE)/i2c-ocores/* | grep -E "\/[0-9]+\.[0-9]+\.[0-9]+" | sort -V | tail -n 1))
SPI_VERSION ?= $(shell basename $(shell ls -d $(DKMSTREE)/spi-ocores/* | grep -E "\/[0-9]+\.[0-9]+\.[0-9]+" | sort -V | tail -n 1))
CONFIG_FPGA_MGR_BACKPORT_PATH ?= $(DKMSTREE)/fpga_mgr/$(FPGA_MGR_VERSION)/source
FMC ?= $(DKMSTREE)/fmc/$(FMC_VERSION)/source
I2C ?= $(DKMSTREE)/i2c-ocores/$(I2C_VERSION)/source
SPI ?= $(DKMSTREE)/spi-ocores/$(SPI_VERSION)/source
endif
CONFIG_FPGA_MGR_BACKPORT_PATH_ABS ?= $(abspath $(CONFIG_FPGA_MGR_BACKPORT_PATH))
FMC_ABS ?= $(abspath $(FMC))
I2C_ABS ?= $(abspath $(I2C))
SPI_ABS ?= $(abspath $(SPI))
VERSION = $(shell git describe --dirty --long --tags)
CHEBY ?= /usr/bin/cheby
all: modules
.PHONY: all modules clean help install modules_install spec-core-fpga.h
spec-core-fpga.h:
ifeq ($(DKMS), 0)
$(CHEBY) --gen-c -i $(HDL_DIR)/rtl/spec_base_regs.cheby > $@
endif
modules help install modules_install: spec-core-fpga.h
$(MAKE) -C $(LINUX) M=$(shell pwd) VERSION=$(VERSION) CONFIG_FPGA_MGR_BACKPORT_PATH_ABS=$(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS) CONFIG_FPGA_MGR_BACKPORT=$(CONFIG_FPGA_MGR_BACKPORT) FMC_ABS=$(FMC_ABS) I2C_ABS=$(I2C_ABS) SPI_ABS=$(SPI_ABS) $@
# be able to run the "clean" rule even if $(LINUX) is not valid
clean:
rm -rf *.o *~ .*.cmd *.ko *.mod.c .tmp_versions Module.symvers \
Module.markers modules.order
ifeq ($(DKMS), 0)
rm -f spec-core-fpga.h
endif
software/kernel/gn412x-fcl.c 0 → 100644
View file @ 204ff681
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#include <linux/platform_device.h>
#include <linux/fpga/fpga-mgr.h>
#include <linux/delay.h>
#include <linux/version.h>
#include "spec.h"
#include "spec-compat.h"
#include "gn412x.h"
#define FCL_CTRL_START_FSM BIT(0)
#define FCL_CTRL_SPRI_EN BIT(1)
#define FCL_CTRL_FSM_EN BIT(2)
#define FCL_CTRL_SEND_CFG_DATA BIT(3)
#define FCL_CTRL_LAST_BYTE_CNT_1 (0x3 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_2 (0x2 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_3 (0x1 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_4 (0x0 << 4)
#define FCL_CTRL_RESET BIT(6)
#define FCL_CTRL_DATA_PUSH_COMP BIT(7)
#define FCL_CTRL_SPRI_CLK_STOP_EN BIT(8)
#define FCL_SPRI_CLKOUT BIT(0)
#define FCL_SPRI_DATAOUT BIT(1)
#define FCL_SPRI_CONFIG BIT(2)
#define FCL_SPRI_DONE BIT(3)
#define FCL_SPRI_XI_SWAP BIT(4)
#define FCL_SPRI_STATUS BIT(5)
#define FCL_IRQ_SPRI_STATUS BIT(0)
#define FCL_IRQ_TIMER BIT(1)
#define FCL_IRQ_CONFIG_ERROR BIT(2)
#define FCL_IRQ_CONFIG_DONE BIT(3)
#define FCL_IRQ_FIFO_UNDRFL BIT(4)
#define FCL_IRQ_FIFO_HALFFULL BIT(5)
/* Compatibility layer */
static int gn412x_fcl_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count);
static int gn412x_fcl_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info);
static int compat_get_fpga_last_word_size(struct fpga_image_info *info,
size_t count)
{
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
return count;
#else
return info ? info->count : count;
#endif
}
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
static int compat_gn412x_fcl_write_init(struct fpga_manager *mgr,
u32 flags,
const char *buf, size_t count)
{
return gn412x_fcl_write_init(mgr, NULL, buf, count);
}
static int compat_gn412x_fcl_write_complete(struct fpga_manager *mgr,
u32 flags)
{
return gn412x_fcl_write_complete(mgr, NULL);
}
#else
static int compat_gn412x_fcl_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count)
{
return gn412x_fcl_write_init(mgr, info, buf, count);
}
static int compat_gn412x_fcl_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info)
{
return gn412x_fcl_write_complete(mgr, info);
}
#endif
#if KERNEL_VERSION(4, 18, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
static struct fpga_manager *compat_fpga_mgr_create(struct device *dev,
const char *name,
const struct fpga_manager_ops *mops,
void *priv)
{
int err;
err = fpga_mgr_register(dev, name, mops, priv);
if (err)
return NULL;
return (struct fpga_manager *)dev;
}
static void compat_fpga_mgr_free(struct fpga_manager *mgr)
{
fpga_mgr_unregister((struct device *)mgr);
}
static int compat_fpga_mgr_register(struct fpga_manager *mgr)
{
return mgr ? 0 : 1;
}
static void compat_fpga_mgr_unregister(struct fpga_manager *mgr)
{
return mgr ? 0 : 1;
}
#else
static struct fpga_manager *compat_fpga_mgr_create(struct device *dev,
const char *name,
const struct fpga_manager_ops *mops,
void *priv)
{
return fpga_mgr_create(dev, name, mops, priv);
}
static void compat_fpga_mgr_free(struct fpga_manager *mgr)
{
fpga_mgr_free(mgr);
}
static int compat_fpga_mgr_register(struct fpga_manager *mgr)
{
return fpga_mgr_register(mgr);
}
static void compat_fpga_mgr_unregister(struct fpga_manager *mgr)
{
fpga_mgr_unregister(mgr);
}
#endif
/* The real code */
/**
* struct gn412x_dev GN412X device descriptor
* @compl: for IRQ testing
* @int_cfg_gpio: INT_CFG used for GPIO interrupts
*/
struct gn412x_fcl_dev {
void __iomem *mem;
struct fpga_manager *mgr;
struct dentry *dbg_dir;
#define GN412X_DBG_REG_NAME "regs"
struct dentry *dbg_reg;
struct debugfs_regset32 dbg_reg32;
};
#define REG32(_name, _offset) {.name = _name, .offset = _offset}
static const struct debugfs_reg32 gn412x_debugfs_reg32[] = {
REG32("FCL_CTRL", FCL_CTRL),
REG32("FCL_STATUS", FCL_STATUS),
REG32("FCL_IODATA_IN", FCL_IODATA_IN),
REG32("FCL_IODATA_OUT", FCL_IODATA_OUT),
REG32("FCL_EN", FCL_EN),
REG32("FCL_TIMER0", FCL_TIMER_0),
REG32("FCL_TIMER1", FCL_TIMER_1),
REG32("FCL_CLK_DIV", FCL_CLK_DIV),
REG32("FCL_IRQ", FCL_IRQ),
REG32("FCL_TIMER_CTRL", FCL_TIMER_CTRL),
REG32("FCL_IM", FCL_IM),
REG32("FCL_TIMER2_0", FCL_TIMER2_0),
REG32("FCL_TIMER2_1", FCL_TIMER2_1),
REG32("FCL_DBG_STS", FCL_DBG_STS),
};
static int gn4124_dbg_init(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x = platform_get_drvdata(pdev);
struct dentry *dir, *file;
int err;
dir = debugfs_create_dir(dev_name(&pdev->dev), NULL);
if (IS_ERR_OR_NULL(dir)) {
err = PTR_ERR(dir);
dev_warn(&pdev->dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(&pdev->dev), err);
goto err_dir;
}
gn412x->dbg_reg32.regs = gn412x_debugfs_reg32;
gn412x->dbg_reg32.nregs = ARRAY_SIZE(gn412x_debugfs_reg32);
gn412x->dbg_reg32.base = gn412x->mem;
file = debugfs_create_regset32(GN412X_DBG_REG_NAME, 0200,
dir, &gn412x->dbg_reg32);
if (IS_ERR_OR_NULL(file)) {
err = PTR_ERR(file);
dev_warn(&pdev->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
GN412X_DBG_REG_NAME, err);
goto err_reg32;
}
gn412x->dbg_dir = dir;
gn412x->dbg_reg = file;
return 0;
err_reg32:
debugfs_remove_recursive(dir);
err_dir:
return err;
}
static void gn4124_dbg_exit(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x = platform_get_drvdata(pdev);
debugfs_remove_recursive(gn412x->dbg_dir);
}
static uint32_t gn412x_ioread32(struct gn412x_fcl_dev *gn412x,
int reg)
{
return ioread32(gn412x->mem + reg);
}
static void gn412x_iowrite32(struct gn412x_fcl_dev *gn412x,
uint32_t val, int reg)
{
return iowrite32(val, gn412x->mem + reg);
}
static inline uint8_t reverse_bits8(uint8_t x)
{
x = ((x >> 1) & 0x55) | ((x & 0x55) << 1);
x = ((x >> 2) & 0x33) | ((x & 0x33) << 2);
x = ((x >> 4) & 0x0f) | ((x & 0x0f) << 4);
return x;
}
static uint32_t unaligned_bitswap_le32(const uint32_t *ptr32)
{
static uint32_t tmp32;
static uint8_t *tmp8 = (uint8_t *) &tmp32;
static uint8_t *ptr8;
ptr8 = (uint8_t *) ptr32;
*(tmp8 + 0) = reverse_bits8(*(ptr8 + 0));
*(tmp8 + 1) = reverse_bits8(*(ptr8 + 1));
*(tmp8 + 2) = reverse_bits8(*(ptr8 + 2));
*(tmp8 + 3) = reverse_bits8(*(ptr8 + 3));
return tmp32;
}
/**
* it resets the FPGA
*/
static void gn4124_fpga_reset(struct gn412x_fcl_dev *gn412x)
{
uint32_t reg;
/* After reprogramming, reset the FPGA using the gennum register */
reg = gn412x_ioread32(gn412x, GNPCI_SYS_CFG_SYSTEM);
/*
* This _fucking_ register must be written with extreme care,
* becase some fields are "protected" and some are not. *hate*
*/
gn412x_iowrite32(gn412x, (reg & ~0xffff) | 0x3fff,
GNPCI_SYS_CFG_SYSTEM);
gn412x_iowrite32(gn412x, (reg & ~0xffff) | 0x7fff,
GNPCI_SYS_CFG_SYSTEM);
}
/**
* Initialize the gennum
* @gn412x: gn412x device instance
* @last_word_size: last word size in the FPGA bitstream
*
* Return: 0 on success, otherwise a negative error code
*/
static int gn4124_fpga_fcl_init(struct gn412x_fcl_dev *gn412x,
int last_word_size)
{
uint32_t ctrl, en;
int i;
gn412x_iowrite32(gn412x, 0x00, FCL_CLK_DIV);
gn412x_iowrite32(gn412x, FCL_CTRL_RESET, FCL_CTRL);
i = gn412x_ioread32(gn412x, FCL_CTRL);
if (i != FCL_CTRL_RESET) {
pr_err("%s: %i: error\n", __func__, __LINE__);
return -EIO;
}
gn412x_iowrite32(gn412x, 0x00, FCL_CTRL);
gn412x_iowrite32(gn412x, 0x00, FCL_IRQ); /* clear pending irq */
ctrl = 0;
ctrl |= FCL_CTRL_SPRI_EN;
ctrl |= FCL_CTRL_FSM_EN;
ctrl |= FCL_CTRL_SPRI_CLK_STOP_EN;
switch (last_word_size) {
case 3:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_3;
break;
case 2:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_2;
break;
case 1:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_1;
break;
case 0:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_4;
break;
default: return -EINVAL;
}
gn412x_iowrite32(gn412x, ctrl, FCL_CTRL);
gn412x_iowrite32(gn412x, 0x00, FCL_CLK_DIV);
gn412x_iowrite32(gn412x, 0x00, FCL_TIMER_CTRL);
gn412x_iowrite32(gn412x, 0x10, FCL_TIMER_0);
gn412x_iowrite32(gn412x, 0x00, FCL_TIMER_1);
/*
* Set delay before data and clock is applied by FCL
* after SPRI_STATUS is detected being assert.
*/
gn412x_iowrite32(gn412x, 0x08, FCL_TIMER2_0);
gn412x_iowrite32(gn412x, 0x00, FCL_TIMER2_1);
en = 0;
en |= FCL_SPRI_CLKOUT;
en |= FCL_SPRI_DATAOUT;
en |= FCL_SPRI_CONFIG;
en |= FCL_SPRI_XI_SWAP;
gn412x_iowrite32(gn412x, en, FCL_EN);
ctrl |= FCL_CTRL_START_FSM;
gn412x_iowrite32(gn412x, ctrl, FCL_CTRL);
return 0;
}
/**
* Wait for the FPGA to be configured and ready
* @gn412x: device instance
*
* Return: 0 on success,-ETIMEDOUT on failure
*/
static int gn4124_fpga_fcl_waitdone(struct gn412x_fcl_dev *gn412x)
{
unsigned long j;
j = jiffies + 2 * HZ;
while (1) {
uint32_t val = gn412x_ioread32(gn412x, FCL_IRQ);
/* Done */
if (val & 0x8)
return 0;
/* Fail */
if (val & 0x4)
return -EIO;
/* Timeout */
if (time_after(jiffies, j))
return -ETIMEDOUT;
udelay(100);
}
}
/**
* It configures the FPGA with the given image
* @gn412x: gn412x instance
* @data: FPGA configuration code
* @len: image length in bytes
*
* Return: 0 on success, otherwise a negative error code
*/
static int gn4124_fpga_load(struct gn412x_fcl_dev *gn412x,
const void *data, int len)
{
int size32 = (len + 3) >> 2;
int done = 0, wrote = 0;
const uint32_t *data32 = data;
while (size32 > 0) {
/* Check to see if FPGA configuation has error */
int i = gn412x_ioread32(gn412x, FCL_IRQ);
if ((i & FCL_IRQ_CONFIG_DONE) && wrote) {
done = 1;
pr_err("%s: %i: done after %i%i\n",
__func__, __LINE__,
wrote, ((len + 3) >> 2));
} else if ((i & FCL_IRQ_CONFIG_ERROR) && !done) {
pr_err("%s: %i: error after %i/%i\n",
__func__, __LINE__,
wrote, ((len + 3) >> 2));
return -EIO;
}
/* Wait until at least 1/2 of the fifo is empty */
while (gn412x_ioread32(gn412x, FCL_IRQ) & FCL_IRQ_FIFO_HALFFULL)
;
/* Write a few dwords into FIFO at a time. */
for (i = 0; size32 && i < 32; i++) {
gn412x_iowrite32(gn412x, unaligned_bitswap_le32(data32),
FCL_FIFO);
data32++; size32--; wrote++;
}
}
return 0;
}
/**
* It notifies the gennum that the configuration is over
* @gn412x: gn412x device instance
*/
static void gn4124_fpga_fcl_complete(struct gn412x_fcl_dev *gn412x)
{
uint32_t ctrl = 0;
ctrl |= FCL_CTRL_SPRI_EN;
ctrl |= FCL_CTRL_FSM_EN;
ctrl |= FCL_CTRL_DATA_PUSH_COMP;
ctrl |= FCL_CTRL_SPRI_CLK_STOP_EN;
gn412x_iowrite32(gn412x, ctrl, FCL_CTRL);
}
static enum fpga_mgr_states gn412x_fcl_state(struct fpga_manager *mgr)
{
return mgr->state;
}
static int gn412x_fcl_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count)
{
struct gn412x_fcl_dev *gn412x = mgr->priv;
int err = 0, last_word_size;
last_word_size = compat_get_fpga_last_word_size(info, count) & 0x3;
err = gn4124_fpga_fcl_init(gn412x, last_word_size);
if (err < 0)
goto err;
return 0;
err:
return err;
}
static int gn412x_fcl_write(struct fpga_manager *mgr,
const char *buf, size_t count)
{
struct gn412x_fcl_dev *gn412x = mgr->priv;
return gn4124_fpga_load(gn412x, buf, count);
}
static void gn4124_fcl_reset(struct gn412x_fcl_dev *gn412x)
{
gn412x_iowrite32(gn412x, 0x00, FCL_CTRL);
gn412x_iowrite32(gn412x, 0x00, FCL_EN);
}
static int gn412x_fcl_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info)
{
struct gn412x_fcl_dev *gn412x = mgr->priv;
int err;
gn4124_fpga_fcl_complete(gn412x);
err = gn4124_fpga_fcl_waitdone(gn412x);
if (err < 0)
return err;
gn4124_fcl_reset(gn412x);
gn4124_fpga_reset(gn412x);
return 0;
}
static void gn412x_fcl_fpga_remove(struct fpga_manager *mgr)
{
/* do nothing */
}
static const struct fpga_manager_ops gn412x_fcl_ops = {
compat_fpga_ops_initial_header_size
compat_fpga_ops_groups
.state = gn412x_fcl_state,
.write_init = compat_gn412x_fcl_write_init,
.write = gn412x_fcl_write,
.write_complete = compat_gn412x_fcl_write_complete,
.fpga_remove = gn412x_fcl_fpga_remove,
};
static int gn412x_fcl_probe(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x;
struct resource *r;
int err;
gn412x = devm_kzalloc(&pdev->dev, sizeof(*gn412x), GFP_KERNEL);
if (!gn412x)
return -ENOMEM;
platform_set_drvdata(pdev, gn412x);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(&pdev->dev, "Missing memory resource\n");
err = -EINVAL;
goto err_res_mem;
}
gn412x->mem = devm_ioremap(&pdev->dev, r->start, resource_size(r));
if (!gn412x->mem) {
err = -EADDRNOTAVAIL;
goto err_map;
}
gn4124_fcl_reset(gn412x);
gn4124_dbg_init(pdev);
gn412x->mgr = compat_fpga_mgr_create(&pdev->dev,
dev_name(&pdev->dev),
&gn412x_fcl_ops, gn412x);
if (!gn412x->mgr) {
err = -EPERM;
goto err_fpga_create;
}
err = compat_fpga_mgr_register(gn412x->mgr);
if (err)
goto err_fpga_reg;
return 0;
err_fpga_reg:
compat_fpga_mgr_free(gn412x->mgr);
err_fpga_create:
gn4124_dbg_exit(pdev);
devm_iounmap(&pdev->dev, gn412x->mem);
err_map:
err_res_mem:
devm_kfree(&pdev->dev, gn412x);
return err;
}
static int gn412x_fcl_remove(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x = platform_get_drvdata(pdev);
gn4124_dbg_exit(pdev);
if (!gn412x->mgr)
return -ENODEV;
compat_fpga_mgr_unregister(gn412x->mgr);
compat_fpga_mgr_free(gn412x->mgr);
dev_dbg(&pdev->dev, "%s\n", __func__);
return 0;
}
static const struct platform_device_id gn412x_fcl_id[] = {
{
.name = "gn412x-fcl",
},
{ .name = "" }, /* last */
};
static struct platform_driver gn412x_fcl_platform_driver = {
.driver = {
.name = KBUILD_MODNAME,
},
.probe = gn412x_fcl_probe,
.remove = gn412x_fcl_remove,
.id_table = gn412x_fcl_id,
};
module_platform_driver(gn412x_fcl_platform_driver);
MODULE_AUTHOR("Federico Vaga <federico.vaga@cern.ch>");
MODULE_DESCRIPTION("GN412X FCL driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(VERSION);
MODULE_DEVICE_TABLE(platform, gn412x_fcl_id);
software/kernel/gn412x-gpio.c 0 → 100644
View file @ 204ff681
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#include <linux/module.h>
#include <linux/gpio/driver.h>
#include <linux/debugfs.h>
#include "spec.h"
#include "gn412x.h"
#include "platform_data/gn412x-gpio.h"
/**
* struct gn412x_gpio_dev GN412X device descriptor
* @compl: for IRQ testing
* @int_cfg_gpio: INT_CFG used for GPIO interrupts
*/
struct gn412x_gpio_dev {
void __iomem *mem;
struct gpio_chip gpiochip;
struct completion compl;
struct gn412x_platform_data *pdata;
struct dentry *dbg_dir;
#define GN412X_DBG_REG_NAME "regs"
struct dentry *dbg_reg;
struct debugfs_regset32 dbg_reg32;
};
static struct gn412x_platform_data gn412x_gpio_pdata_default = {
.int_cfg = 0,
};
static inline struct gn412x_gpio_dev *to_gn412x_gpio_dev_gpio(struct gpio_chip *chip)
{
return container_of(chip, struct gn412x_gpio_dev, gpiochip);
}
enum gn412x_gpio_versions {
GN412X_VER = 0,
};
enum htvic_mem_resources {
GN412X_MEM_BASE = 0,
};
#define REG32(_name, _offset) {.name = _name, .offset = _offset}
static const struct debugfs_reg32 gn412x_debugfs_reg32[] = {
REG32("INT_CTRL", GNINT_CTRL),
REG32("INT_STAT", GNINT_STAT),
REG32("INT_CFG0", GNINT_CFG_0),
REG32("INT_CFG1", GNINT_CFG_1),
REG32("INT_CFG2", GNINT_CFG_2),
REG32("INT_CFG3", GNINT_CFG_3),
REG32("INT_CFG4", GNINT_CFG_4),
REG32("INT_CFG5", GNINT_CFG_5),
REG32("INT_CFG6", GNINT_CFG_6),
REG32("INT_CFG7", GNINT_CFG_7),
REG32("GPIO_BYPASS_MODE", GNGPIO_BYPASS_MODE),
REG32("GPIO_DIRECTION_MODE", GNGPIO_DIRECTION_MODE),
REG32("GPIO_OUTPUT_ENABLE", GNGPIO_OUTPUT_ENABLE),
REG32("GPIO_OUTPUT_VALUE", GNGPIO_OUTPUT_VALUE),
REG32("GPIO_INPUT_VALUE", GNGPIO_INPUT_VALUE),
REG32("GPIO_INT_MASK", GNGPIO_INT_MASK),
REG32("GPIO_INT_MASK_CLR", GNGPIO_INT_MASK_CLR),
REG32("GPIO_INT_MASK_SET", GNGPIO_INT_MASK_SET),
REG32("GPIO_INT_STATUS", GNGPIO_INT_STATUS),
REG32("GPIO_INT_TYPE", GNGPIO_INT_TYPE),
REG32("GPIO_INT_VALUE", GNGPIO_INT_VALUE),
REG32("GPIO_INT_ON_ANY", GNGPIO_INT_ON_ANY),
};
static int gn412x_dbg_init(struct gn412x_gpio_dev *gn412x)
{
struct dentry *dir, *file;
int err;
dir = debugfs_create_dir(dev_name(gn412x->gpiochip.dev), NULL);
if (IS_ERR_OR_NULL(dir)) {
err = PTR_ERR(dir);
dev_warn(gn412x->gpiochip.dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(gn412x->gpiochip.dev), err);
goto err_dir;
}
gn412x->dbg_reg32.regs = gn412x_debugfs_reg32;
gn412x->dbg_reg32.nregs = ARRAY_SIZE(gn412x_debugfs_reg32);
gn412x->dbg_reg32.base = gn412x->mem;
file = debugfs_create_regset32(GN412X_DBG_REG_NAME, 0200,
dir, &gn412x->dbg_reg32);
if (IS_ERR_OR_NULL(file)) {
err = PTR_ERR(file);
dev_warn(gn412x->gpiochip.dev,
"Cannot create debugfs file \"%s\" (%d)\n",
GN412X_DBG_REG_NAME, err);
goto err_reg32;
}
gn412x->dbg_dir = dir;
gn412x->dbg_reg = file;
return 0;
err_reg32:
debugfs_remove_recursive(dir);
err_dir:
return err;
}
static void gn412x_dbg_exit(struct gn412x_gpio_dev *gn412x)
{
debugfs_remove_recursive(gn412x->dbg_dir);
}
static uint32_t gn412x_ioread32(struct gn412x_gpio_dev *gn412x,
int reg)
{
return ioread32(gn412x->mem + reg);
}
static void gn412x_iowrite32(struct gn412x_gpio_dev *gn412x,
uint32_t val, int reg)
{
return iowrite32(val, gn412x->mem + reg);
}
static int gn412x_gpio_reg_read(struct gpio_chip *chip,
int reg, unsigned int offset)
{
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(chip);
return gn412x_ioread32(gn412x, reg) & BIT(offset);
}
static void gn412x_gpio_reg_write(struct gpio_chip *chip,
int reg, unsigned int offset, int value)
{
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(chip);
uint32_t regval;
regval = gn412x_ioread32(gn412x, reg);
if (value)
regval |= BIT(offset);
else
regval &= ~BIT(offset);
gn412x_iowrite32(gn412x, regval, reg);
}
/**
* Enable GPIO interrupts
* @gn412x gn412x device
*
* Return: 0 on success, otherwise a negative error number
*/
static void gn412x_gpio_int_cfg_enable(struct gn412x_gpio_dev *gn412x)
{
uint32_t int_cfg;
int_cfg = gn412x_ioread32(gn412x, GNINT_CFG(gn412x->pdata->int_cfg));
int_cfg |= GNINT_STAT_GPIO;
gn412x_iowrite32(gn412x, int_cfg, GNINT_CFG(gn412x->pdata->int_cfg));
}
/**
* Disable GPIO interrupts from a single configuration space
* @gn412x gn412x device
*
* Return: 0 on success, otherwise a negative error number
*/
static void gn412x_gpio_int_cfg_disable(struct gn412x_gpio_dev *gn412x)
{
uint32_t int_cfg;
int_cfg = gn412x_ioread32(gn412x, GNINT_CFG(gn412x->pdata->int_cfg));
int_cfg &= ~GNINT_STAT_GPIO;
gn412x_iowrite32(gn412x, int_cfg, GNINT_CFG(gn412x->pdata->int_cfg));
}
static int gn412x_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
int val;
val = gn412x_gpio_reg_read(chip, GNGPIO_BYPASS_MODE, offset);
if (val) {
dev_err(chip->dev, "%s GPIO %d is in BYPASS mode\n",
chip->label, offset);
return -EBUSY;
}
return 0;
}
static void gn412x_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
/* set it as input to avoid to drive anything */
gn412x_gpio_reg_write(chip, GNGPIO_DIRECTION_MODE, offset, 1);
}
static int gn412x_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
return !gn412x_gpio_reg_read(chip, GNGPIO_DIRECTION_MODE, offset);
}
static int gn412x_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
gn412x_gpio_reg_write(chip, GNGPIO_DIRECTION_MODE, offset, 1);
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_ENABLE, offset, 0);
return 0;
}
static int gn412x_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
gn412x_gpio_reg_write(chip, GNGPIO_DIRECTION_MODE, offset, 0);
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_ENABLE, offset, 1);
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_VALUE, offset, value);
return 0;
}
static int gn412x_gpio_get(struct gpio_chip *chip,
unsigned int offset)
{
return gn412x_gpio_reg_read(chip, GNGPIO_INPUT_VALUE, offset);
}
static void gn412x_gpio_set(struct gpio_chip *chip,
unsigned int offset, int value)
{
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_VALUE, offset, value);
}
/**
* (disable)
*/
static void gn412x_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(gc);
gn412x_iowrite32(gn412x, BIT(d->hwirq), GNGPIO_INT_MASK_SET);
}
/**
* (enable)
*/
static void gn412x_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(gc);
gn412x_iowrite32(gn412x, BIT(d->hwirq), GNGPIO_INT_MASK_CLR);
}
static int gn412x_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
/*
* detect errors:
* - level and edge together cannot work
*/
if ((flow_type & IRQ_TYPE_LEVEL_MASK) &&
(flow_type & IRQ_TYPE_EDGE_BOTH)) {
dev_err(gc->dev,
"Impossible to set GPIO IRQ %ld to both LEVEL and EDGE (0x%x)\n",
d->hwirq, flow_type);
return -EINVAL;
}
/* Configure: level or edge (default)? */
if (flow_type & IRQ_TYPE_LEVEL_MASK) {
gn412x_gpio_reg_write(gc, GNGPIO_INT_TYPE, d->hwirq, 1);
} else {
gn412x_gpio_reg_write(gc, GNGPIO_INT_TYPE, d->hwirq, 0);
/* if we want to trigger on any edge */
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
gn412x_gpio_reg_write(gc, GNGPIO_INT_ON_ANY,
d->hwirq, 1);
}
/* Configure: level-low or falling-edge, level-high or raising-edge */
if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
gn412x_gpio_reg_write(gc, GNGPIO_INT_VALUE, d->hwirq, 0);
else
gn412x_gpio_reg_write(gc, GNGPIO_INT_VALUE, d->hwirq, 1);
return IRQ_SET_MASK_OK;
}
/**
* A new IRQ interrupt has been requested
* @d IRQ related data
*
* We need to set the GPIO line to be input and disable completely any
* kind of output. We do not want any alternative function (bypass mode).
*/
static unsigned int gn412x_gpio_irq_startup(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
gn412x_gpio_reg_write(gc, GNGPIO_BYPASS_MODE, d->hwirq, 0);
gn412x_gpio_reg_write(gc, GNGPIO_DIRECTION_MODE, d->hwirq, 1);
gn412x_gpio_reg_write(gc, GNGPIO_OUTPUT_ENABLE, d->hwirq, 0);
gn412x_gpio_direction_input(gc, d->hwirq);
/* FIXME in the original code we had this? What is it? */
/* !!(gennum_readl(spec, GNGPIO_INPUT_VALUE) & bit); */
gn412x_gpio_irq_unmask(d);
return 0;
}
/**
* It disables the GPIO interrupt by masking it
*/
static void gn412x_gpio_irq_disable(struct irq_data *d)
{
gn412x_gpio_irq_mask(d);
}
static void gn412x_gpio_irq_ack(struct irq_data *d)
{
/*
* based on HW design,there is no need to ack HW
* before handle current irq. But this routine is
* necessary for handle_edge_irq
*/
}
static struct irq_chip gn412x_gpio_irq_chip = {
.name = "GN412X-GPIO",
.irq_startup = gn412x_gpio_irq_startup,
.irq_disable = gn412x_gpio_irq_disable,
.irq_mask = gn412x_gpio_irq_mask,
.irq_unmask = gn412x_gpio_irq_unmask,
.irq_set_type = gn412x_gpio_irq_set_type,
.irq_ack = gn412x_gpio_irq_ack,
};
/**
* This will run in hard-IRQ context since we do not have much to do
*/
static irqreturn_t spec_irq_sw_handler(int irq, void *arg)
{
struct gn412x_gpio_dev *gn412x = arg;
/* Ack the interrupts */
gn412x_ioread32(gn412x, GNINT_STAT);
gn412x_iowrite32(gn412x, 0x0000, GNINT_STAT);
complete(&gn412x->compl);
return IRQ_HANDLED;
}
/**
* Handle IRQ from the GPIO block
*/
static irqreturn_t gn412x_gpio_irq_handler_t(int irq, void *arg)
{
struct gn412x_gpio_dev *gn412x = arg;
struct gpio_chip *gc = &gn412x->gpiochip;
unsigned int cascade_irq;
uint32_t gpio_int_status, gpio_int_type;
unsigned long loop;
irqreturn_t ret = IRQ_NONE;
int i;
gpio_int_status = gn412x_ioread32(gn412x, GNGPIO_INT_STATUS);
gpio_int_status &= ~gn412x_ioread32(gn412x, GNGPIO_INT_MASK);
if (!gpio_int_status)
goto out_enable_irq;
loop = gpio_int_status;
for_each_set_bit(i, &loop, GN4124_GPIO_MAX) {
cascade_irq = irq_find_mapping(gc->irqdomain, i);
dev_dbg(gc->dev, "GPIO: %d, IRQ: %d\n", i, cascade_irq);
/*
* Ok, now we execute the handler for the given IRQ. Please
* note that this is not the action requested by the device
* driver but it is the handler defined during the IRQ mapping
*/
handle_nested_irq(cascade_irq);
}
/*
* Level interrupts are cleared only when they are processed. This
* means that at this point (interrupts have been processed) the
* GPIO_INT_STATUS is still set because it is a sticky bit that got
* set again after our first read because we did not handle yet
* the IRQ. For this reason we have to clear it (defentivelly) by
* reading again the register ...
*/
gpio_int_status = gn412x_ioread32(gn412x, GNGPIO_INT_STATUS);
/*
* ... but like this edge interrupts are lost. So write back
* in the register the status of all pending edge interrupts.
* (NOTE: not yet prooven that it works)
*/
gpio_int_type = gn412x_ioread32(gn412x, GNGPIO_INT_TYPE);
gn412x_iowrite32(gn412x, (gpio_int_status & (~gpio_int_type)),
GNGPIO_INT_STATUS);
ret = IRQ_HANDLED;
out_enable_irq:
/* Re-enable the GPIO interrupts, we are done here */
gn412x_gpio_int_cfg_enable(gn412x);
return ret;
}
static irqreturn_t gn412x_gpio_irq_handler_h(int irq, void *arg)
{
struct gn412x_gpio_dev *gn412x = arg;
uint32_t int_stat, int_cfg;
int_cfg = gn412x_ioread32(gn412x, GNINT_CFG(gn412x->pdata->int_cfg));
int_stat = gn412x_ioread32(gn412x, GNINT_STAT);
if (unlikely(!(int_stat & int_cfg)))
return IRQ_NONE;
if (unlikely(int_stat & GNINT_STAT_SW_ALL)) /* only for testing */
return spec_irq_sw_handler(irq, gn412x);
/*
* Do not listen to new interrupts while handling the current GPIOs.
* This may take a while since the chain behind each GPIO can be long.
* If the IRQ behind is level, we do not want this IRQ handeler to be
* called continuously. But on the other hand we do not want other
* devices sharing the same IRQ to wait for us; just to play safe,
* let's disable interrupts. Within the thread we will re-enable them
* when we are ready (like IRQF_ONESHOT).
*/
gn412x_gpio_int_cfg_disable(gn412x);
return IRQ_WAKE_THREAD;
}
static void gn412x_gpio_irq_set_nested_thread(struct gn412x_gpio_dev *gn412x,
unsigned int gpio, bool nest)
{
int irq;
irq = irq_find_mapping(gn412x->gpiochip.irqdomain, gpio);
irq_set_nested_thread(irq, nest);
}
static void gn412x_gpio_irq_set_nested_thread_all(struct gn412x_gpio_dev *gn412x,
bool nest)
{
int i;
for (i = 0; i < GN4124_GPIO_MAX; ++i)
gn412x_gpio_irq_set_nested_thread(gn412x, i, nest);
}
static int gn412x_gpio_probe(struct platform_device *pdev)
{
struct gn412x_gpio_dev *gn412x;
struct resource *r;
int err;
gn412x = devm_kzalloc(&pdev->dev, sizeof(*gn412x), GFP_KERNEL);
if (!gn412x)
return -ENOMEM;
platform_set_drvdata(pdev, gn412x);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(&pdev->dev, "Missing memory resource\n");
err = -EINVAL;
goto err_res_mem;
}
gn412x->mem = devm_ioremap(&pdev->dev, r->start, resource_size(r));
if (!gn412x->mem) {
err = -EADDRNOTAVAIL;
goto err_map;
}
gn412x->pdata = dev_get_platdata(&pdev->dev);
if (!gn412x->pdata) {
dev_warn(&pdev->dev, "Missing platform data, use default\n");
gn412x->pdata = &gn412x_gpio_pdata_default;
}
gn412x_iowrite32(gn412x, 0, GNGPIO_BYPASS_MODE);
gn412x->gpiochip.dev = &pdev->dev;
gn412x->gpiochip.label = "gn412x-gpio";
gn412x->gpiochip.owner = THIS_MODULE;
gn412x->gpiochip.request = gn412x_gpio_request;
gn412x->gpiochip.free = gn412x_gpio_free;
gn412x->gpiochip.get_direction = gn412x_gpio_get_direction;
gn412x->gpiochip.direction_input = gn412x_gpio_direction_input;
gn412x->gpiochip.direction_output = gn412x_gpio_direction_output;
gn412x->gpiochip.get = gn412x_gpio_get;
gn412x->gpiochip.set = gn412x_gpio_set;
gn412x->gpiochip.base = -1;
gn412x->gpiochip.ngpio = GN4124_GPIO_MAX;
gn412x->gpiochip.can_sleep = 0;
err = gpiochip_add(&gn412x->gpiochip);
if (err)
goto err_add;
gn412x_gpio_int_cfg_disable(gn412x);
gn412x_iowrite32(gn412x, 0xFFFF, GNGPIO_INT_MASK_SET);
err = gpiochip_irqchip_add(&gn412x->gpiochip,
&gn412x_gpio_irq_chip,
0, handle_simple_irq,
IRQ_TYPE_NONE);
if (err)
goto err_add_irq;
gn412x_gpio_irq_set_nested_thread_all(gn412x, true);
err = request_threaded_irq(platform_get_irq(pdev, 0),
gn412x_gpio_irq_handler_h,
gn412x_gpio_irq_handler_t,
IRQF_SHARED,
dev_name(gn412x->gpiochip.dev),
gn412x);
if (err) {
dev_err(gn412x->gpiochip.dev, "Can't request IRQ %d (%d)\n",
platform_get_irq(pdev, 0), err);
goto err_req;
}
gn412x_gpio_int_cfg_enable(gn412x);
gn412x_dbg_init(gn412x);
return 0;
err_req:
gn412x_gpio_irq_set_nested_thread_all(gn412x, false);
err_add_irq:
gpiochip_remove(&gn412x->gpiochip);
err_add:
devm_iounmap(&pdev->dev, gn412x->mem);
err_map:
err_res_mem:
devm_kfree(&pdev->dev, gn412x);
return err;
}
static int gn412x_gpio_remove(struct platform_device *pdev)
{
struct gn412x_gpio_dev *gn412x = platform_get_drvdata(pdev);
gn412x_dbg_exit(gn412x);
gn412x_gpio_int_cfg_disable(gn412x);
free_irq(platform_get_irq(pdev, 0), gn412x);
gn412x_gpio_irq_set_nested_thread_all(gn412x, false);
gpiochip_remove(&gn412x->gpiochip);
dev_dbg(&pdev->dev, "%s\n", __func__);
return 0;
}
static const struct platform_device_id gn412x_gpio_id[] = {
{
.name = "gn412x-gpio",
},
{ .name = "" }, /* last */
};
static struct platform_driver gn412x_gpio_platform_driver = {
.driver = {
.name = KBUILD_MODNAME,
},
.probe = gn412x_gpio_probe,
.remove = gn412x_gpio_remove,
.id_table = gn412x_gpio_id,
};
module_platform_driver(gn412x_gpio_platform_driver);
MODULE_AUTHOR("Federico Vaga <federico.vaga@cern.ch>");
MODULE_DESCRIPTION("GN412X GPIO driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(VERSION);
MODULE_DEVICE_TABLE(platform, gn412x_gpio_id);
software/kernel/gn412x.h 0 → 100644
View file @ 204ff681
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2010-2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#ifndef __GN412X_H__
#define __GN412X_H__
#define GNINT_STAT_GPIO BIT(15)
#define GNINT_STAT_SW0 BIT(2)
#define GNINT_STAT_SW1 BIT(3)
#define GNINT_STAT_SW_ALL (GNINT_STAT_SW0 | GNINT_STAT_SW1)
/* Registers for GN4124 access */
enum {
/* page 106 */
GNPPCI_MSI_CONTROL = 0x48, /* actually, 3 smaller regs */
GNPPCI_MSI_ADDRESS_LOW = 0x4c,
GNPPCI_MSI_ADDRESS_HIGH = 0x50,
GNPPCI_MSI_DATA = 0x54,
GNPCI_SYS_CFG_SYSTEM = 0x800,
/* page 130 ff */
GNINT_CTRL = 0x810,
GNINT_STAT = 0x814,
GNINT_CFG_0 = 0x820,
GNINT_CFG_1 = 0x824,
GNINT_CFG_2 = 0x828,
GNINT_CFG_3 = 0x82c,
GNINT_CFG_4 = 0x830,
GNINT_CFG_5 = 0x834,
GNINT_CFG_6 = 0x838,
GNINT_CFG_7 = 0x83c,
#define GNINT_CFG(x) (GNINT_CFG_0 + 4 * (x))
/* page 146 ff */
GNGPIO_BASE = 0xA00,
GNGPIO_BYPASS_MODE = GNGPIO_BASE,
GNGPIO_DIRECTION_MODE = GNGPIO_BASE + 0x04, /* 0 == output */
GNGPIO_OUTPUT_ENABLE = GNGPIO_BASE + 0x08,
GNGPIO_OUTPUT_VALUE = GNGPIO_BASE + 0x0C,
GNGPIO_INPUT_VALUE = GNGPIO_BASE + 0x10,
GNGPIO_INT_MASK = GNGPIO_BASE + 0x14, /* 1 == disabled */
GNGPIO_INT_MASK_CLR = GNGPIO_BASE + 0x18, /* irq enable */
GNGPIO_INT_MASK_SET = GNGPIO_BASE + 0x1C, /* irq disable */
GNGPIO_INT_STATUS = GNGPIO_BASE + 0x20,
GNGPIO_INT_TYPE = GNGPIO_BASE + 0x24, /* 1 == level */
GNGPIO_INT_VALUE = GNGPIO_BASE + 0x28, /* 1 == high/rise */
GNGPIO_INT_ON_ANY = GNGPIO_BASE + 0x2C, /* both edges */
/* page 158 ff */
FCL_BASE = 0xB00,
FCL_CTRL = FCL_BASE,
FCL_STATUS = FCL_BASE + 0x04,
FCL_IODATA_IN = FCL_BASE + 0x08,
FCL_IODATA_OUT = FCL_BASE + 0x0C,
FCL_EN = FCL_BASE + 0x10,
FCL_TIMER_0 = FCL_BASE + 0x14,
FCL_TIMER_1 = FCL_BASE + 0x18,
FCL_CLK_DIV = FCL_BASE + 0x1C,
FCL_IRQ = FCL_BASE + 0x20,
FCL_TIMER_CTRL = FCL_BASE + 0x24,
FCL_IM = FCL_BASE + 0x28,
FCL_TIMER2_0 = FCL_BASE + 0x2C,
FCL_TIMER2_1 = FCL_BASE + 0x30,
FCL_DBG_STS = FCL_BASE + 0x34,
FCL_FIFO = 0xE00,
PCI_SYS_CFG_SYSTEM = 0x800
};
#endif
software/kernel/platform_data/gn412x-gpio.h 0 → 100644
View file @ 204ff681
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#ifndef __GN412X_GPIO_H__
#define __GN412X_GPIO_H__
struct gn412x_platform_data {
unsigned int int_cfg;
};
#endif
software/kernel/spec-compat.c 0 → 100644
View file @ 204ff681
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#include <linux/kallsyms.h>
#include <linux/module.h>
#include <linux/fpga/fpga-mgr.h>
#include <linux/mfd/core.h>
#include <linux/version.h>
#include <linux/gpio/driver.h>
#include "spec-compat.h"
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
struct fpga_manager *__fpga_mgr_get(struct device *dev)
{
struct fpga_manager *mgr;
int ret = -ENODEV;
mgr = to_fpga_manager(dev);
if (!mgr)
goto err_dev;
/* Get exclusive use of fpga manager */
if (!mutex_trylock(&mgr->ref_mutex)) {
ret = -EBUSY;
goto err_dev;
}
if (!try_module_get(dev->parent->driver->owner))
goto err_ll_mod;
return mgr;
err_ll_mod:
mutex_unlock(&mgr->ref_mutex);
err_dev:
put_device(dev);
return ERR_PTR(ret);
}
static int fpga_mgr_dev_match(struct device *dev, const void *data)
{
return dev->parent == data;
}
/**
* fpga_mgr_get - get an exclusive reference to a fpga mgr
* @dev:parent device that fpga mgr was registered with
*
* Given a device, get an exclusive reference to a fpga mgr.
*
* Return: fpga manager struct or IS_ERR() condition containing error code.
*/
struct fpga_manager *fpga_mgr_get(struct device *dev)
{
struct class *fpga_mgr_class = (struct class *) kallsyms_lookup_name("fpga_mgr_class");
struct device *mgr_dev;
mgr_dev = class_find_device(fpga_mgr_class, NULL, dev, fpga_mgr_dev_match);
if (!mgr_dev)
return ERR_PTR(-ENODEV);
return __fpga_mgr_get(mgr_dev);
}
#endif
static int __compat_spec_fw_load(struct fpga_manager *mgr, const char *name)
{
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE
return fpga_mgr_firmware_load(mgr, 0, name);
#else
struct fpga_image_info image;
memset(&image, 0, sizeof(image));
return fpga_mgr_firmware_load(mgr, &image, name);
#endif
#else
struct fpga_image_info image;
memset(&image, 0, sizeof(image));
image.firmware_name = (char *)name;
image.dev = mgr->dev.parent;
return fpga_mgr_load(mgr, &image);
#endif
}
struct mfd_find_data {
const char *name;
int id;
};
static int mfd_find_device_match(struct device *dev, void *data)
{
struct mfd_find_data *d = data;
struct platform_device *pdev = to_platform_device(dev);
if (strncmp(d->name, mfd_get_cell(pdev)->name,
strnlen(d->name, 32)) != 0)
return 0;
if (d->id >= 0 && pdev->id != d->id)
return 0;
return 1;
}
static struct platform_device *mfd_find_device(struct device *parent,
const char *name,
int id)
{
struct mfd_find_data d = {name, id};
struct device *dev;
dev = device_find_child(parent, (void *)&d, mfd_find_device_match);
if (!dev)
return NULL;
return to_platform_device(dev);
}
int compat_spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name)
{
struct fpga_manager *mgr;
struct platform_device *fpga_pdev;
int err;
fpga_pdev = mfd_find_device(&spec_gn412x->pdev->dev, "gn412x-fcl", -1);
if (!fpga_pdev)
return -ENODEV;
mgr = fpga_mgr_get(&fpga_pdev->dev);
if (IS_ERR(mgr))
return -ENODEV;
err = fpga_mgr_lock(mgr);
if (err)
goto out;
err = __compat_spec_fw_load(mgr, name);
fpga_mgr_unlock(mgr);
out:
fpga_mgr_put(mgr);
return err;
}
int compat_gpiod_add_lookup_table(struct gpiod_lookup_table *table)
{
void (*gpiod_add_lookup_table_p)(struct gpiod_lookup_table *table);
gpiod_add_lookup_table_p = (void *) kallsyms_lookup_name("gpiod_add_lookup_table");
if (gpiod_add_lookup_table_p)
gpiod_add_lookup_table_p(table);
else
return WARN(1, "Cannot find 'gpiod_add_lookup_table'");
return 0;
}
#if KERNEL_VERSION(4, 3, 0) > LINUX_VERSION_CODE
void gpiod_remove_lookup_table(struct gpiod_lookup_table *table)
{
struct mutex *gpio_lookup_lock_p = (void *) kallsyms_lookup_name("gpio_lookup_lock");
mutex_lock(gpio_lookup_lock_p);
list_del(&table->list);
mutex_unlock(gpio_lookup_lock_p);
}
#endif
software/kernel/spec-compat.h 0 → 100644
View file @ 204ff681
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#ifndef __SPEC_COMPAT_H__
#define __SPEC_COMPAT_H__
#include <linux/fpga/fpga-mgr.h>
#include <linux/types.h>
#include <linux/version.h>
#include <linux/gpio/driver.h>
#include "spec.h"
#if KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE
/* So that we select the buffer size because smaller */
#define compat_fpga_ops_initial_header_size .initial_header_size = 0xFFFFFFFF,
#else
#define compat_fpga_ops_initial_header_size .initial_header_size = 0,
#endif
#else
#define compat_fpga_ops_initial_header_size
#endif
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
#define compat_fpga_ops_groups
#else
#define compat_fpga_ops_groups .groups = NULL,
#endif
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
struct fpga_image_info;
#endif
int compat_spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name);
#if KERNEL_VERSION(3, 11, 0) > LINUX_VERSION_CODE
#define __ATTR_RW(_name) __ATTR(_name, (S_IWUSR | S_IRUGO), \
_name##_show, _name##_store)
#define __ATTR_WO(_name) { \
.attr = { .name = __stringify(_name), .mode = S_IWUSR }, \
.store = _name##_store, \
}
#define DEVICE_ATTR_RW(_name) \
struct device_attribute dev_attr_##_name = __ATTR_RW(_name)
#define DEVICE_ATTR_RO(_name) \
struct device_attribute dev_attr_##_name = __ATTR_RO(_name)
#define DEVICE_ATTR_WO(_name) \
struct device_attribute dev_attr_##_name = __ATTR_WO(_name)
#endif
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE
#define GPIO_PERSISTENT (0 << 3)
#endif
extern int compat_gpiod_add_lookup_table(struct gpiod_lookup_table *table);
#if KERNEL_VERSION(4, 3, 0) > LINUX_VERSION_CODE
extern void gpiod_remove_lookup_table(struct gpiod_lookup_table *table);
#endif
#endif /* __SPEC_COMPAT_H__ */
software/kernel/spec-core-fpga.c 0 → 100644
View file @ 204ff681
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#include <linux/types.h>
#include <linux/platform_data/i2c-ocores.h>
#include <linux/platform_data/spi-ocores.h>
#include <linux/ioport.h>
#include <linux/gpio/consumer.h>
#include <linux/irqdomain.h>
#include <linux/mfd/core.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/bitops.h>
#include <linux/fmc.h>
#include <linux/delay.h>
#include "spec.h"
#include "spec-compat.h"
enum spec_fpga_irq_lines {
SPEC_FPGA_IRQ_FMC_I2C = 0,
SPEC_FPGA_IRQ_SPI,
SPEC_FPGA_IRQ_DMA_DONE,
};
enum spec_fpga_csr_offsets {
SPEC_FPGA_CSR_APP_OFF = SPEC_BASE_REGS_CSR + 0x00,
SPEC_FPGA_CSR_RESETS = SPEC_BASE_REGS_CSR + 0x04,
SPEC_FPGA_CSR_FMC_PRESENT = SPEC_BASE_REGS_CSR + 0x08,
SPEC_FPGA_CSR_GN4124_STATUS = SPEC_BASE_REGS_CSR + 0x0C,
SPEC_FPGA_CSR_DDR_STATUS = SPEC_BASE_REGS_CSR + 0x10,
SPEC_FPGA_CSR_PCB_REV = SPEC_BASE_REGS_CSR + 0x14,
};
enum spec_fpga_csr_fields {
SPEC_FPGA_CSR_DDR_STATUS_DONE = 0x1,
};
enum spec_fpga_therm_offsets {
SPEC_FPGA_THERM_SERID_MSB = SPEC_BASE_REGS_THERM_ID + 0x0,
SPEC_FPGA_THERM_SERID_LSB = SPEC_BASE_REGS_THERM_ID + 0x4,
SPEC_FPGA_THERM_TEMP = SPEC_BASE_REGS_THERM_ID + 0x8,
};
enum spec_fpga_meta_cap_mask {
SPEC_META_CAP_VIC = BIT(0),
SPEC_META_CAP_THERM = BIT(1),
SPEC_META_CAP_SPI = BIT(2),
SPEC_META_CAP_WR = BIT(3),
SPEC_META_CAP_BLD = BIT(4),
SPEC_META_CAP_DMA = BIT(5),
};
static const struct debugfs_reg32 spec_fpga_debugfs_reg32[] = {
{
.name = "Application offset",
.offset = SPEC_FPGA_CSR_APP_OFF,
},
{
.name = "Resets",
.offset = SPEC_FPGA_CSR_RESETS,
},
{
.name = "FMC present",
.offset = SPEC_FPGA_CSR_FMC_PRESENT,
},
{
.name = "GN4124 Status",
.offset = SPEC_FPGA_CSR_GN4124_STATUS,
},
{
.name = "DDR Status",
.offset = SPEC_FPGA_CSR_DDR_STATUS,
},
{
.name = "PCB revision",
.offset = SPEC_FPGA_CSR_PCB_REV,
},
};
static int spec_fpga_dbg_bld_info(struct seq_file *s, void *offset)
{
struct spec_fpga *spec_fpga = s->private;
int off;
if (!(spec_fpga->meta->cap & SPEC_META_CAP_BLD)) {
seq_puts(s, "not available\n");
return 0;
}
for (off = SPEC_BASE_REGS_BUILDINFO;
off < SPEC_BASE_REGS_BUILDINFO + SPEC_BASE_REGS_BUILDINFO_SIZE -1;
off++) {
char tmp = ioread8(spec_fpga->fpga + off);
if (!tmp)
return 0;
seq_putc(s, tmp);
}
return 0;
}
static int spec_fpga_dbg_bld_info_open(struct inode *inode,
struct file *file)
{
struct spec_gn412x *spec = inode->i_private;
return single_open(file, spec_fpga_dbg_bld_info, spec);
}
static const struct file_operations spec_fpga_dbg_bld_info_ops = {
.owner = THIS_MODULE,
.open = spec_fpga_dbg_bld_info_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int spec_fpga_dbg_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pdev = to_pci_dev(spec_fpga->dev.parent);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
int err;
spec_fpga->dbg_dir_fpga = debugfs_create_dir(dev_name(&spec_fpga->dev),
spec_gn412x->dbg_dir);
if (IS_ERR_OR_NULL(spec_fpga->dbg_dir_fpga)) {
err = PTR_ERR(spec_fpga->dbg_dir_fpga);
dev_err(&spec_fpga->dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(&spec_fpga->dev), err);
return err;
}
spec_fpga->dbg_csr_reg.regs = spec_fpga_debugfs_reg32;
spec_fpga->dbg_csr_reg.nregs = ARRAY_SIZE(spec_fpga_debugfs_reg32);
spec_fpga->dbg_csr_reg.base = spec_fpga->fpga;
spec_fpga->dbg_csr = debugfs_create_regset32(SPEC_DBG_CSR_NAME, 0200,
spec_fpga->dbg_dir_fpga,
&spec_fpga->dbg_csr_reg);
if (IS_ERR_OR_NULL(spec_fpga->dbg_csr)) {
err = PTR_ERR(spec_fpga->dbg_csr);
dev_warn(&spec_fpga->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
SPEC_DBG_CSR_NAME, err);
goto err;
}
spec_fpga->dbg_bld_info = debugfs_create_file(SPEC_DBG_BLD_INFO_NAME, 0444,
spec_fpga->dbg_dir_fpga,
spec_fpga,
&spec_fpga_dbg_bld_info_ops);
if (IS_ERR_OR_NULL(spec_fpga->dbg_bld_info)) {
err = PTR_ERR(spec_fpga->dbg_bld_info);
dev_err(&spec_fpga->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
SPEC_DBG_BLD_INFO_NAME, err);
goto err;
}
return 0;
err:
debugfs_remove_recursive(spec_fpga->dbg_dir_fpga);
return err;
}
static void spec_fpga_dbg_exit(struct spec_fpga *spec_fpga)
{
debugfs_remove_recursive(spec_fpga->dbg_dir_fpga);
}
static inline uint32_t spec_fpga_csr_app_offset(struct spec_fpga *spec_fpga)
{
return ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_APP_OFF);
}
static inline uint32_t spec_fpga_csr_pcb_rev(struct spec_fpga *spec_fpga)
{
return ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_PCB_REV);
}
static struct resource spec_fpga_vic_res[] = {
{
.name = "htvic-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_BASE_REGS_VIC,
.end = SPEC_BASE_REGS_VIC + SPEC_BASE_REGS_VIC_SIZE -1,
}, {
.name = "htvic-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = 0,
.end = 0,
},
};
/* Vector Interrupt Controller */
static int spec_fpga_vic_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pcidev);
unsigned long pci_start = pci_resource_start(pcidev, 0);
const unsigned int res_n = ARRAY_SIZE(spec_fpga_vic_res);
struct resource res[ARRAY_SIZE(spec_fpga_vic_res)];
struct platform_device *pdev;
if (!(spec_fpga->meta->cap & SPEC_META_CAP_VIC))
return 0;
memcpy(&res, spec_fpga_vic_res, sizeof(spec_fpga_vic_res));
res[0].start += pci_start;
res[0].end += pci_start;
res[1].start = gpiod_to_irq(spec_gn412x->gpiod[GN4124_GPIO_IRQ1]);
res[1].end = res[1].start;
pdev = platform_device_register_resndata(&spec_fpga->dev,
"htvic-spec",
PLATFORM_DEVID_AUTO,
res, res_n,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
spec_fpga->vic_pdev = pdev;
return 0;
}
static void spec_fpga_vic_exit(struct spec_fpga *spec_fpga)
{
if (spec_fpga->vic_pdev) {
platform_device_unregister(spec_fpga->vic_pdev);
spec_fpga->vic_pdev = NULL;
}
}
/* DMA engine */
static struct resource spec_fpga_dma_res[] = {
{
.name = "spec-gn412x-dma-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_BASE_REGS_DMA,
.end = SPEC_BASE_REGS_DMA + SPEC_BASE_REGS_DMA_SIZE - 1,
}, {
.name = "spec-gn412x-dma-irq-done",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = 0,
.end = 0,
},
};
static int spec_fpga_dma_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
unsigned long pci_start = pci_resource_start(pcidev, 0);
const unsigned int res_n = ARRAY_SIZE(spec_fpga_dma_res);
struct resource res[ARRAY_SIZE(spec_fpga_dma_res)];
struct platform_device *pdev;
struct irq_domain *vic_domain;
uint32_t ddr_status;
if (!(spec_fpga->meta->cap & SPEC_META_CAP_DMA))
return 0;
mdelay(1);
ddr_status = ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_DDR_STATUS);
if (!(ddr_status & SPEC_FPGA_CSR_DDR_STATUS_DONE)) {
dev_err(&spec_fpga->dev,
"Failed to load DMA engine: DDR controller not calibrated - 0x%x.\n",
ddr_status);
return -ENODEV;
}
vic_domain = irq_find_host((void *)&spec_fpga->vic_pdev->dev);
if (!vic_domain) {
dev_err(&spec_fpga->dev,
"Failed to load DMA engine: missing can't find VIC.\n");
return -ENODEV;
}
memcpy(&res, spec_fpga_dma_res, sizeof(spec_fpga_dma_res));
res[0].start += pci_start;
res[0].end += pci_start;
res[1].start = irq_find_mapping(vic_domain, SPEC_FPGA_IRQ_DMA_DONE);
pdev = platform_device_register_resndata(&spec_fpga->dev,
"spec-gn412x-dma",
PLATFORM_DEVID_AUTO,
res, res_n,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
spec_fpga->dma_pdev = pdev;
return 0;
}
static void spec_fpga_dma_exit(struct spec_fpga *spec_fpga)
{
if (spec_fpga->dma_pdev) {
platform_device_unregister(spec_fpga->dma_pdev);
spec_fpga->dma_pdev = NULL;
}
}
/* MFD devices */
enum spec_fpga_mfd_devs_enum {
SPEC_FPGA_MFD_FMC_I2C = 0,
SPEC_FPGA_MFD_SPI,
};
static struct resource spec_fpga_fmc_i2c_res[] = {
{
.name = "i2c-ocores-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_BASE_REGS_FMC_I2C,
.end = SPEC_BASE_REGS_FMC_I2C + SPEC_BASE_REGS_FMC_I2C_SIZE -1,
}, {
.name = "i2c-ocores-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = SPEC_FPGA_IRQ_FMC_I2C,
.end = SPEC_FPGA_IRQ_FMC_I2C,
},
};
#define SPEC_FPGA_WB_CLK_HZ 62500000
#define SPEC_FPGA_WB_CLK_KHZ (SPEC_FPGA_WB_CLK_HZ / 1000)
static struct ocores_i2c_platform_data spec_fpga_fmc_i2c_pdata = {
.reg_shift = 2, /* 32bit aligned */
.reg_io_width = 4,
.clock_khz = SPEC_FPGA_WB_CLK_KHZ,
.big_endian = 0,
.num_devices = 0,
.devices = NULL,
};
static struct resource spec_fpga_spi_res[] = {
{
.name = "spi-ocores-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_BASE_REGS_FLASH_SPI,
.end = SPEC_BASE_REGS_FLASH_SPI + SPEC_BASE_REGS_FLASH_SPI_SIZE - 1,
}, {
.name = "spi-ocores-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = SPEC_FPGA_IRQ_SPI,
.end = SPEC_FPGA_IRQ_SPI,
},
};
struct flash_platform_data spec_flash_pdata = {
.name = "spec-flash",
.parts = NULL,
.nr_parts = 0,
.type = "m25p32",
};
static struct spi_board_info spec_fpga_spi_devices_info[] = {
{
.modalias = "m25p32",
.max_speed_hz = SPEC_FPGA_WB_CLK_HZ / 128,
.chip_select = 0,
.platform_data = &spec_flash_pdata,
}
};
static struct spi_ocores_platform_data spec_fpga_spi_pdata = {
.big_endian = 0,
.clock_hz = SPEC_FPGA_WB_CLK_HZ,
.num_devices = ARRAY_SIZE(spec_fpga_spi_devices_info),
.devices = spec_fpga_spi_devices_info,
};
static const struct mfd_cell spec_fpga_mfd_devs[] = {
[SPEC_FPGA_MFD_FMC_I2C] = {
.name = "i2c-ohwr",
.platform_data = &spec_fpga_fmc_i2c_pdata,
.pdata_size = sizeof(spec_fpga_fmc_i2c_pdata),
.num_resources = ARRAY_SIZE(spec_fpga_fmc_i2c_res),
.resources = spec_fpga_fmc_i2c_res,
},
[SPEC_FPGA_MFD_SPI] = {
.name = "spi-ocores",
.platform_data = &spec_fpga_spi_pdata,
.pdata_size = sizeof(spec_fpga_spi_pdata),
.num_resources = ARRAY_SIZE(spec_fpga_spi_res),
.resources = spec_fpga_spi_res,
},
};
static inline size_t __fpga_mfd_devs_size(void)
{
#define SPEC_FPGA_MFD_DEVS_MAX 4
return (sizeof(struct mfd_cell) * SPEC_FPGA_MFD_DEVS_MAX);
}
static int spec_fpga_devices_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
struct mfd_cell *fpga_mfd_devs;
struct irq_domain *vic_domain;
unsigned int n_mfd = 0;
int err;
fpga_mfd_devs = devm_kzalloc(&spec_fpga->dev,
__fpga_mfd_devs_size(),
GFP_KERNEL);
if (!fpga_mfd_devs)
return -ENOMEM;
memcpy(&fpga_mfd_devs[n_mfd],
&spec_fpga_mfd_devs[SPEC_FPGA_MFD_FMC_I2C],
sizeof(fpga_mfd_devs[n_mfd]));
n_mfd++;
if (spec_fpga->meta->cap & SPEC_META_CAP_SPI) {
memcpy(&fpga_mfd_devs[n_mfd],
&spec_fpga_mfd_devs[SPEC_FPGA_MFD_SPI],
sizeof(fpga_mfd_devs[n_mfd]));
n_mfd++;
}
vic_domain = irq_find_host((void *)&spec_fpga->vic_pdev->dev);
if (!vic_domain) {
/* Remove IRQ resource from all devices */
fpga_mfd_devs[0].num_resources = 1; /* FMC I2C */
fpga_mfd_devs[1].num_resources = 1; /* SPI */
}
err = mfd_add_devices(&spec_fpga->dev,
PLATFORM_DEVID_AUTO,
fpga_mfd_devs, n_mfd,
&pcidev->resource[0],
0, vic_domain);
if (err)
goto err_mfd;
return 0;
err_mfd:
devm_kfree(&spec_fpga->dev, fpga_mfd_devs);
return err;
}
static void spec_fpga_devices_exit(struct spec_fpga *spec_fpga)
{
mfd_remove_devices(&spec_fpga->dev);
}
/* Thermometer */
static ssize_t temperature_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
if (spec_fpga->meta->cap & SPEC_META_CAP_THERM) {
uint32_t temp = ioread32(spec_fpga->fpga + SPEC_FPGA_THERM_TEMP);
return snprintf(buf, PAGE_SIZE, "%d.%d C\n",
temp / 16, (temp & 0xF) * 1000 / 16);
} else {
return snprintf(buf, PAGE_SIZE, "-.- C\n");
}
}
static DEVICE_ATTR_RO(temperature);
static ssize_t serial_number_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
if (spec_fpga->meta->cap & SPEC_META_CAP_THERM) {
uint32_t msb = ioread32(spec_fpga->fpga + SPEC_FPGA_THERM_SERID_MSB);
uint32_t lsb = ioread32(spec_fpga->fpga + SPEC_FPGA_THERM_SERID_LSB);
return snprintf(buf, PAGE_SIZE, "0x%08x%08x\n", msb, lsb);
} else {
return snprintf(buf, PAGE_SIZE, "0x----------------\n");
}
}
static DEVICE_ATTR_RO(serial_number);
static struct attribute *spec_fpga_therm_attrs[] = {
&dev_attr_serial_number.attr,
&dev_attr_temperature.attr,
NULL,
};
static const struct attribute_group spec_fpga_therm_group = {
.name = "thermometer",
.attrs = spec_fpga_therm_attrs,
};
/* CSR attributes */
static ssize_t pcb_rev_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
return snprintf(buf, PAGE_SIZE, "0x%x\n",
spec_fpga_csr_pcb_rev(spec_fpga));
}
static DEVICE_ATTR_RO(pcb_rev);
static ssize_t application_offset_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
return snprintf(buf, PAGE_SIZE, "0x%x\n",
spec_fpga_csr_app_offset(spec_fpga));
}
static DEVICE_ATTR_RO(application_offset);
enum spec_fpga_csr_resets {
SPEC_FPGA_CSR_RESETS_ALL = BIT(0),
SPEC_FPGA_CSR_RESETS_APP = BIT(1),
};
static void spec_fpga_app_reset(struct spec_fpga *spec_fpga, bool val)
{
uint32_t resets;
resets = ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_RESETS);
if (val)
resets |= SPEC_FPGA_CSR_RESETS_APP;
else
resets &= ~SPEC_FPGA_CSR_RESETS_APP;
iowrite32(resets, spec_fpga->fpga + SPEC_FPGA_CSR_RESETS);
}
static void spec_fpga_app_restart(struct spec_fpga *spec_fpga)
{
spec_fpga_app_reset(spec_fpga, true);
udelay(1);
spec_fpga_app_reset(spec_fpga, false);
udelay(1);
}
static ssize_t reset_app_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
uint32_t resets;
resets = ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_RESETS);
return snprintf(buf, PAGE_SIZE, "%d\n",
!!(resets & SPEC_FPGA_CSR_RESETS_APP));
}
static ssize_t reset_app_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
spec_fpga_app_reset(to_spec_fpga(dev), val);
return count;
}
static DEVICE_ATTR(reset_app, 0644, reset_app_show, reset_app_store);
static struct attribute *spec_fpga_csr_attrs[] = {
&dev_attr_pcb_rev.attr,
&dev_attr_application_offset.attr,
&dev_attr_reset_app.attr,
NULL,
};
static const struct attribute_group spec_fpga_csr_group = {
.attrs = spec_fpga_csr_attrs,
};
/* FMC */
#define SPEC_FMC_SLOTS 1
static inline u8 spec_fmc_presence(struct spec_fpga *spec_fpga)
{
return (ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_FMC_PRESENT) & 0x1);
}
static int spec_fmc_is_present(struct fmc_carrier *carrier,
struct fmc_slot *slot)
{
struct spec_fpga *spec_fpga = carrier->priv;
return spec_fmc_presence(spec_fpga);
}
static const struct fmc_carrier_operations spec_fmc_ops = {
.owner = THIS_MODULE,
.is_present = spec_fmc_is_present,
};
static int spec_i2c_find_adapter(struct device *dev, void *data)
{
struct spec_fpga *spec_fpga = data;
struct i2c_adapter *adap, *adap_parent;
if (dev->type != &i2c_adapter_type)
return 0;
adap = to_i2c_adapter(dev);
adap_parent = i2c_parent_is_i2c_adapter(adap);
if (!adap_parent)
return 0;
/* We have a muxed I2C master */
if (&spec_fpga->dev != adap_parent->dev.parent->parent)
return 0;
/* Found! Return the bus ID */
return i2c_adapter_id(adap);
}
/**
* Get the I2C adapter associated with an FMC slot
* @data: data used to find the correct I2C bus
* @slot_nr: FMC slot number
*
* Return: the I2C bus to be used
*/
static int spec_i2c_get_bus(struct spec_fpga *spec_fpga)
{
return i2c_for_each_dev(spec_fpga, spec_i2c_find_adapter);
}
/**
* Create an FMC interface
*/
static int spec_fmc_init(struct spec_fpga *spec_fpga)
{
int err;
spec_fpga->slot_info.i2c_bus_nr = spec_i2c_get_bus(spec_fpga);
if (spec_fpga->slot_info.i2c_bus_nr <= 0)
return -ENODEV;
spec_fpga->slot_info.ga = 0;
spec_fpga->slot_info.lun = 1;
err = fmc_carrier_register(&spec_fpga->dev, &spec_fmc_ops,
SPEC_FMC_SLOTS, &spec_fpga->slot_info,
spec_fpga);
if (err) {
dev_err(spec_fpga->dev.parent,
"Failed to register as FMC carrier\n");
goto err_fmc;
}
return 0;
err_fmc:
return err;
}
static int spec_fmc_exit(struct spec_fpga *spec_fpga)
{
return fmc_carrier_unregister(&spec_fpga->dev);
}
/* FPGA Application */
/**
* Build the platform_device_id->name from metadata
*
* The byte order on SPEC is little endian, but we want to convert it
* in string. Use big-endian read to swap word and get the string order
* from MSB to LSB
*/
static int spec_fpga_app_id_build(struct spec_fpga *spec_fpga,
unsigned long app_off,
char *id, unsigned int size)
{
uint32_t vendor = ioread32be(spec_fpga->fpga + app_off + FPGA_META_VENDOR);
uint32_t device = ioread32be(spec_fpga->fpga + app_off + FPGA_META_DEVICE);
memset(id, 0, size);
if (vendor == 0xFF000000) {
dev_warn(&spec_fpga->dev, "Vendor UUID not supported yet\n");
return -ENODEV;
} else {
snprintf(id, size, "id:%4phN%4phN", &vendor, &device);
}
return 0;
}
static int spec_fpga_app_init(struct spec_fpga *spec_fpga)
{
#define SPEC_FPGA_APP_NAME_MAX 47
#define SPEC_FPGA_APP_IRQ_BASE 6
#define SPEC_FPGA_APP_RES_N (32 - SPEC_FPGA_APP_IRQ_BASE + 1)
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
unsigned int res_n = SPEC_FPGA_APP_RES_N;
struct resource res[SPEC_FPGA_APP_RES_N] = {
[0] = {
.name = "app-mem",
.flags = IORESOURCE_MEM,
},
};
struct platform_device *pdev;
struct irq_domain *vic_domain;
char app_name[SPEC_FPGA_APP_NAME_MAX];
unsigned long app_offset;
int err;
app_offset = spec_fpga_csr_app_offset(spec_fpga);
if (!app_offset) {
dev_warn(&spec_fpga->dev, "Application not found\n");
return 0;
}
res[0].start = pci_resource_start(pcidev, 0) + app_offset;
res[0].end = pci_resource_end(pcidev, 0);
if (spec_fpga->vic_pdev)
vic_domain = irq_find_host((void *)&spec_fpga->vic_pdev->dev);
else
vic_domain = NULL;
if (vic_domain) {
int i, hwirq;
for (i = 1, hwirq = SPEC_FPGA_APP_IRQ_BASE;
i < SPEC_FPGA_APP_RES_N;
++i, ++hwirq) {
res[i].name = "app-irq",
res[i].flags = IORESOURCE_IRQ,
res[i].start = irq_find_mapping(vic_domain, hwirq);
res[i].end = res[1].start;
}
} else {
res_n = 1;
}
err = spec_fpga_app_id_build(spec_fpga, app_offset,
app_name, SPEC_FPGA_APP_NAME_MAX);
if (err)
return err;
spec_fpga_app_restart(spec_fpga);
pdev = platform_device_register_resndata(&spec_fpga->dev,
app_name, PLATFORM_DEVID_AUTO,
res, res_n,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
spec_fpga->app_pdev = pdev;
return 0;
}
static void spec_fpga_app_exit(struct spec_fpga *spec_fpga)
{
if (spec_fpga->app_pdev) {
platform_device_unregister(spec_fpga->app_pdev);
spec_fpga->app_pdev = NULL;
}
}
static bool spec_fpga_is_valid(struct spec_gn412x *spec_gn412x,
struct spec_meta_id *meta)
{
if ((meta->bom & SPEC_META_BOM_END_MASK) != SPEC_META_BOM_LE) {
dev_err(&spec_gn412x->pdev->dev,
"Expected Little Endian devices BOM: 0x%x\n",
meta->bom);
return false;
}
if ((meta->bom & SPEC_META_BOM_VER_MASK) != 0) {
dev_err(&spec_gn412x->pdev->dev,
"Unknow Metadata specification version BOM: 0x%x\n",
meta->bom);
return false;
}
if (meta->vendor != SPEC_META_VENDOR_ID ||
meta->device != SPEC_META_DEVICE_ID) {
dev_err(&spec_gn412x->pdev->dev,
"Unknow vendor/device ID: %08x:%08x\n",
meta->vendor, meta->device);
return false;
}
if ((meta->version & SPEC_META_VERSION_MASK) != SPEC_META_VERSION_1_4) {
dev_err(&spec_gn412x->pdev->dev,
"Unknow version: %08x\n", meta->version);
return false;
}
return true;
}
static void spec_release(struct device *dev)
{
}
static int spec_uevent(struct device *dev, struct kobj_uevent_env *env)
{
return 0;
}
static const struct attribute_group *spec_groups[] = {
&spec_fpga_therm_group,
&spec_fpga_csr_group,
NULL
};
static const struct device_type spec_fpga_type = {
.name = "spec",
.release = spec_release,
.uevent = spec_uevent,
.groups = spec_groups,
};
/**
* Initialize carrier devices on FPGA
*/
int spec_fpga_init(struct spec_gn412x *spec_gn412x)
{
struct spec_fpga *spec_fpga;
struct resource *r0 = &spec_gn412x->pdev->resource[0];
int err;
spec_fpga = kzalloc(sizeof(*spec_fpga), GFP_KERNEL);
if (!spec_fpga)
return -ENOMEM;
spec_gn412x->spec_fpga = spec_fpga;
spec_fpga->fpga = ioremap(r0->start, resource_size(r0));
if (!spec_fpga->fpga) {
err = -ENOMEM;
goto err_map;
}
spec_fpga->meta = spec_fpga->fpga + SPEC_META_BASE;
if (!spec_fpga_is_valid(spec_gn412x, spec_fpga->meta)) {
err = -EINVAL;
goto err_valid;
}
spec_fpga->dev.parent = &spec_gn412x->pdev->dev;
spec_fpga->dev.driver = spec_gn412x->pdev->dev.driver;
spec_fpga->dev.type = &spec_fpga_type;
err = dev_set_name(&spec_fpga->dev, "spec-%s",
dev_name(&spec_gn412x->pdev->dev));
if (err)
goto err_name;
err = device_register(&spec_fpga->dev);
if (err) {
dev_err(&spec_gn412x->pdev->dev, "Failed to register '%s'\n",
dev_name(&spec_gn412x->pdev->dev));
goto err_dev;
}
spec_fpga_dbg_init(spec_fpga);
err = spec_fpga_vic_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize VIC %d\n", err);
goto err_vic;
}
err = spec_fpga_dma_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize DMA %d\n", err);
goto err_dma;
}
err = spec_fpga_devices_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize Devices %d\n", err);
goto err_devs;
}
err = spec_fmc_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize FMC %d\n", err);
goto err_fmc;
}
err = spec_fpga_app_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize APP %d\n", err);
goto err_app;
}
return 0;
err_app:
spec_fmc_exit(spec_fpga);
err_fmc:
spec_fpga_devices_exit(spec_fpga);
err_devs:
spec_fpga_dma_exit(spec_fpga);
err_dma:
spec_fpga_vic_exit(spec_fpga);
err_vic:
return err;
err_dev:
err_name:
err_valid:
iounmap(spec_fpga->fpga);
err_map:
kfree(spec_fpga);
spec_gn412x->spec_fpga = NULL;
return err;
}
int spec_fpga_exit(struct spec_gn412x *spec_gn412x)
{
struct spec_fpga *spec_fpga = spec_gn412x->spec_fpga;
if (!spec_fpga)
return 0;
spec_fpga_app_exit(spec_fpga);
spec_fmc_exit(spec_fpga);
spec_fpga_devices_exit(spec_fpga);
spec_fpga_dma_exit(spec_fpga);
spec_fpga_vic_exit(spec_fpga);
spec_fpga_dbg_exit(spec_fpga);
device_unregister(&spec_fpga->dev);
iounmap(spec_fpga->fpga);
kfree(spec_fpga);
spec_gn412x->spec_fpga = NULL;
return 0;
}
software/kernel/spec-core.c 0 → 100644
View file @ 204ff681
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*
* Driver for SPEC (Simple PCI FMC carrier) board.
*/
#include <linux/device.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/pci.h>
#include <linux/firmware.h>
#include <linux/moduleparam.h>
#include <linux/mfd/core.h>
#include <linux/gpio/consumer.h>
#include "platform_data/gn412x-gpio.h"
#include "spec.h"
#include "spec-compat.h"
static char *spec_fw_name_45t = "spec-golden-45T.bin";
static char *spec_fw_name_100t = "spec-golden-100T.bin";
static char *spec_fw_name_150t = "spec-golden-150T.bin";
char *spec_fw_name = "";
module_param_named(fw_name, spec_fw_name, charp, 0444);
static int spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name);
/* Debugging */
static int spec_irq_dbg_info(struct seq_file *s, void *offset)
{
struct spec_gn412x *spec_gn412x = s->private;
seq_printf(s, "'%s':\n", dev_name(&spec_gn412x->pdev->dev));
seq_printf(s, " redirect: %d\n",
to_pci_dev(&spec_gn412x->pdev->dev)->irq);
seq_puts(s, " irq-mapping:\n");
seq_puts(s, " - hardware: 8\n");
seq_printf(s, " linux: %d\n",
gpiod_to_irq(spec_gn412x->gpiod[GN4124_GPIO_IRQ1]));
seq_puts(s, " - hardware: 9\n");
seq_printf(s, " linux: %d\n",
gpiod_to_irq(spec_gn412x->gpiod[GN4124_GPIO_IRQ0]));
return 0;
}
static int spec_irq_dbg_info_open(struct inode *inode, struct file *file)
{
struct spec_gn412x *spec = inode->i_private;
return single_open(file, spec_irq_dbg_info, spec);
}
static const struct file_operations spec_irq_dbg_info_ops = {
.owner = THIS_MODULE,
.open = spec_irq_dbg_info_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static ssize_t spec_dbg_fw_write(struct file *file,
const char __user *buf,
size_t count, loff_t *ppos)
{
struct spec_gn412x *spec_gn412x = file->private_data;
int err;
if (!buf || !count) {
dev_err(&spec_gn412x->pdev->dev, "Invalid input\n");
return -EINVAL;
}
err = spec_fw_load(spec_gn412x, buf);
if (err)
return err;
return count;
}
static int spec_dbg_fw_open(struct inode *inode, struct file *file)
{
file->private_data = inode->i_private;
return 0;
}
static const struct file_operations spec_dbg_fw_ops = {
.owner = THIS_MODULE,
.open = spec_dbg_fw_open,
.write = spec_dbg_fw_write,
};
static int spec_dbg_meta(struct seq_file *s, void *offset)
{
struct spec_gn412x *spec_gn412x = s->private;
struct resource *r0 = &spec_gn412x->pdev->resource[0];
struct spec_meta_id __iomem *meta;
meta = ioremap(r0->start + SPEC_META_BASE, sizeof(*meta));
if (!meta) {
dev_warn(&spec_gn412x->pdev->dev, "%s: Mapping failed\n",
__func__);
return -ENOMEM;
}
seq_printf(s, "'%s':\n", dev_name(&spec_gn412x->pdev->dev));
seq_puts(s, "Metadata:\n");
seq_printf(s, " - Vendor: 0x%08x\n", meta->vendor);
seq_printf(s, " - Device: 0x%08x\n", meta->device);
seq_printf(s, " - Version: 0x%08x\n", meta->version);
seq_printf(s, " - BOM: 0x%08x\n", meta->bom);
seq_printf(s, " - SourceID: 0x%08x%08x%08x%08x\n",
meta->src[0],
meta->src[1],
meta->src[2],
meta->src[3]);
seq_printf(s, " - CapabilityMask: 0x%08x\n", meta->cap);
seq_printf(s, " - VendorUUID: 0x%08x%08x%08x%08x\n",
meta->uuid[0],
meta->uuid[1],
meta->uuid[2],
meta->uuid[3]);
iounmap(meta);
return 0;
}
static int spec_dbg_meta_open(struct inode *inode, struct file *file)
{
struct spec_gn412x *spec = inode->i_private;
return single_open(file, spec_dbg_meta, spec);
}
static const struct file_operations spec_dbg_meta_ops = {
.owner = THIS_MODULE,
.open = spec_dbg_meta_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
/**
* It initializes the debugfs interface
* @spec: SPEC device instance
*
* Return: 0 on success, otherwise a negative error number
*/
static int spec_dbg_init(struct spec_gn412x *spec_gn412x)
{
struct device *dev = &spec_gn412x->pdev->dev;
spec_gn412x->dbg_dir = debugfs_create_dir(dev_name(dev),
NULL);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_dir)) {
dev_err(dev, "Cannot create debugfs directory (%ld)\n",
PTR_ERR(spec_gn412x->dbg_dir));
return PTR_ERR(spec_gn412x->dbg_dir);
}
spec_gn412x->dbg_info = debugfs_create_file(SPEC_DBG_INFO_NAME, 0444,
spec_gn412x->dbg_dir,
spec_gn412x,
&spec_irq_dbg_info_ops);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_info)) {
dev_err(dev, "Cannot create debugfs file \"%s\" (%ld)\n",
SPEC_DBG_INFO_NAME, PTR_ERR(spec_gn412x->dbg_info));
return PTR_ERR(spec_gn412x->dbg_info);
}
spec_gn412x->dbg_fw = debugfs_create_file(SPEC_DBG_FW_NAME, 0200,
spec_gn412x->dbg_dir,
spec_gn412x,
&spec_dbg_fw_ops);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_fw)) {
dev_err(dev, "Cannot create debugfs file \"%s\" (%ld)\n",
SPEC_DBG_FW_NAME, PTR_ERR(spec_gn412x->dbg_fw));
return PTR_ERR(spec_gn412x->dbg_fw);
}
spec_gn412x->dbg_meta = debugfs_create_file(SPEC_DBG_META_NAME, 0200,
spec_gn412x->dbg_dir,
spec_gn412x,
&spec_dbg_meta_ops);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_meta)) {
dev_err(dev, "Cannot create debugfs file \"%s\" (%ld)\n",
SPEC_DBG_META_NAME, PTR_ERR(spec_gn412x->dbg_meta));
return PTR_ERR(spec_gn412x->dbg_meta);
}
return 0;
}
/**
* It removes the debugfs interface
* @spec: SPEC device instance
*/
static void spec_dbg_exit(struct spec_gn412x *spec_gn412x)
{
debugfs_remove_recursive(spec_gn412x->dbg_dir);
}
/* SPEC GPIO configuration */
static void spec_gpio_fpga_select_set(struct spec_gn412x *spec_gn412x,
enum spec_fpga_select sel)
{
switch (sel) {
case SPEC_FPGA_SELECT_FPGA_FLASH:
case SPEC_FPGA_SELECT_GN4124_FPGA:
case SPEC_FPGA_SELECT_GN4124_FLASH:
gpiod_set_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0],
!!(sel & 0x1));
gpiod_set_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1],
!!(sel & 0x2));
break;
default:
break;
}
}
static enum spec_fpga_select spec_gpio_fpga_select_get(struct spec_gn412x *spec_gn412x)
{
enum spec_fpga_select sel = 0;
sel |= !!gpiod_get_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1]) << 1;
sel |= !!gpiod_get_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0]) << 0;
return sel;
}
static const struct gpiod_lookup_table spec_gpiod_table = {
.table = {
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_BOOTSEL0,
"bootsel", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_BOOTSEL1,
"bootsel", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SPRI_DIN,
"spi", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SPRI_FLASH_CS,
"spi", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_IRQ0,
"irq", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_IRQ1,
"irq", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SCL,
"i2c", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SDA,
"i2c", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
{},
}
};
static inline size_t spec_gpiod_table_size(void)
{
return sizeof(struct gpiod_lookup_table) +
(sizeof(struct gpiod_lookup) * 9);
}
static int spec_gpio_init_table(struct spec_gn412x *spec_gn412x)
{
struct gpiod_lookup_table *lookup;
int err = 0;
lookup = kzalloc(spec_gpiod_table_size(), GFP_KERNEL);
if (!lookup)
return -ENOMEM;
memcpy(lookup, &spec_gpiod_table, spec_gpiod_table_size());
lookup->dev_id = kstrdup(dev_name(&spec_gn412x->pdev->dev), GFP_KERNEL);
if (!lookup->dev_id)
goto err_dup;
spec_gn412x->gpiod_table = lookup;
err = compat_gpiod_add_lookup_table(spec_gn412x->gpiod_table);
if (err)
goto err_lookup;
return 0;
err_lookup:
kfree(lookup->dev_id);
err_dup:
kfree(lookup);
return err;
}
static void spec_gpio_exit_table(struct spec_gn412x *spec_gn412x)
{
struct gpiod_lookup_table *lookup = spec_gn412x->gpiod_table;
gpiod_remove_lookup_table(lookup);
kfree(lookup->dev_id);
kfree(lookup);
spec_gn412x->gpiod_table = NULL;
}
/**
* Configure bootsel GPIOs
*
* Note: Because of a BUG in RedHat kernel 3.10 we re-set direction
*/
static int spec_gpio_init_bootsel(struct spec_gn412x *spec_gn412x)
{
struct gpio_desc *gpiod;
int err;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "bootsel", 0,
GPIOD_OUT_HIGH);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel0;
}
err = gpiod_direction_output(gpiod, 1);
if (err) {
gpiod_put(gpiod);
goto err_out0;
}
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0] = gpiod;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "bootsel", 1,
GPIOD_OUT_HIGH);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel1;
}
err = gpiod_direction_output(gpiod, 1);
if (err) {
gpiod_put(gpiod);
goto err_out1;
}
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1] = gpiod;
return 0;
err_out1:
err_sel1:
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0]);
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0] = NULL;
err_out0:
err_sel0:
return err;
}
static void spec_gpio_exit_bootsel(struct spec_gn412x *spec_gn412x)
{
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1]);
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1] = NULL;
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0]);
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0] = NULL;
}
/**
* Configure IRQ GPIOs
*
* Note: Because of a BUG in RedHat kernel 3.10 we re-set direction
*/
static int spec_gpio_init_irq(struct spec_gn412x *spec_gn412x)
{
struct gpio_desc *gpiod;
int err;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "irq", 0, GPIOD_IN);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel0;
}
err = gpiod_direction_input(gpiod);
if (err) {
gpiod_put(gpiod);
goto err_out0;
}
spec_gn412x->gpiod[GN4124_GPIO_IRQ0] = gpiod;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "irq", 1, GPIOD_IN);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel1;
}
err = gpiod_direction_input(gpiod);
if (err) {
gpiod_put(gpiod);
goto err_out1;
}
spec_gn412x->gpiod[GN4124_GPIO_IRQ1] = gpiod;
return 0;
err_out1:
err_sel1:
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_IRQ0]);
spec_gn412x->gpiod[GN4124_GPIO_IRQ0] = NULL;
err_out0:
err_sel0:
return err;
}
static void spec_gpio_exit_irq(struct spec_gn412x *spec_gn412x)
{
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_IRQ1]);
spec_gn412x->gpiod[GN4124_GPIO_IRQ1] = NULL;
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_IRQ0]);
spec_gn412x->gpiod[GN4124_GPIO_IRQ0] = NULL;
}
static int spec_gpio_init(struct spec_gn412x *spec_gn412x)
{
int err;
err = spec_gpio_init_table(spec_gn412x);
if (err)
return err;
err = spec_gpio_init_bootsel(spec_gn412x);
if (err)
goto err_bootsel;
err = spec_gpio_init_irq(spec_gn412x);
if (err)
goto err_irq;
return 0;
err_irq:
spec_gpio_exit_bootsel(spec_gn412x);
err_bootsel:
spec_gpio_exit_table(spec_gn412x);
return err;
}
static void spec_gpio_exit(struct spec_gn412x *spec_gn412x)
{
spec_gpio_exit_irq(spec_gn412x);
spec_gpio_exit_bootsel(spec_gn412x);
spec_gpio_exit_table(spec_gn412x);
}
/* SPEC sub-devices */
static struct gn412x_platform_data gn412x_gpio_pdata = {
.int_cfg = 0,
};
static struct resource gn412x_gpio_res[] = {
{
.name = "gn412x-gpio-mem",
.flags = IORESOURCE_MEM,
.start = 0,
.end = 0x1000 - 1,
}, {
.name = "gn412x-gpio-irq",
.flags = IORESOURCE_IRQ,
.start = 0,
.end = 0,
}
};
static struct resource gn412x_fcl_res[] = {
{
.name = "gn412x-fcl-mem",
.flags = IORESOURCE_MEM,
.start = 0,
.end = 0x1000 - 1,
}, {
.name = "gn412x-fcl-irq",
.flags = IORESOURCE_IRQ,
.start = 0,
.end = 0,
}
};
enum spec_mfd_enum {
SPEC_MFD_GN412X_GPIO = 0,
SPEC_MFD_GN412X_FCL,
};
static const struct mfd_cell spec_mfd_devs[] = {
[SPEC_MFD_GN412X_GPIO] = {
.name = "gn412x-gpio",
.platform_data = &gn412x_gpio_pdata,
.pdata_size = sizeof(gn412x_gpio_pdata),
.num_resources = ARRAY_SIZE(gn412x_gpio_res),
.resources = gn412x_gpio_res,
},
[SPEC_MFD_GN412X_FCL] = {
.name = "gn412x-fcl",
.platform_data = NULL,
.pdata_size = 0,
.num_resources = ARRAY_SIZE(gn412x_fcl_res),
.resources = gn412x_fcl_res,
},
};
/**
* Return the SPEC defult FPGA firmware name based on PCI ID
* @spec: SPEC device
*
* Return: FPGA firmware name
*/
static const char *spec_fw_name_init_get(struct spec_gn412x *spec_gn412x)
{
if (strlen(spec_fw_name) > 0)
return spec_fw_name;
switch (spec_gn412x->pdev->device) {
case PCI_DEVICE_ID_SPEC_45T:
return spec_fw_name_45t;
case PCI_DEVICE_ID_SPEC_100T:
return spec_fw_name_100t;
case PCI_DEVICE_ID_SPEC_150T:
return spec_fw_name_150t;
default:
return NULL;
}
}
/**
* Load FPGA code
* @spec: SPEC device
* @name: FPGA bitstream file name
*
* Return: 0 on success, otherwise a negative error number
*/
static int spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name)
{
enum spec_fpga_select sel;
int err;
dev_dbg(&spec_gn412x->pdev->dev, "Writing firmware '%s'\n", name);
err = spec_fpga_exit(spec_gn412x);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Cannot remove FPGA device instances. Try to remove them manually and to reload this device instance\n");
return err;
}
mutex_lock(&spec_gn412x->mtx);
sel = spec_gpio_fpga_select_get(spec_gn412x);
spec_gpio_fpga_select_set(spec_gn412x, SPEC_FPGA_SELECT_GN4124_FPGA);
err = compat_spec_fw_load(spec_gn412x, name);
if (err)
goto out;
err = spec_fpga_init(spec_gn412x);
if (err)
dev_warn(&spec_gn412x->pdev->dev,
"FPGA incorrectly programmed %d\n", err);
out:
spec_gpio_fpga_select_set(spec_gn412x, sel);
mutex_unlock(&spec_gn412x->mtx);
return err;
}
static ssize_t bootselect_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
enum spec_fpga_select sel;
if (strncmp("fpga-flash", buf, 8) == 0) {
sel = SPEC_FPGA_SELECT_FPGA_FLASH;
} else if (strncmp("gn4124-fpga", buf, 8) == 0) {
sel = SPEC_FPGA_SELECT_GN4124_FPGA;
} else if (strncmp("gn4124-flash", buf, 8) == 0) {
sel = SPEC_FPGA_SELECT_GN4124_FLASH;
} else {
dev_err(dev, "Unknown bootselect option '%s'\n",
buf);
return -EINVAL;
}
mutex_lock(&spec_gn412x->mtx);
spec_gpio_fpga_select_set(spec_gn412x, sel);
mutex_unlock(&spec_gn412x->mtx);
return count;
}
static ssize_t bootselect_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
enum spec_fpga_select sel;
sel = spec_gpio_fpga_select_get(spec_gn412x);
switch (sel) {
case SPEC_FPGA_SELECT_FPGA_FLASH:
return snprintf(buf, PAGE_SIZE, "fpga-flash\n");
case SPEC_FPGA_SELECT_GN4124_FPGA:
return snprintf(buf, PAGE_SIZE, "gn4124-fpga\n");
case SPEC_FPGA_SELECT_GN4124_FLASH:
return snprintf(buf, PAGE_SIZE, "gn4124-flash\n");
default:
dev_err(dev, "Unknown bootselect option '%x'\n",
sel);
return -EINVAL;
}
}
static DEVICE_ATTR(bootselect, 0644, bootselect_show, bootselect_store);
/**
* Load golden bitstream on FGPA
*/
static ssize_t load_golden_fpga_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
int err;
err = spec_fw_load(spec_gn412x, spec_fw_name_init_get(spec_gn412x));
return err < 0 ? err : count;
}
static DEVICE_ATTR_WO(load_golden_fpga);
static struct attribute *gn412x_fpga_attrs[] = {
&dev_attr_load_golden_fpga.attr,
&dev_attr_bootselect.attr,
NULL,
};
static const struct attribute_group gn412x_fpga_group = {
.name = "fpga-options",
.attrs = gn412x_fpga_attrs,
};
static int spec_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct spec_gn412x *spec_gn412x;
int err = 0;
spec_gn412x = kzalloc(sizeof(*spec_gn412x), GFP_KERNEL);
if (!spec_gn412x)
return -ENOMEM;
mutex_init(&spec_gn412x->mtx);
pci_set_drvdata(pdev, spec_gn412x);
spec_gn412x->pdev = pdev;
err = pci_enable_device(pdev);
if (err) {
dev_err(&pdev->dev, "Failed to enable PCI device (%d)\n",
err);
goto err_enable;
}
pci_set_master(pdev);
err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
spec_mfd_devs,
ARRAY_SIZE(spec_mfd_devs),
&pdev->resource[4], pdev->irq, NULL);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to add MFD devices (%d)\n",
err);
goto err_mfd;
}
err = spec_gpio_init(spec_gn412x);
if (err) {
dev_err(&pdev->dev, "Failed to get GPIOs (%d)\n", err);
goto err_sgpio;
}
err = sysfs_create_group(&pdev->dev.kobj, &gn412x_fpga_group);
if (err)
goto err_sysfs;
spec_dbg_init(spec_gn412x);
mutex_lock(&spec_gn412x->mtx);
err = spec_fpga_init(spec_gn412x);
if (err)
dev_warn(&pdev->dev,
"FPGA incorrectly programmed or empty (%d)\n", err);
mutex_unlock(&spec_gn412x->mtx);
return 0;
err_sysfs:
spec_gpio_exit(spec_gn412x);
err_sgpio:
mfd_remove_devices(&pdev->dev);
err_mfd:
pci_disable_device(pdev);
err_enable:
kfree(spec_gn412x);
return err;
}
static void spec_remove(struct pci_dev *pdev)
{
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
spec_fpga_exit(spec_gn412x);
spec_dbg_exit(spec_gn412x);
sysfs_remove_group(&pdev->dev.kobj, &gn412x_fpga_group);
spec_gpio_exit(spec_gn412x);
mfd_remove_devices(&pdev->dev);
pci_disable_device(pdev);
kfree(spec_gn412x);
}
static const struct pci_device_id spec_pci_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_45T)},
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_100T)},
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_150T)},
{0,},
};
static struct pci_driver spec_driver = {
.driver = {
.owner = THIS_MODULE,
},
.name = "spec-fmc-carrier",
.probe = spec_probe,
.remove = spec_remove,
.id_table = spec_pci_tbl,
};
module_pci_driver(spec_driver);
MODULE_AUTHOR("Federico Vaga <federico.vaga@cern.ch>");
MODULE_LICENSE("GPL v2");
MODULE_VERSION(VERSION);
MODULE_DESCRIPTION("Driver for the 'Simple PCIe FMC Carrier' a.k.a. SPEC");
MODULE_DEVICE_TABLE(pci, spec_pci_tbl);
MODULE_SOFTDEP("pre: gn412x_gpio gn412x_fcl htvic spec_gn412x_dma i2c_mux i2c_ohwr spi-ocores");
ADDITIONAL_VERSIONS;
software/kernel/spec-gn412x-dma.c 0 → 100644
View file @ 204ff681
/**
* Copyright (C) 2017 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@vaga.pv.it>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/stddef.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/dmapool.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/debugfs.h>
#include <linux/dma-mapping.h>
/* Kernel functions not exported */
#if 0
/*
* Take it from the sources, like if this driver was part
* of that directory
*/
#include <../drivers/dma/dmaengine.h>
#else
/**
* dma_cookie_complete - complete a descriptor
* @tx: descriptor to complete
*
* Mark this descriptor complete by updating the channels completed
* cookie marker. Zero the descriptors cookie to prevent accidental
* repeated completions.
*
* Note: caller is expected to hold a lock to prevent concurrency.
*/
static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
{
BUG_ON(tx->cookie < DMA_MIN_COOKIE);
tx->chan->completed_cookie = tx->cookie;
tx->cookie = 0;
}
/**
* dma_cookie_init - initialize the cookies for a DMA channel
* @chan: dma channel to initialize
*/
static inline void dma_cookie_init(struct dma_chan *chan)
{
chan->cookie = DMA_MIN_COOKIE;
chan->completed_cookie = DMA_MIN_COOKIE;
}
/**
* dma_cookie_assign - assign a DMA engine cookie to the descriptor
* @tx: descriptor needing cookie
*
* Assign a unique non-zero per-channel cookie to the descriptor.
* Note: caller is expected to hold a lock to prevent concurrency.
*/
static inline dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx)
{
struct dma_chan *chan = tx->chan;
dma_cookie_t cookie;
cookie = chan->cookie + 1;
if (cookie < DMA_MIN_COOKIE)
cookie = DMA_MIN_COOKIE;
tx->cookie = chan->cookie = cookie;
return cookie;
}
/**
* dma_cookie_status - report cookie status
* @chan: dma channel
* @cookie: cookie we are interested in
* @state: dma_tx_state structure to return last/used cookies
*
* Report the status of the cookie, filling in the state structure if
* non-NULL. No locking is required.
*/
static inline enum dma_status dma_cookie_status(struct dma_chan *chan,
dma_cookie_t cookie, struct dma_tx_state *state)
{
dma_cookie_t used, complete;
used = chan->cookie;
complete = chan->completed_cookie;
if (state) {
state->last = complete;
state->used = used;
state->residue = 0;
}
return dma_async_is_complete(cookie, complete, used);
}
#endif
enum gn412x_dma_regs {
GN412X_DMA_CTRL = 0x00,
GN412X_DMA_STAT = 0x04,
GN412X_DMA_ADDR_MEM = 0x08,
GN412X_DMA_ADDR_L = 0x0C,
GN412X_DMA_ADDR_H = 0x10,
GN412X_DMA_LEN = 0x14,
GN412X_DMA_NEXT_L = 0x18,
GN412X_DMA_NEXT_H = 0x1C,
GN412X_DMA_ATTR = 0x20,
GN412X_DMA_CUR_ADDR_MEM = 0x24,
GN412X_DMA_CUR_ADDR_L = 0x28,
GN412X_DMA_CUR_ADDR_H = 0x2C,
GN412X_DMA_CUR_LEN = 0x30,
};
enum gn412x_dma_regs_ctrl {
GN412X_DMA_CTRL_START = BIT(0),
GN412X_DMA_CTRL_ABORT = BIT(1),
GN412X_DMA_CTRL_SWAPPING = 0xC,
};
enum gn412x_dma_ctrl_swapping {
GN412X_DMA_CTRL_SWAPPING_NONE = 0,
GN412X_DMA_CTRL_SWAPPING_16,
GN412X_DMA_CTRL_SWAPPING_16_WORD,
GN412X_DMA_CTRL_SWAPPING_32,
};
#define GN412X_DMA_ATTR_DIR_MEM_TO_DEV (1 << 0)
#define GN412X_DMA_ATTR_CHAIN (1 << 1)
struct gn412x_dma_tx;
/**
* List of device identifiers
*/
enum gn412x_dma_id_enum {
GN412X_DMA_GN4124_IPCORE = 0,
};
enum gn412x_dma_state {
GN412X_DMA_STAT_IDLE = 0,
GN412X_DMA_STAT_BUSY,
GN412X_DMA_STAT_ERROR,
GN412X_DMA_STAT_ABORTED,
};
#define GN412X_DMA_STAT_ACK BIT(2)
/**
* Transfer descriptor an hardware transfer
* @start_addr: pointer where start to retrieve data from device memory
* @dma_addr_l: low 32bit of the dma address on host memory
* @dma_addr_h: high 32bit of the dma address on host memory
* @dma_len: number of bytes to transfer from device to host
* @next_addr_l: low 32bit of the address of the next memory area to use
* @next_addr_h: high 32bit of the address of the next memory area to use
* @attribute: dma information about data transferm. At the moment it is used
* only to provide the "last item" bit, direction is fixed to
* device->host
*
* note: it must be a power of 2 in order to be used also as alignement
* within the DMA pool
*/
struct gn412x_dma_tx_hw {
uint32_t start_addr;
uint32_t dma_addr_l;
uint32_t dma_addr_h;
uint32_t dma_len;
uint32_t next_addr_l;
uint32_t next_addr_h;
uint32_t attribute;
uint32_t reserved; /* alignement */
};
/**
* DMA channel descriptor
* @chan: dmaengine channel
* @pending_list: list of pending transfers
* @tx_curr: current transfer
* @task: tasklet for DMA start
* @lock: protects: pending_list, tx_curr, sconfig
* @sconfig: channel configuration to be used
* @error: number of errors detected
*/
struct gn412x_dma_chan {
struct dma_chan chan;
struct list_head pending_list;
struct gn412x_dma_tx *tx_curr;
struct tasklet_struct task;
spinlock_t lock;
struct dma_slave_config sconfig;
unsigned int error;
};
static inline struct gn412x_dma_chan *to_gn412x_dma_chan(struct dma_chan *_ptr)
{
return container_of(_ptr, struct gn412x_dma_chan, chan);
}
static inline bool gn412x_dma_has_pending_tx(struct gn412x_dma_chan *gn412x_dma_chan)
{
return !list_empty(&gn412x_dma_chan->pending_list);
}
/**
* DMA device descriptor
* @pdev: platform device associated
* @addr: component base address
* @dma: dmaengine device
* @chan: list of DMA channels
* @pool: shared DMA pool for HW descriptors
* @pool_list: list of HW descriptor allocated
*/
struct gn412x_dma_device {
struct platform_device *pdev;
void __iomem *addr;
struct dma_device dma;
struct gn412x_dma_chan chan;
struct dma_pool *pool;
struct list_head *pool_list;
struct dentry *dbg_dir;
#define GN412X_DMA_DBG_REG_NAME "regs"
struct dentry *dbg_reg;
struct debugfs_regset32 dbg_reg32;
};
static inline struct gn412x_dma_device *to_gn412x_dma_device(struct dma_device *_ptr)
{
return container_of(_ptr, struct gn412x_dma_device, dma);
}
/**
* DMA transfer descriptor
* @tx: dmaengine descriptor
* @sgl_hw: scattelist HW descriptors
* @sg_len: number of entries in the scatterlist
* @list: token to indentify this transfer in the pending list
*/
struct gn412x_dma_tx {
struct dma_async_tx_descriptor tx;
struct gn412x_dma_tx_hw **sgl_hw;
unsigned int sg_len;
struct list_head list;
};
static inline struct gn412x_dma_tx *to_gn412x_dma_tx(struct dma_async_tx_descriptor *_ptr)
{
return container_of(_ptr, struct gn412x_dma_tx, tx);
}
#define REG32(_name, _offset) {.name = _name, .offset = _offset}
static const struct debugfs_reg32 gn412x_dma_debugfs_reg32[] = {
REG32("DMACTRLR", GN412X_DMA_CTRL),
REG32("DMASTATR", GN412X_DMA_STAT),
REG32("DMACSTARTR", GN412X_DMA_ADDR_MEM),
REG32("DMAHSTARTLR", GN412X_DMA_ADDR_L),
REG32("DMAHSTARTHR", GN412X_DMA_ADDR_H),
REG32("DMALENR", GN412X_DMA_LEN),
REG32("DMANEXTLR", GN412X_DMA_NEXT_L),
REG32("DMANEXTHR", GN412X_DMA_NEXT_H),
REG32("DMAATTRIBR", GN412X_DMA_ATTR),
REG32("DMACURCSTARTR", GN412X_DMA_CUR_ADDR_MEM),
REG32("DMACURHSTARTLR", GN412X_DMA_CUR_ADDR_L),
REG32("DMACURHSTARTHR", GN412X_DMA_CUR_ADDR_H),
REG32("DMACURLENR", GN412X_DMA_CUR_LEN),
};
/**
* Start DMA transfer
* @gn412x_dma: DMA device
*/
static void gn412x_dma_ctrl_start(struct gn412x_dma_device *gn412x_dma)
{
uint32_t ctrl;
ctrl = ioread32(gn412x_dma->addr + GN412X_DMA_CTRL);
ctrl |= GN412X_DMA_CTRL_START;
iowrite32(ctrl, gn412x_dma->addr + GN412X_DMA_CTRL);
dev_dbg(&gn412x_dma->pdev->dev, "%s: stat: 0x%x\n",
__func__, ioread32(gn412x_dma->addr + GN412X_DMA_STAT));
}
/**
* Abort on going DMA transfer
* @gn412x_dma: DMA device
*/
static void gn412x_dma_ctrl_abort(struct gn412x_dma_device *gn412x_dma)
{
uint32_t ctrl;
ctrl = ioread32(gn412x_dma->addr + GN412X_DMA_CTRL);
ctrl |= GN412X_DMA_CTRL_ABORT;
iowrite32(ctrl, gn412x_dma->addr + GN412X_DMA_CTRL);
}
/**
* Set swapping option
* @gn412x_dma: DMA device
* @swap: swapping option
*/
static void gn412x_dma_ctrl_swapping(struct gn412x_dma_device *gn412x_dma,
enum gn412x_dma_ctrl_swapping swap)
{
uint32_t ctrl = swap;
iowrite32(ctrl, gn412x_dma->addr + GN412X_DMA_CTRL);
}
static enum gn412x_dma_state gn412x_dma_state(struct gn412x_dma_device *gn412x_dma)
{
return ioread32(gn412x_dma->addr + GN412X_DMA_STAT);
}
static bool gn412x_dma_is_busy(struct gn412x_dma_device *gn412x_dma)
{
uint32_t status;
status = ioread32(gn412x_dma->addr + GN412X_DMA_STAT);
return status & GN412X_DMA_STAT_BUSY;
}
static bool gn412x_dma_is_abort(struct gn412x_dma_device *gn412x_dma)
{
uint32_t status;
status = ioread32(gn412x_dma->addr + GN412X_DMA_STAT);
return status & GN412X_DMA_STAT_ABORTED;
}
static void gn412x_dma_irq_ack(struct gn412x_dma_device *gn412x_dma)
{
iowrite32(GN412X_DMA_STAT_ACK, gn412x_dma->addr + GN412X_DMA_STAT);
}
static void gn412x_dma_config(struct gn412x_dma_device *gn412x_dma,
struct gn412x_dma_tx_hw *tx_hw)
{
iowrite32(tx_hw->start_addr, gn412x_dma->addr + GN412X_DMA_ADDR_MEM);
iowrite32(tx_hw->dma_addr_l, gn412x_dma->addr + GN412X_DMA_ADDR_L);
iowrite32(tx_hw->dma_addr_h, gn412x_dma->addr + GN412X_DMA_ADDR_H);
iowrite32(tx_hw->dma_len, gn412x_dma->addr + GN412X_DMA_LEN);
iowrite32(tx_hw->next_addr_l, gn412x_dma->addr + GN412X_DMA_NEXT_L);
iowrite32(tx_hw->next_addr_h, gn412x_dma->addr + GN412X_DMA_NEXT_H);
iowrite32(tx_hw->attribute, gn412x_dma->addr + GN412X_DMA_ATTR);
}
static int gn412x_dma_alloc_chan_resources(struct dma_chan *dchan)
{
struct gn412x_dma_chan *chan = to_gn412x_dma_chan(dchan);
memset(&chan->sconfig, 0, sizeof(struct dma_slave_config));
chan->sconfig.direction = DMA_DEV_TO_MEM;
return 0;
}
static void gn412x_dma_free_chan_resources(struct dma_chan *dchan)
{
}
/**
* Add a descriptor to the pending DMA transfer queue.
* This will not trigger any DMA transfer: here we just collect DMA
* transfer descriptions.
*/
static dma_cookie_t gn412x_dma_tx_submit(struct dma_async_tx_descriptor *tx)
{
struct gn412x_dma_tx *gn412x_dma_tx = to_gn412x_dma_tx(tx);
struct gn412x_dma_chan *chan = to_gn412x_dma_chan(tx->chan);
dma_cookie_t cookie;
unsigned long flags;
dev_dbg(&tx->chan->dev->device, "%s submit %p\n", __func__, tx);
spin_lock_irqsave(&chan->lock, flags);
cookie = dma_cookie_assign(tx);
list_add_tail(&gn412x_dma_tx->list, &chan->pending_list);
spin_unlock_irqrestore(&chan->lock, flags);
return cookie;
}
static void gn412x_dma_prep_fixup(struct gn412x_dma_tx_hw *tx_hw,
dma_addr_t next_addr)
{
if (!tx_hw || !next_addr)
return;
tx_hw->next_addr_l = ((next_addr >> 0) & 0xFFFFFFFF);
tx_hw->next_addr_h = ((next_addr >> 32) & 0xFFFFFFFF);
}
static void gn412x_dma_prep(struct gn412x_dma_tx_hw *tx_hw,
struct scatterlist *sg,
dma_addr_t start_addr)
{
tx_hw->start_addr = start_addr & 0xFFFFFFFF;
tx_hw->dma_addr_l = sg_dma_address(sg);
tx_hw->dma_addr_l &= 0xFFFFFFFF;
tx_hw->dma_addr_h = ((uint64_t)sg_dma_address(sg) >> 32);
tx_hw->dma_addr_h &= 0xFFFFFFFF;
tx_hw->dma_len = sg_dma_len(sg);
tx_hw->next_addr_l = 0x00000000;
tx_hw->next_addr_h = 0x00000000;
tx_hw->attribute = 0x0;
if (!sg_is_last(sg))
tx_hw->attribute = GN412X_DMA_ATTR_CHAIN;
}
static struct dma_async_tx_descriptor *gn412x_dma_prep_slave_sg(
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
enum dma_transfer_direction direction, unsigned long flags,
void *context)
{
struct gn412x_dma_device *gn412x_dma = to_gn412x_dma_device(chan->device);
struct dma_slave_config *sconfig = &to_gn412x_dma_chan(chan)->sconfig;
struct gn412x_dma_tx *gn412x_dma_tx;
struct scatterlist *sg;
dma_addr_t src_addr;
int i;
if (unlikely(direction != DMA_DEV_TO_MEM)) {
dev_err(&chan->dev->device,
"Support only DEV -> MEM transfers\n");
goto err;
}
if (unlikely(sconfig->direction != direction)) {
dev_err(&chan->dev->device,
"Transfer and slave configuration disagree on DMA direction\n");
goto err;
}
if (unlikely(!sgl || !sg_len)) {
dev_err(&chan->dev->device,
"You must provide a DMA scatterlist\n");
goto err;
}
gn412x_dma_tx = kzalloc(sizeof(struct gn412x_dma_tx), GFP_NOWAIT);
if (!gn412x_dma_tx)
goto err;
dma_async_tx_descriptor_init(&gn412x_dma_tx->tx, chan);
gn412x_dma_tx->tx.tx_submit = gn412x_dma_tx_submit;
gn412x_dma_tx->sg_len = sg_len;
/* Configure the hardware for this transfer */
gn412x_dma_tx->sgl_hw = kcalloc(sizeof(struct gn412x_dma_tx_hw *),
gn412x_dma_tx->sg_len,
GFP_KERNEL);
if (!gn412x_dma_tx->sgl_hw)
goto err_alloc_sglhw;
src_addr = sconfig->src_addr;
for_each_sg(sgl, sg, sg_len, i) {
dma_addr_t phys;
if (sg_dma_len(sg) > dma_get_max_seg_size(chan->device->dev)) {
dev_err(&chan->dev->device,
"Maximum transfer size %d, got %d on transfer %d\n",
0x3FFF, sg_dma_len(sg), i);
goto err_alloc_pool;
}
gn412x_dma_tx->sgl_hw[i] = dma_pool_alloc(gn412x_dma->pool,
GFP_DMA,
&phys);
if (!gn412x_dma_tx->sgl_hw[i])
goto err_alloc_pool;
if (i > 0) {
/*
* To build the chained transfer the previous
* descriptor (sgl_hw[i - 1]) must point to
* the physical address of current one (phys)
*/
gn412x_dma_prep_fixup(gn412x_dma_tx->sgl_hw[i - 1],
phys);
} else {
gn412x_dma_tx->tx.phys = phys;
}
gn412x_dma_prep(gn412x_dma_tx->sgl_hw[i], sg, src_addr);
src_addr += sg_dma_len(sg);
}
for_each_sg(sgl, sg, sg_len, i) {
struct gn412x_dma_tx_hw *tx_hw = gn412x_dma_tx->sgl_hw[i];
dev_dbg(&chan->dev->device,
"%s\n"
"\tsegment: %d\n"
"\tstart_addr: 0x%x\n"
"\tdma_addr_l: 0x%x\n"
"\tdma_addr_h: 0x%x\n"
"\tdma_len: 0x%x\n"
"\tnext_addr_l: 0x%x\n"
"\tnext_addr_h: 0x%x\n"
"\tattribute: 0x%x\n",
__func__, i,
tx_hw->start_addr,
tx_hw->dma_addr_l,
tx_hw->dma_addr_h,
tx_hw->dma_len,
tx_hw->next_addr_l,
tx_hw->next_addr_h,
tx_hw->attribute);
}
dev_dbg(&chan->dev->device, "%s prepared %p\n", __func__, &gn412x_dma_tx->tx);
return &gn412x_dma_tx->tx;
err_alloc_pool:
while(--i >= 0)
dma_pool_free(gn412x_dma->pool,
gn412x_dma_tx->sgl_hw[i],
gn412x_dma_tx->tx.phys);
kfree(gn412x_dma_tx->sgl_hw);
err_alloc_sglhw:
kfree(gn412x_dma_tx);
err:
return NULL;
}
static void gn412x_dma_schedule_next(struct gn412x_dma_chan *gn412x_dma_chan)
{
unsigned long flags;
bool pending;
spin_lock_irqsave(&gn412x_dma_chan->lock, flags);
pending = gn412x_dma_has_pending_tx(gn412x_dma_chan);
spin_unlock_irqrestore(&gn412x_dma_chan->lock, flags);
if (pending)
tasklet_schedule(&gn412x_dma_chan->task);
}
static void gn412x_dma_issue_pending(struct dma_chan *chan)
{
gn412x_dma_schedule_next(to_gn412x_dma_chan(chan));
}
static void gn412x_dma_start_task(unsigned long arg)
{
struct gn412x_dma_chan *chan = (struct gn412x_dma_chan *)arg;
struct gn412x_dma_device *gn412x_dma = to_gn412x_dma_device(chan->chan.device);
unsigned long flags;
if (unlikely(gn412x_dma_is_busy(gn412x_dma))) {
dev_err(&gn412x_dma->pdev->dev,
"Failed to start DMA transfer: channel busy\n");
return;
}
spin_lock_irqsave(&chan->lock, flags);
if (gn412x_dma_has_pending_tx(chan)) {
struct gn412x_dma_tx *tx;
tx = list_first_entry(&chan->pending_list,
struct gn412x_dma_tx, list);
list_del(&tx->list);
gn412x_dma_config(gn412x_dma, tx->sgl_hw[0]);
gn412x_dma_ctrl_swapping(gn412x_dma,
GN412X_DMA_CTRL_SWAPPING_NONE);
gn412x_dma_ctrl_start(gn412x_dma);
chan->tx_curr = tx;
}
spin_unlock_irqrestore(&chan->lock, flags);
}
static enum dma_status gn412x_dma_tx_status(struct dma_chan *chan,
dma_cookie_t cookie,
struct dma_tx_state *state)
{
return DMA_ERROR;
}
static int gn412x_dma_slave_config(struct dma_chan *chan,
struct dma_slave_config *sconfig)
{
struct gn412x_dma_chan *gn412x_dma_chan = to_gn412x_dma_chan(chan);
unsigned long flags;
spin_lock_irqsave(&gn412x_dma_chan->lock, flags);
memcpy(&gn412x_dma_chan->sconfig, sconfig,
sizeof(struct dma_slave_config));
spin_unlock_irqrestore(&gn412x_dma_chan->lock, flags);
return 0;
}
static int gn412x_dma_terminate_all(struct dma_chan *chan)
{
struct gn412x_dma_device *gn412x_dma = to_gn412x_dma_device(chan->device);
gn412x_dma_ctrl_abort(gn412x_dma);
/* FIXME remove all pending */
if (!gn412x_dma_is_abort(gn412x_dma)) {
dev_err(&gn412x_dma->pdev->dev,
"Failed to abort DMA transfer\n");
return -EINVAL;
}
return 0;
}
static int gn412x_dma_device_control(struct dma_chan *chan,
enum dma_ctrl_cmd cmd,
unsigned long arg)
{
switch (cmd) {
case DMA_SLAVE_CONFIG:
return gn412x_dma_slave_config(chan,
(struct dma_slave_config *)arg);
case DMA_TERMINATE_ALL:
return gn412x_dma_terminate_all(chan);
case DMA_PAUSE:
break;
case DMA_RESUME:
break;
default:
break;
}
return -ENODEV;
}
static irqreturn_t gn412x_dma_irq_handler(int irq, void *arg)
{
struct gn412x_dma_device *gn412x_dma = arg;
struct gn412x_dma_chan *chan = &gn412x_dma->chan;
struct gn412x_dma_tx *tx;
unsigned long flags;
unsigned int i;
enum gn412x_dma_state state;
/* FIXME check for spurious - need HDL fix */
gn412x_dma_irq_ack(gn412x_dma);
spin_lock_irqsave(&chan->lock, flags);
tx = chan->tx_curr;
chan->tx_curr = NULL;
spin_unlock_irqrestore(&chan->lock, flags);
state = gn412x_dma_state(gn412x_dma);
switch (state) {
case GN412X_DMA_STAT_IDLE:
dma_cookie_complete(&tx->tx);
if (tx->tx.callback)
tx->tx.callback(tx->tx.callback_param);
break;
case GN412X_DMA_STAT_ERROR:
dev_err(&gn412x_dma->pdev->dev,
"DMA transfer failed: error\n");
break;
default:
dev_err(&gn412x_dma->pdev->dev,
"DMA transfer failed: inconsitent state %d\n",
state);
break;
}
/* Clean up memory */
for (i = 0; i < tx->sg_len; ++i)
dma_pool_free(gn412x_dma->pool, tx->sgl_hw[i], tx->tx.phys);
kfree(tx->sgl_hw);
kfree(tx);
gn412x_dma_schedule_next(chan);
return IRQ_HANDLED;
}
static int gn412x_dma_dbg_init(struct gn412x_dma_device *gn412x_dma)
{
struct dentry *dir, *file;
int err;
dir = debugfs_create_dir(dev_name(&gn412x_dma->pdev->dev), NULL);
if (IS_ERR_OR_NULL(dir)) {
err = PTR_ERR(dir);
dev_warn(&gn412x_dma->pdev->dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(&gn412x_dma->pdev->dev), err);
goto err_dir;
}
gn412x_dma->dbg_reg32.regs = gn412x_dma_debugfs_reg32;
gn412x_dma->dbg_reg32.nregs = ARRAY_SIZE(gn412x_dma_debugfs_reg32);
gn412x_dma->dbg_reg32.base = gn412x_dma->addr;
file = debugfs_create_regset32(GN412X_DMA_DBG_REG_NAME, 0200,
dir, &gn412x_dma->dbg_reg32);
if (IS_ERR_OR_NULL(file)) {
err = PTR_ERR(file);
dev_warn(&gn412x_dma->pdev->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
GN412X_DMA_DBG_REG_NAME, err);
goto err_reg32;
}
gn412x_dma->dbg_dir = dir;
gn412x_dma->dbg_reg = file;
return 0;
err_reg32:
debugfs_remove_recursive(dir);
err_dir:
return err;
}
static void gn412x_dma_dbg_exit(struct gn412x_dma_device *gn412x_dma)
{
debugfs_remove_recursive(gn412x_dma->dbg_dir);
}
/**
* Configure DMA Engine configuration
*/
static int gn412x_dma_engine_init(struct gn412x_dma_device *gn412x_dma,
struct device *parent)
{
struct dma_device *dma = &gn412x_dma->dma;
dma->dev = parent;
if (dma_set_mask(dma->dev, DMA_BIT_MASK(64))) {
/* Check if hardware supports 32-bit DMA */
if (dma_set_mask(dma->dev, DMA_BIT_MASK(32))) {
dev_err(dma->dev,
"32-bit DMA addressing not available\n");
return -EINVAL;
}
}
INIT_LIST_HEAD(&dma->channels);
dma_cap_zero(dma->cap_mask);
dma_cap_set(DMA_SLAVE, dma->cap_mask);
dma_cap_set(DMA_PRIVATE, dma->cap_mask);
dma->device_alloc_chan_resources = gn412x_dma_alloc_chan_resources;
dma->device_free_chan_resources = gn412x_dma_free_chan_resources;
dma->device_prep_slave_sg = gn412x_dma_prep_slave_sg;
dma->device_control = gn412x_dma_device_control;
dma->device_tx_status = gn412x_dma_tx_status;
dma->device_issue_pending = gn412x_dma_issue_pending;
gn412x_dma->chan.chan.device = dma;
list_add_tail(&gn412x_dma->chan.chan.device_node, &dma->channels);
INIT_LIST_HEAD(&gn412x_dma->chan.pending_list);
spin_lock_init(&gn412x_dma->chan.lock);
tasklet_init(&gn412x_dma->chan.task, gn412x_dma_start_task,
(unsigned long)&gn412x_dma->chan);
dma_set_max_seg_size(dma->dev, 0x7FFF);
gn412x_dma->pool = dma_pool_create(dev_name(dma->dev), dma->dev,
sizeof(struct gn412x_dma_tx_hw),
sizeof(struct gn412x_dma_tx_hw),
0);
if (!gn412x_dma->pool)
return -ENOMEM;
return 0;
}
/**
* Release DMa engine configuration
*/
static void gn412x_dma_engine_exit(struct gn412x_dma_device *gn412x_dma)
{
dma_pool_destroy(gn412x_dma->pool);
}
/**
* It creates a new instance of the GN4124 DMA engine
* @pdev: platform device
*
* @return: 0 on success otherwise a negative error code
*/
static int gn412x_dma_probe(struct platform_device *pdev)
{
struct gn412x_dma_device *gn412x_dma;
const struct resource *r;
int err;
/* FIXME set DMA mask on pdev? */
gn412x_dma = kzalloc(sizeof(struct gn412x_dma_device), GFP_KERNEL);
if (!gn412x_dma)
return -ENOMEM;
gn412x_dma->pdev = pdev;
platform_set_drvdata(pdev, gn412x_dma);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(&pdev->dev, "Missing memory resource\n");
err = -EINVAL;
goto err_res_mem;
}
gn412x_dma->addr = ioremap(r->start, resource_size(r));
if (!gn412x_dma->addr) {
err = -EADDRNOTAVAIL;
goto err_map;
}
err = request_any_context_irq(platform_get_irq(pdev, 0),
gn412x_dma_irq_handler, 0,
dev_name(&pdev->dev), gn412x_dma);
if (err < 0)
goto err_irq;
/* Get the pci_dev device because it is the one configured for DMA */
err = gn412x_dma_engine_init(gn412x_dma, pdev->dev.parent->parent);
if (err) {
dev_err(&pdev->dev, "Can't allocate DMA pool\n");
goto err_dma_init;
}
err = dma_async_device_register(&gn412x_dma->dma);
if (err)
goto err_reg;
gn412x_dma_dbg_init(gn412x_dma);
return 0;
err_reg:
gn412x_dma_engine_exit(gn412x_dma);
err_dma_init:
free_irq(platform_get_irq(pdev, 0), gn412x_dma);
err_irq:
iounmap(gn412x_dma->addr);
err_map:
err_res_mem:
kfree(gn412x_dma);
return err;
}
/**
* It removes an instance of the GN4124 DMA engine
* @pdev: platform device
*
* @return: 0 on success otherwise a negative error code
*/
static int gn412x_dma_remove(struct platform_device *pdev)
{
struct gn412x_dma_device *gn412x_dma = platform_get_drvdata(pdev);
gn412x_dma_dbg_exit(gn412x_dma);
dmaengine_terminate_all(&gn412x_dma->chan.chan);
dma_async_device_unregister(&gn412x_dma->dma);
gn412x_dma_engine_exit(gn412x_dma);
free_irq(platform_get_irq(pdev, 0), gn412x_dma);
iounmap(gn412x_dma->addr);
kfree(gn412x_dma);
return 0;
}
/**
* List of all the compatible devices
*/
static const struct platform_device_id gn412x_dma_id[] = {
{
.name = "spec-gn412x-dma",
.driver_data = GN412X_DMA_GN4124_IPCORE,
},
{ .name = "" }, /* last */
};
struct platform_driver gn412x_dma_driver = {
.driver = {
.name = KBUILD_MODNAME,
},
.probe = gn412x_dma_probe,
.remove = gn412x_dma_remove,
.id_table = gn412x_dma_id
};
module_platform_driver(gn412x_dma_driver);
MODULE_AUTHOR("Federico Vaga <federico.vaga@cern.ch>");
MODULE_DESCRIPTION("SPEC GN4124 IP-Core DMA engine");
MODULE_LICENSE("GPL");
MODULE_VERSION(VERSION);
MODULE_DEVICE_TABLE(platform, gn412x_dma_id);
software/kernel/spec.h 0 → 100644
View file @ 204ff681
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2010-2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
* Author: Alessandro Rubini <rubini@gnudd.com>
*/
#ifndef __SPEC_H__
#define __SPEC_H__
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/irqdomain.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <linux/fmc.h>
#include "gn412x.h"
#include "spec-core-fpga.h"
#define SPEC_FMC_SLOTS 1
/* On FPGA components */
#define PCI_VENDOR_ID_CERN (0x10DC)
#define PCI_DEVICE_ID_SPEC_45T (0x018D)
#define PCI_DEVICE_ID_SPEC_100T (0x01A2)
#define PCI_DEVICE_ID_SPEC_150T (0x01A3)
#define PCI_VENDOR_ID_GENNUM (0x1A39)
#define PCI_DEVICE_ID_GN4124 (0x0004)
#define GN4124_GPIO_MAX 16
#define GN4124_GPIO_BOOTSEL0 15
#define GN4124_GPIO_BOOTSEL1 14
#define GN4124_GPIO_SPRI_DIN 13
#define GN4124_GPIO_SPRI_FLASH_CS 12
#define GN4124_GPIO_IRQ0 9
#define GN4124_GPIO_IRQ1 8
#define GN4124_GPIO_SCL 5
#define GN4124_GPIO_SDA 4
/**
* @SPEC_FPGA_SELECT_FPGA_FLASH: (default) the FPGA is an SPI master that can
* access the flash (at boot it takes its
* configuration from flash)
* @SPEC_FPGA_SELECT_GN4124_FPGA: the GN4124 can configure the FPGA
* @SPEC_FPGA_SELECT_GN4124_FLASH: the GN4124 is an SPI master that can access
* the flash
*/
enum spec_fpga_select {
SPEC_FPGA_SELECT_FPGA_FLASH = 0x3,
SPEC_FPGA_SELECT_GN4124_FPGA = 0x1,
SPEC_FPGA_SELECT_GN4124_FLASH = 0x0,
};
enum {
/* Metadata */
FPGA_META_VENDOR = 0x00,
FPGA_META_DEVICE = 0x04,
FPGA_META_VERSION = 0x08,
FPGA_META_BOM = 0x0C,
FPGA_META_SRC = 0x10,
FPGA_META_CAP = 0x20,
FPGA_META_UUID = 0x30,
};
enum {
/* Metadata */
SPEC_META_BASE = SPEC_BASE_REGS_METADATA,
SPEC_META_VENDOR = SPEC_META_BASE + FPGA_META_VENDOR,
SPEC_META_DEVICE = SPEC_META_BASE + FPGA_META_DEVICE,
SPEC_META_VERSION = SPEC_META_BASE + FPGA_META_VERSION,
SPEC_META_BOM = SPEC_META_BASE + FPGA_META_BOM,
SPEC_META_SRC = SPEC_META_BASE + FPGA_META_SRC,
SPEC_META_CAP = SPEC_META_BASE + FPGA_META_CAP,
SPEC_META_UUID = SPEC_META_BASE + FPGA_META_UUID,
};
#define SPEC_META_VENDOR_ID PCI_VENDOR_ID_CERN
#define SPEC_META_DEVICE_ID 0x53504543
#define SPEC_META_BOM_LE 0xFFFE0000
#define SPEC_META_BOM_END_MASK 0xFFFF0000
#define SPEC_META_BOM_VER_MASK 0x0000FFFF
#define SPEC_META_VERSION_MASK 0xFFFF0000
#define SPEC_META_VERSION_1_4 0x01040000
/**
* struct spec_meta_id Metadata
*/
struct spec_meta_id {
uint32_t vendor;
uint32_t device;
uint32_t version;
uint32_t bom;
uint32_t src[4];
uint32_t cap;
uint32_t uuid[4];
};
/**
* struct spec_fpga - it contains data to handle the FPGA
*
* @pdev: pointer to the PCI device
* @fpga:
* @meta:
* @vic_pdev:
* @app_pdev:
* @slot_info:
* @dbg_dir_fpga:
* @dbg_csr:
* @dbg_csr_reg:
*/
struct spec_fpga {
struct device dev;
void __iomem *fpga;
struct spec_meta_id __iomem *meta;
struct platform_device *vic_pdev;
struct platform_device *dma_pdev;
struct platform_device *app_pdev;
struct fmc_slot_info slot_info;
struct dentry *dbg_dir_fpga;
#define SPEC_DBG_CSR_NAME "csr_regs"
struct dentry *dbg_csr;
struct debugfs_regset32 dbg_csr_reg;
#define SPEC_DBG_BLD_INFO_NAME "build_info"
struct dentry *dbg_bld_info;
};
/**
* struct spec_gn412x - it contains data to handle the PCB
*
* @pdev: pointer to the PCI device
* @mtx: it protects FPGA device/configuration loading
*/
struct spec_gn412x {
struct pci_dev *pdev;
struct mutex mtx;
struct gpiod_lookup_table *gpiod_table;
struct gpio_desc *gpiod[GN4124_GPIO_MAX];
struct dentry *dbg_dir;
#define SPEC_DBG_INFO_NAME "info"
struct dentry *dbg_info;
#define SPEC_DBG_FW_NAME "fpga_firmware"
struct dentry *dbg_fw;
#define SPEC_DBG_META_NAME "fpga_device_metadata"
struct dentry *dbg_meta;
struct spec_fpga *spec_fpga;
};
static inline struct spec_fpga *to_spec_fpga(struct device *_dev)
{
return container_of(_dev, struct spec_fpga, dev);
}
extern int spec_fpga_init(struct spec_gn412x *spec_gn412x);
extern int spec_fpga_exit(struct spec_gn412x *spec_gn412x);
#endif /* __SPEC_H__ */
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