Commit 204ff681 authored by Federico Vaga's avatar Federico Vaga

Merge branch 'release/v1.4.0'

parents a465c3cc 05eef233
*.o
*.ko
*.mod.c
.*.o.cmd
.*.ko.cmd
*.mod.d
*.o.d
*.tmp
.tmp_versions
modules.order
Module.symvers
\#*
*~
GTAGS
GPATH
GRTAGS
Makefile.specific
\ No newline at end of file
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
# Changelog
## [1.4.0] 2019-09-11
### Added
- [hdl] spec-base IP-core to support SPEC based designs
- [sw] Driver for GN4124 FCL using Linux FPGA manager
- [sw] Driver for GN4124 GPIO using Linux GPIOlib
- [sw] Driver for gn412x-core DMA using Linux DMA engine
- [sw] Support for spec-base IP-core
- [sw] Support for FMC
## [x.x.x] 2012-12-14
### Changed
- HDL: GN412x-CORE upgrade
## [x.x.x] 2012-12-14
### Added
- HDL: golden bitstream
## [0.0.0]
Start the development
This diff is collapsed.
modules = { "local" : [ "hdl/rtl" ] }
if action == "synthesis":
modules["local"].append("hdl/syn/common")
==============================
Simple PCIe FMC Carrier - SPEC
==============================
This git repository contains the HDL code necessary to enable most of
the SPEC features and the correspondent Linux driver.
TOP_DIR ?= $(shell pwd)/../
HDL_DIR ?= $(TOP_DIR)/hdl
DRIVER_NAME := spec-fmc-carrier
VERSION := $(shell git describe --abbrev=0)
DIR_NAME := $(DRIVER_NAME)-$(VERSION)
KEEP_TEMP ?= n
BUILD ?= $(abspath build)
BUILD_DKMS := $(BUILD)/dkms
BUILD_DKMSSOURCE := $(BUILD_DKMS)/source
BUILD_DKMSTREE := $(BUILD_DKMS)/tree
DKMS_OPT := --dkmstree $(BUILD_DKMSTREE) -m $(DRIVER_NAME)/$(VERSION)
all: kernel
CHEBY ?= /usr/bin/cheby
spec-core-fpga.h:
$(CHEBY) --gen-c -i $(HDL_DIR)/rtl/spec_base_regs.cheby > /tmp/$@
kernel: dkms-tar dkms-rpm
dkms-tree:
@mkdir -p $(BUILD_DKMSSOURCE)
@mkdir -p $(BUILD_DKMSTREE)
dkms-src: dkms-tree spec-core-fpga.h
$(eval $@_src := $(shell git ls-tree -r --name-only HEAD $(TOP_DIR) | grep "kernel" | tr '\n' ' '))
$(eval $@_dir := $(BUILD_DKMSSOURCE)/$(DRIVER_NAME)-$(VERSION))
@mkdir -p $($@_dir)/platform_data
@mv /tmp/spec-core-fpga.h $($@_dir)
@cp -a $($@_src) $(TOP_DIR)/distribution/dkms.conf $($@_dir)
@mv $($@_dir)/gn412x-gpio.h $($@_dir)/platform_data
@cp -a $(TOP_DIR)/LICENSES/GPL-2.0.txt $($@_dir)/LICENSE
@sed -r -i -e "s/^VERSION\s=\s.*/VERSION = $(VERSION)/" $($@_dir)/Makefile
@sed -r -i -e "s/@PKGNAME@/$(DRIVER_NAME)/" $($@_dir)/dkms.conf
@sed -r -i -e "s/@PKGVER@/$(VERSION)/" $($@_dir)/dkms.conf
dkms-add: dkms-src
@dkms add $(DKMS_OPT) --sourcetree $(BUILD_DKMSSOURCE)
dkms-tar: dkms-add
@dkms mktarball $(DKMS_OPT) --source-only
dkms-rpm: dkms-add
@dkms mkrpm $(DKMS_OPT) --source-only
clean:
@rm -rf $(BUILD)
.PHONY: dkmstree dkms-add kernel-dkms-tar
PACKAGE_NAME="@PKGNAME@"
PACKAGE_VERSION="@PKGVER@"
CLEAN="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 clean"
MAKE[0]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
MAKE[1]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
MAKE[2]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
MAKE[3]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
BUILT_MODULE_NAME[0]="@PKGNAME@"
BUILT_MODULE_NAME[1]="gn412x-gpio"
BUILT_MODULE_NAME[2]="gn412x-fcl"
BUILT_MODULE_NAME[3]="spec-gn412x-dma"
DEST_MODULE_LOCATION[0]="/updates"
DEST_MODULE_LOCATION[1]="/updates"
DEST_MODULE_LOCATION[2]="/updates"
DEST_MODULE_LOCATION[3]="/updates"
BUILD_DEPENDS[0]="fmc"
BUILD_DEPENDS[1]="fpga_mgr"
BUILD_DEPENDS[2]="i2c-ocores"
AUTOINSTALL="yes"
# Minimal makefile for Sphinx documentation
#
# You can set these variables from the command line.
SPHINXOPTS =
SPHINXBUILD = sphinx-build
SOURCEDIR = .
BUILDDIR = _build
# Put it first so that "make" without argument is like "make help".
help:
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: help Makefile
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
\ No newline at end of file
# -*- coding: utf-8 -*-
#
# Configuration file for the Sphinx documentation builder.
#
# This file does only contain a selection of the most common options. For a
# full list see the documentation:
# http://www.sphinx-doc.org/en/master/config
# -- Path setup --------------------------------------------------------------
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
#
# import os
# import sys
# sys.path.insert(0, os.path.abspath('.'))
# -- Project information -----------------------------------------------------
project = 'SPEC'
copyright = '2019, Federico Vaga <federico.vaga@cern.ch>, Tristan Gingold <tristan.gingold@cern.ch>, Dimitris Lampridis <dimitrios.lampridis@cern.ch>'
author = 'Federico Vaga <federico.vaga@cern.ch>, Tristan Gingold <tristan.gingold@cern.ch>, Dimitris Lampridis <dimitrios.lampridis@cern.ch>'
# The short X.Y version
version = ''
# The full version, including alpha/beta/rc tags
release = 'v1.4'
# -- General configuration ---------------------------------------------------
# If your documentation needs a minimal Sphinx version, state it here.
#
# needs_sphinx = '1.0'
# Add any Sphinx extension module names here, as strings. They can be
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
extensions = [
]
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
# The suffix(es) of source filenames.
# You can specify multiple suffix as a list of string:
#
# source_suffix = ['.rst', '.md']
source_suffix = '.rst'
# The master toctree document.
master_doc = 'index'
# The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages.
#
# This is also used if you do content translation via gettext catalogs.
# Usually you set "language" from the command line for these cases.
language = None
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
# This pattern also affects html_static_path and html_extra_path.
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
# The name of the Pygments (syntax highlighting) style to use.
pygments_style = None
# -- Options for HTML output -------------------------------------------------
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#
html_theme = 'alabaster'
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the
# documentation.
#
# html_theme_options = {}
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
html_static_path = ['_static']
# Custom sidebar templates, must be a dictionary that maps document names
# to template names.
#
# The default sidebars (for documents that don't match any pattern) are
# defined by theme itself. Builtin themes are using these templates by
# default: ``['localtoc.html', 'relations.html', 'sourcelink.html',
# 'searchbox.html']``.
#
# html_sidebars = {}
# -- Options for HTMLHelp output ---------------------------------------------
# Output file base name for HTML help builder.
htmlhelp_basename = 'SPECdoc'
# -- Options for LaTeX output ------------------------------------------------
latex_elements = {
# The paper size ('letterpaper' or 'a4paper').
#
# 'papersize': 'letterpaper',
# The font size ('10pt', '11pt' or '12pt').
#
# 'pointsize': '10pt',
# Additional stuff for the LaTeX preamble.
#
# 'preamble': '',
# Latex figure (float) alignment
#
# 'figure_align': 'htbp',
}
# Grouping the document tree into LaTeX files. List of tuples
# (source start file, target name, title,
# author, documentclass [howto, manual, or own class]).
latex_documents = [
(master_doc, 'SPEC.tex', 'SPEC Documentation',
'Federico Vaga \\textless{}federico.vaga@cern.ch\\textgreater{}, Tristan Gingold \\textless{}tristan.gingold@cern.ch\\textgreater{}, Dimitris Lampridis \\textless{}dimitrios.lampridis@cern.ch\\textgreater{}', 'manual'),
]
# -- Options for manual page output ------------------------------------------
# One entry per manual page. List of tuples
# (source start file, name, description, authors, manual section).
man_pages = [
(master_doc, 'spec', 'SPEC Documentation',
[author], 1)
]
# -- Options for Texinfo output ----------------------------------------------
# Grouping the document tree into Texinfo files. List of tuples
# (source start file, target name, title, author,
# dir menu entry, description, category)
texinfo_documents = [
(master_doc, 'SPEC', 'SPEC Documentation',
author, 'SPEC', 'One line description of project.',
'Miscellaneous'),
]
# -- Options for Epub output -------------------------------------------------
# Bibliographic Dublin Core info.
epub_title = project
# The unique identifier of the text. This can be a ISBN number
# or the project homepage.
#
# epub_identifier = ''
# A unique identification for the text.
#
# epub_uid = ''
# A list of files that should not be packed into the epub file.
epub_exclude_files = ['search.html']
.. _spec_hdl_spec_base:
SPEC Base HDL Component
=======================
The ``SPEC base`` HDL component provides the basic support for the SPEC card
and it strongly recommended for any SPEC based application. The VHDL code for
this component is part of the `SPEC project`_ source code as well as the
necessary Linux drivers.
Interface Rules
---------------
The ``SPEC base`` is an :ref:`FPGA device <device-structure>` that contains
all the necessary logic to use the SPEC carrier's features.
Rule
The ``SPEC base`` design must follow the FPGA design guide lines
Rule
The ``SPEC base`` instance must be present in any SPEC based
design.
Rule
The ``SPEC base`` metadata table must contain the following
constant values
========== ========== ================== ============
Offset Size (bit) Name Default (LE)
0x00000000 32 Vendor ID 0x000010DC
0x00000004 32 Device ID 0x53504543
0x00000008 32 Version <variable>
0x0000000C 32 Byte Order Mark 0xFFFE0000
0x00000010 128 Source ID <variable>
0x00000020 32 Capability Mask <variable>
0x00000030 128 Vendor UUID 0x00000000
========== ========== ================== ============
Observation
The ``SPEC base`` typically is instantiated in a *top level* design
next to an ``Application Device``.
Rule
The ``SPEC base`` must have a 32bit register containing the offset
to the ``Application Device``. If there is no application, then the content
of this register must be ``0x00000000``.
Observation
The ``Application Device`` offset is design specific and it must be
declared in the ``Application Access`` register
Version 1.4
~~~~~~~~~~~
Rule
The ``SPEC base`` metadata table must contain the following
constant values for this version.
========== ========== ================== ============
Offset Size (bit) Name Default (LE)
0x00000000 32 Vendor ID 0x000010DC
0x00000004 32 Device ID 0x53504543
0x00000008 32 Version 0x0104xxxx
0x0000000C 32 Byte Order Mark 0xFFFE0000
0x00000010 128 Source ID <variable>
0x00000020 32 Capability Mask 0x0000000x
0x00000030 128 Vendor UUID 0x00000000
========== ========== ================== ============
Rule
The ``SPEC base`` is made of the following components
=================== ============ ========== =============
Component Start End Cap. Mask Bit
CSR 0x00000040 0x0000005F (Mandatory)
Therm. & ID 0x00000070 0x0000007F 1
Gen-Core I2C Ocore 0x00000080 0x0000009F (Mandatory)
Gen-Core SPI 0x000000A0 0x000000BF 2
DMA for DDR 0x000000C0 0x000000FF 5
Gen-Core VIC 0x00000100 0x000001FF 0
Build info 0x00000200 0x000002FF 4
White-Rabbit 0x00001000 0x00001FFF 3
=================== ============ ========== =============
Observation
The capability mask value ``0x1F`` means that all optional components
are instantiated.
Rule
The ``SPEC base`` must connect the VIC IRQ output to the ``GPIO 8`` on
the GN4124 chip
Observation
The GN4124 ``GPIO 9`` can be used for interrupts by the application.
Rule
The ``SPEC base`` reserves the first 6 interrupt lines of
the internal interrupt controller (``VIC``) for the following purposes:
============== ===================
Interrupt Line Component
0 Gen-Core I2C Ocore
1 Gen-Core SPI
2 Gen-Core Gennum DMA DONE
3 (reserved)
4 (reserved)
5 (reserved)
============== ===================
.. _`SPEC project`: https://ohwr.org/project/spec
================================
Welcome to SPEC's documentation!
================================
The Simple PCIe FMC Carrier (SPEC) is a 4 lane PCIe card that has an
FPGA and can hold one FMC module and one SFP connector.
Its bridge to the PCIe bus is the Gennum GN4124 chip and its purpose
is to create a bridge between the PCIe bus and the FPGA. With the
exception of the M25P32 FLASH memory, all components are connected to
the FPGA. This implies that an FPGA configuration is necessary to
fully use the card.
The `SPEC project`_ is hosted on the `Open HardWare Repository`_
.. toctree::
:maxdepth: 2
:caption: Contents:
hdl-spec-base
sw-driver
Indices and tables
==================
* :ref:`genindex`
* :ref:`modindex`
* :ref:`search`
.. _`Open HardWare Repository`: https://ohwr.org/
.. _`SPEC project`: https://ohwr.org/project/spec
SPEC Driver(s)
==============
There are drivers for the GN4124 chip and there are drivers for the
:ref:`SPEC base<spec_hdl_spec_base>` component. All these drivers are
managed by:
SPEC FMC Carrier
This is the driver that wrap up all the physical components and the
:ref:`SPEC base<spec_hdl_spec_base>` ones. It configures the card so
that all components cooperate correctly.
The driver for the GN4124 chip are always present and distributed as
part of the SPEC driver. They must work no matter what FPGA design has
been loaded on FPGA.
GN4124 GPIO
This driver provides support for the GN4124 GPIOs. It uses the standard
Linux `GPIO interface`_ and it export a dedicated IRQ domain.
Gn4124 FCL
This driver provides support for the GN4124 FCL (FPGA Configuration Loader).
It uses the `FPGA manager interface`_ to program the FPGA at runtime.
If the SPEC based application is using the :ref:`SPEC
base<spec_hdl_spec_base>` component then it can profit from the
following driver. They are not all mandatory, it depends on the
application, and most of them are distributed separately:
SPEC GN412x DMA
This driver provides for DMA transfers to/from the SPEC DDR. It uses
the standard Linux `DMA Engine`_. It is part of the `SPEC project`_
I2C OCORE
This is the driver for the I2C OCORE IP-core. It is used to communicate with
the standard FMC EEPROM available what on FMC modules. The driver is
available in Linux.
SPI OCORE
This is the driver for the SPI OCORE IP-core. It is used to communicate with
the M25P32 FLASH memory where FPGA bitstreams are stored. The driver is
distributed separately.
VIC
The driver for the VIC interrupt controller IP-core. The driver is
distributed separately.
.. _`SPEC project`: https://ohwr.org/project/spec
.. _`GPIO interface`: https://www.kernel.org/doc/html/latest/driver-api/gpio/index.html
.. _`FPGA manager interface`: https://www.kernel.org/doc/html/latest/driver-api/fpga/index.html
.. _`DMA Engine`: https://www.kernel.org/doc/html/latest/driver-api/dmaengine/index.html~
fetchto = "ip_cores"
modules = { "local" : [ "top", "platform" ] }
modules = {"local" : "xilinx"}
files = [ "wr_xilinx_pkg.vhd" ]
modules = {"local" : ["wr_gtp_phy", "chipscope"]}
\ No newline at end of file
files =["chipscope_icon.ngc", "chipscope_ila.ngc" ]
This diff is collapsed.
files = ["gtp_bitslide.vhd",
"gtp_phase_align.vhd",
"gtp_phase_align_virtex6.vhd",
"gtx_reset.vhd",
"whiterabbitgtx_wrapper_gtx.vhd",
# "whiterabbitgtp_wrapper.vhd",
"whiterabbitgtp_wrapper_tile.vhd",
"wr_gtp_phy_spartan6.vhd",
"wr_gtx_phy_virtex6.vhd"];
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - bitslide state machine
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_bitslide.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Module implements a manual bitslide alignment state machine and
-- provides the obtained bitslide value to the MAC.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-- 2011-09-12 0.6 twlostow Virtex6 port
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_bitslide is
generic (
-- set to non-zero value to enable some simulation speedups (reduce delays)
g_simulation : integer;
g_target : string := "spartan6");
port (
gtp_rst_i : in std_logic;
-- GTP
gtp_rx_clk_i : in std_logic;
-- '1' indicates that the GTP has detected a comma in the incoming serial stream
gtp_rx_comma_det_i : in std_logic;
gtp_rx_byte_is_aligned_i : in std_logic;
-- GTP ready flag (PLL locked and RX signal present)
serdes_ready_i : in std_logic;
-- GTP manual bitslip control line
gtp_rx_slide_o : out std_logic;
-- GTP CDR reset, asserted when the link is lost to set the bitslide to a known
-- value
gtp_rx_cdr_rst_o : out std_logic;
-- Current bitslide, in UIs
bitslide_o : out std_logic_vector(4 downto 0);
-- '1' when the bitsliding has been completed and the link is up
synced_o : out std_logic
);
end gtp_bitslide;
architecture behavioral of gtp_bitslide is
function f_eval_sync_detect_threshold
return integer is
begin
if(g_simulation /= 0) then
return 256;
elsif(g_target = "spartan6") then
return 8192;
else
return 16384;
end if;
end f_eval_sync_detect_threshold;
function f_eval_pause_tics return integer is
begin
if(g_target = "spartan6") then
return 31;
else
return 63;
end if;
end f_eval_pause_tics;
constant c_pause_tics : integer := f_eval_pause_tics;
constant c_sync_detect_threshold : integer := f_eval_sync_detect_threshold;
type t_bitslide_fsm_state is (S_SYNC_LOST, S_STABILIZE, S_SLIDE, S_PAUSE, S_GOT_SYNC, S_RESET_CDR);
signal cur_slide : unsigned(4 downto 0);
signal state : t_bitslide_fsm_state;
signal counter : unsigned(15 downto 0);
signal commas_missed : unsigned(1 downto 0);
begin -- behavioral
p_do_slide : process(gtp_rx_clk_i, gtp_rst_i)
begin
if gtp_rst_i = '1' then
state <= S_SYNC_LOST;
gtp_rx_slide_o <= '0';
counter <= (others => '0');
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
elsif rising_edge(gtp_rx_clk_i) then
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
case state is
-- State: synchronization lost. Waits until a comma pattern is detected
when S_SYNC_LOST =>
cur_slide <= (others => '0');
counter <= (others => '0');
gtp_rx_slide_o <= '0';
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
commas_missed <= (others => '0');
if(gtp_rx_comma_det_i = '1') then
state <= S_STABILIZE;
end if;
-- State: stabilize:
when S_STABILIZE =>
if(gtp_rx_comma_det_i = '1') then
counter <= counter + 1;
commas_missed <= (others => '0');
else
commas_missed <= commas_missed + 1;
if(commas_missed(1) = '1') then
state <= S_SYNC_LOST;
end if;