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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
Commits
1aa51431
Commit
1aa51431
authored
Jul 15, 2019
by
Tristan Gingold
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spec template: add buildinfo.
parent
47c8d80d
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4 changed files
with
76 additions
and
5 deletions
+76
-5
spec_template_regs.cheby
hdl/rtl/spec_template_regs.cheby
+9
-4
spec_template_regs.vhd
hdl/rtl/spec_template_regs.vhd
+26
-1
spec_template_wr.vhd
hdl/rtl/spec_template_wr.vhd
+35
-0
Manifest.py
hdl/syn/golden_wr/Manifest.py
+6
-0
No files found.
hdl/rtl/spec_template_regs.cheby
View file @
1aa51431
...
...
@@ -4,10 +4,10 @@ memory-map:
size: 0x2000
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
size: 0x40
interface: sram
name: metadata
description: a ROM containing the carrier metadata
size: 0x40
interface: sram
- block:
name: csr
description: carrier and fmc status and control
...
...
@@ -100,6 +100,11 @@ memory-map:
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: buildinfo
description: a ROM containing build information
size: 0x100
interface: sram
- submap:
name: wrc_regs
address: 0x1000
...
...
hdl/rtl/spec_template_regs.vhd
View file @
1aa51431
...
...
@@ -62,6 +62,11 @@ entity spec_template_regs is
vic_i
:
in
t_wishbone_master_in
;
vic_o
:
out
t_wishbone_master_out
;
-- a ROM containing build information
buildinfo_addr_o
:
out
std_logic_vector
(
7
downto
2
);
buildinfo_data_i
:
in
std_logic_vector
(
31
downto
0
);
buildinfo_data_o
:
out
std_logic_vector
(
31
downto
0
);
-- white-rabbit core registers
wrc_regs_i
:
in
t_wishbone_master_in
;
wrc_regs_o
:
out
t_wishbone_master_out
...
...
@@ -111,6 +116,8 @@ architecture syn of spec_template_regs is
signal
vic_tr
:
std_logic
;
signal
vic_wack
:
std_logic
;
signal
vic_rack
:
std_logic
;
signal
buildinfo_rack
:
std_logic
;
signal
buildinfo_re
:
std_logic
;
signal
wrc_regs_re
:
std_logic
;
signal
wrc_regs_wt
:
std_logic
;
signal
wrc_regs_rt
:
std_logic
;
...
...
@@ -250,6 +257,15 @@ begin
vic_o
.
sel
<=
(
others
=>
'1'
);
vic_o
.
we
<=
vic_wt
;
vic_o
.
dat
<=
wb_dat_i
;
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
buildinfo_rack
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
buildinfo_rack
<=
buildinfo_re
and
not
buildinfo_rack
;
end
if
;
end
process
;
buildinfo_data_o
<=
wb_dat_i
;
buildinfo_addr_o
<=
wb_adr_i
(
7
downto
2
);
-- Assignments for submap wrc_regs
wrc_regs_tr
<=
wrc_regs_wt
or
wrc_regs_rt
;
...
...
@@ -356,6 +372,8 @@ begin
-- Submap vic
vic_wt
<=
(
vic_wt
or
wr_int
)
and
not
vic_wack
;
wr_ack_int
<=
vic_wack
;
when
"0010"
=>
-- Submap buildinfo
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
...
...
@@ -435,6 +453,7 @@ begin
rd_ack1_int
<=
rd_int
;
end
case
;
when
"0001"
=>
when
"0010"
=>
when
others
=>
rd_ack1_int
<=
rd_int
;
end
case
;
...
...
@@ -446,7 +465,7 @@ begin
end
process
;
-- Process for read requests.
process
(
wb_adr_i
,
reg_rdat_int
,
rd_ack1_int
,
rd_int
,
rd_int
,
metadata_data_i
,
metadata_rack
,
rd_int
,
therm_id_i
.
dat
,
therm_id_rack
,
therm_id_rt
,
rd_int
,
fmc_i2c_i
.
dat
,
fmc_i2c_rack
,
fmc_i2c_rt
,
rd_int
,
flash_spi_i
.
dat
,
flash_spi_rack
,
flash_spi_rt
,
rd_int
,
dma_i
.
dat
,
dma_rack
,
dma_rt
,
rd_int
,
vic_i
.
dat
,
vic_rack
,
vic_rt
,
rd_int
,
wrc_regs_i
.
dat
,
wrc_regs_rack
,
wrc_regs_rt
)
begin
process
(
wb_adr_i
,
reg_rdat_int
,
rd_ack1_int
,
rd_int
,
rd_int
,
metadata_data_i
,
metadata_rack
,
rd_int
,
therm_id_i
.
dat
,
therm_id_rack
,
therm_id_rt
,
rd_int
,
fmc_i2c_i
.
dat
,
fmc_i2c_rack
,
fmc_i2c_rt
,
rd_int
,
flash_spi_i
.
dat
,
flash_spi_rack
,
flash_spi_rt
,
rd_int
,
dma_i
.
dat
,
dma_rack
,
dma_rt
,
rd_int
,
vic_i
.
dat
,
vic_rack
,
vic_rt
,
rd_int
,
buildinfo_data_i
,
buildinfo_rack
,
rd_int
,
wrc_regs_i
.
dat
,
wrc_regs_rack
,
wrc_regs_rt
)
begin
-- By default ack read requests
wb_dat_o
<=
(
others
=>
'0'
);
metadata_re
<=
'0'
;
...
...
@@ -455,6 +474,7 @@ begin
flash_spi_re
<=
'0'
;
dma_re
<=
'0'
;
vic_re
<=
'0'
;
buildinfo_re
<=
'0'
;
wrc_regs_re
<=
'0'
;
case
wb_adr_i
(
12
downto
12
)
is
when
"0"
=>
...
...
@@ -538,6 +558,11 @@ begin
vic_re
<=
rd_int
;
wb_dat_o
<=
vic_i
.
dat
;
rd_ack_int
<=
vic_rack
;
when
"0010"
=>
-- Submap buildinfo
wb_dat_o
<=
buildinfo_data_i
;
rd_ack_int
<=
buildinfo_rack
;
buildinfo_re
<=
rd_int
;
when
others
=>
rd_ack_int
<=
rd_int
;
end
case
;
...
...
hdl/rtl/spec_template_wr.vhd
View file @
1aa51431
...
...
@@ -43,6 +43,7 @@ use work.gn4124_core_pkg.all;
use
work
.
wr_xilinx_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
use
work
.
wr_spec_pkg
.
all
;
use
work
.
synthesis_descriptor
.
all
;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
...
...
@@ -258,6 +259,9 @@ architecture top of spec_template_wr is
signal
metadata_addr
:
std_logic_vector
(
5
downto
2
);
signal
metadata_data
:
std_logic_vector
(
31
downto
0
);
signal
buildinfo_addr
:
std_logic_vector
(
7
downto
2
);
signal
buildinfo_data
:
std_logic_vector
(
31
downto
0
);
signal
therm_id_in
:
t_wishbone_master_in
;
signal
therm_id_out
:
t_wishbone_master_out
;
...
...
@@ -527,6 +531,11 @@ begin -- architecture top
vic_i
=>
vic_in
,
vic_o
=>
vic_out
,
-- a ROM containing build info
buildinfo_addr_o
=>
buildinfo_addr
,
buildinfo_data_i
=>
buildinfo_data
,
buildinfo_data_o
=>
open
,
-- white-rabbit core
wrc_regs_i
=>
wrc_in
,
wrc_regs_o
=>
wrc_out
...
...
@@ -570,12 +579,38 @@ begin -- architecture top
if
g_WITH_DDR
then
metadata_data
(
4
)
<=
'1'
;
end
if
;
-- Buildinfo
metadata_data
(
5
)
<=
'1'
;
when
others
=>
metadata_data
<=
x"00000000"
;
end
case
;
end
if
;
end
process
;
-- Build information
p_buildinfo
:
process
(
clk_sys_62m5
)
is
constant
buildinfo
:
string
:
=
"buildinfo:1"
&
LF
&
"module:"
&
c_sdb_synthesis_info
.
syn_module_name
&
LF
&
"commit:"
&
c_sdb_synthesis_info
.
syn_commit_id
&
LF
&
"syntool:"
&
c_sdb_synthesis_info
.
syn_tool_name
&
LF
&
"toolver:"
&
f_bits2string
(
c_sdb_synthesis_info
.
syn_tool_version
)
&
LF
&
"syndate:"
&
f_bits2string
(
c_sdb_synthesis_info
.
syn_date
)
&
LF
&
"synauth:"
&
c_sdb_synthesis_info
.
syn_username
&
LF
&
NUL
&
NUL
&
NUL
&
NUL
&
NUL
&
NUL
&
NUL
&
NUL
;
variable
addr
:
natural
;
begin
if
rising_edge
(
clk_sys_62m5
)
then
addr
:
=
to_integer
(
unsigned
(
buildinfo_addr
))
*
4
;
if
addr
<
buildinfo
'right
-
4
then
buildinfo_data
<=
f_string2svl
(
buildinfo
(
1
+
addr
to
4
+
addr
));
else
buildinfo_data
<=
x"00000000"
;
end
if
;
end
if
;
end
process
;
fmc_presence
(
0
)
<=
not
fmc0_prsnt_m2c_n_i
;
fmc_presence
(
31
downto
1
)
<=
(
others
=>
'0'
);
...
...
hdl/syn/golden_wr/Manifest.py
View file @
1aa51431
...
...
@@ -14,6 +14,8 @@ syn_properties = [ ["-generics", "dpram=\"3\""]]
board
=
"spec"
ctrls
=
[
"bank3_64b_32b"
]
files
=
[
"synthesis_descriptor.vhd"
]
modules
=
{
"local"
:
"../../top/golden_wr"
,
"git"
:
[
"https://ohwr.org/project/wr-cores.git::proposed_master"
,
...
...
@@ -22,3 +24,7 @@ modules = {
"https://ohwr.org/project/gn4124-core.git::proposed_master"
,
"https://ohwr.org/project/ddr3-sp6-core.git::proposed_master"
]
}
syn_post_project_cmd
=
\
"$(TCL_INTERPRETER) "
+
fetchto
+
"/general-cores/tools/sdb_desc_gen.tcl "
+
\
syn_tool
+
" $(PROJECT_FILE);"
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