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  SPDX-License-Identifier: LGPL-2.1-or-later
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  SPDX-FileCopyrightText: 2019 CERN

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==========
Change Log
==========
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3.0.0 - 2022-11-16
==================
Added
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- ci: better automation
- sw: support for Linux 5.10

Changed
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- sw|API change: the API to flash a bitstream moved from debugfs to sysfs to
  keep it symmetric to the SVEC driver that needed to change due to an
  incompatibility in 5.10
- hdl: update gn4124 and ddr3 ip-cores
- dist: improved RPM packaging
- bld: improved Makefiles

Fixed
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- sw: prevent kernel crash on invalid DMA transfer pointer
- sw: prevent objtool warning about frame pointer state mismatch
- doc: fixed building and configuration files to avoid warning on sphinx 5.x

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2.1.6 - 2021-07-29
==================
Fixed
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- sw: improve compatibilty with newer (greater than 3.10) Linux kernel version
  
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2.1.5 - 2021-05-18
==================
Fixed
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- sw: check if FPGA is programmed before loading FPGA devices
- doc: improve documentation

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2.1.4 - 2020-11-23
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Fixed
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- sw: SPEC driver detects the correct FLASH only on drivers reload

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2.1.3 - 2020-11-16
==================
Added
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- sw,drv: module parameter to ignore bitstream version check (for development
  or debug)
- sw: the spec-firmware-version tool can dump build-info

Fixed
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- hdl: DMA failures fixed with thight timing constraints

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2.1.2 - 2020-11-09
==================
Fixed
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- sw: automatize version validation

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2.1.1 - 2020-11-09
==================
Fixed
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- hdl: report the correct version in spec-golden design

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2.1.0 - 2020-11-09
==================
Fixed
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- hdl: cross-page DMA failure
- sw: DMA pool memory leak
- sw: fix concurrent DMA tasklet

Changed
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- tst: keep the DMA interface open while testing to avoid continuos
  memory re-allocation

Added
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- sw: tool to firmware version inspection
- sw: FLASH partitions

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2.0.2 - 2020-09-29
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==================
Fixed
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- hdl: L2P DMA issues reported with slower hosts

2.0.1 - 2020-08-20
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Fixed
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- sw: program 2 or more SPEC FPGAs in parallel. There is a bug in the
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  GN412x chip that we fixed in software by serializing any attempt of
  parallel programming

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2.0.0 - 2020-07-30
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==================
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Added
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- hdl: new testbench to test the DMA feature (read/write to DDR memory) in the new golden.
- sw: basic Python module to handle DMA and FPGA programming
- sw: user-space DMA interface in debugfs (read/write)
- tst: add integration tests for DMA transfers
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Changed
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- hdl: Switch to 125MHz (from 62.5MHz before) clock for DMA transfers.
- hdl: Cleanup of top-levels, addition of DMA to the golden.
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Fixed
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- hdl: DMA misalignment issue due to loss of 32-bit words, caused in turn by inadequate flow control.
- hdl: typo in synthesis constraints.
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1.4.15 - 2020-06-03
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===================
Added
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- hdl: ignore autogenerated files to build metadata (otherwise the repository
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  is always marked as dirty)

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1.4.14 - 2020-05-28
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===================
Added
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- hdl: export DDMTD clock output
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1.4.13 - 2020-05-12
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===================
Fixed
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- hdl: report correct version in spec-base metadata
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1.4.12 - 2020-05-12
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===================
Added
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- hdl: metadata source-id automatic assignment
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Changed
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- sw: do not double remap memory
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1.4.11 - 2020-05-04
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===================
Added
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- sw: added DMA engine channel for application to the list of resources
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Changed
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- sw: little code improvements
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1.4.10 - 2020-04-24
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===================
Changed
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- bld: assign dependencies path based on REPO_PARENT
- bld: check for missing dependencies
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Fixed
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- sw: fix kernel crash when programming new bitstream
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1.4.9 - 2020-03-10
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==================
Added
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- sw: support for kernel version more recent than 3.10 (RedHat)
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Fixed
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- sw: reduce allocation on stack
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1.4.8 - 2020-02-12
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==================
Fixed
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- sw: fix kernel crash when programming new bitstream
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1.4.7 - 2020-01-15
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==================
Fixed
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- doc: sysfs paths were wrong
- doc: incomplete driver loading list of commands
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1.4.6 - 2020-01-13
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==================
Changed
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- doc: improve documentation
- sw: better error reporting on I2C errors
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1.4.5 - 2019-12-17
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==================
Something happened while synchronizing different branches and version 1.4.4
could be inconsistent on different repositories. This release increment realign
all repositories

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1.4.4 - 2019-12-17
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==================
Changed
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- sw: better integration in coht, rename environment variable to FPGA_MGR

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Fixed
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- sw: suggested fixed reported by checkpatch and coccicheck
- hdl: restore lost references to git submodules
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1.4.3 - 2019-10-17
==================
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Fixed
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- sw: fix SPEC GPIO get_direction
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1.4.2 - 2019-10-15
==================
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Fixed
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- sw: fix SPEC driver dependency with I2C OCores
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1.4.1 - 2019-09-23
==================
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Changed
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- sw: do not used devm_* operations (it seems to solve problems)

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Removed
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- sw: Removed IRQ line assignment to FCL (not used)

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Fixed
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- sw: kcalloc usage
- sw:  memcpy(), memset() usage
- sw: checkpatch style fixes
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1.4.0 2019-09-11
================
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Added
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- hdl: spec-base IP-core to support SPEC based designs
- sw: Driver for GN4124 FCL using Linux FPGA manager
- sw: Driver for GN4124 GPIO using Linux GPIOlib
- sw: Driver for gn412x-core DMA using Linux DMA engine
- sw: Support for spec-base IP-core
- sw: Support for FMC
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0.0.0
=====
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Start the development of a new SPEC driver and SPEC HDL support layer