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  SPDX-License-Identifier: CC-0.0
  SPDX-FileCopyrightText: 2019 CERN

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=========
Changelog
=========
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2.0.0 - 2020-08-20
==================
Fixed
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- program 2 or more SPEC FPGAs in parallel. There is a bug in the
  GN412x chip that we fixed in software by serializing any attempt of
  parallel programming

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2.0.0 - 2020-07-30
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==================
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Added
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- hdl: new testbench to test the DMA feature (read/write to DDR memory) in the new golden.
- sw: basic Python module to handle DMA and FPGA programming
- sw: user-space DMA interface in debugfs (read/write)
- tst: add integration tests for DMA transfers
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Changed
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- hdl: Switch to 125MHz (from 62.5MHz before) clock for DMA transfers.
- hdl: Cleanup of top-levels, addition of DMA to the golden.
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Fixed
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- hdl: DMA misalignment issue due to loss of 32-bit words, caused in turn by inadequate flow control.
- hdl: typo in synthesis constraints.
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1.4.15 - 2020-06-03
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===================
Added
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- hdl: ignore autogenerated files to build metadata (otherwise the repository
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  is always marked as dirty)

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1.4.14 - 2020-05-28
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===================
Added
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- hdl: export DDMTD clock output
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1.4.13 - 2020-05-12
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===================
Fixed
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- hdl: report correct version in spec-base metadata
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1.4.12 - 2020-05-12
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===================
Added
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- hdl: metadata source-id automatic assignment
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Changed
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- sw: do not double remap memory
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1.4.11 - 2020-05-04
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===================
Added
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- sw: added DMA engine channel for application to the list of resources
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Changed
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- sw: little code improvements
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1.4.10 - 2020-04-24
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===================
Changed
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- bld: assign dependencies path based on REPO_PARENT
- bld: check for missing dependencies
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Fixed
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- sw: fix kernel crash when programming new bitstream
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1.4.9 - 2020-03-10
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==================
Added
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- sw: support for kernel version more recent than 3.10 (RedHat)
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Fixed
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- sw: reduce allocation on stack
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1.4.8 - 2020-02-12
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==================
Fixed
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- sw: fix kernel crash when programming new bitstream
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1.4.7 - 2020-01-15
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==================
Fixed
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- doc: sysfs paths were wrong
- doc: incomplete driver loading list of commands
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1.4.6 - 2020-01-13
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==================
Changed
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- doc: improve documentation
- sw: better error reporting on I2C errors
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1.4.5 - 2019-12-17
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==================
Something happened while synchronizing different branches and version 1.4.4
could be inconsistent on different repositories. This release increment realign
all repositories

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1.4.4 - 2019-12-17
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==================
Changed
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- sw: better integration in coht, rename environment variable to FPGA_MGR

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Fixed
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- sw: suggested fixed reported by checkpatch and coccicheck
- hdl: restore lost references to git submodules
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1.4.3 - 2019-10-17
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Fixed
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- sw: fix SPEC GPIO get_direction
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1.4.2 - 2019-10-15
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Fixed
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- sw: fix SPEC driver dependency with I2C OCores
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1.4.1 - 2019-09-23
==================
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Changed
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- sw: do not used devm_* operations (it seems to solve problems)

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Removed
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- sw: Removed IRQ line assignment to FCL (not used)

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Fixed
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- sw: kcalloc usage
- sw:  memcpy(), memset() usage
- sw: checkpatch style fixes
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1.4.0 2019-09-11
================
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Added
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- hdl: spec-base IP-core to support SPEC based designs
- sw: Driver for GN4124 FCL using Linux FPGA manager
- sw: Driver for GN4124 GPIO using Linux GPIOlib
- sw: Driver for gn412x-core DMA using Linux DMA engine
- sw: Support for spec-base IP-core
- sw: Support for FMC
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0.0.0
=====
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Start the development of a new SPEC driver and SPEC HDL support layer