spec_base_regs.vhd 20.9 KB
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-- Do not edit; this file was generated by Cheby using these options:
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--  --gen-hdl=spec_base_regs.vhd -i spec_base_regs.cheby
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

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entity spec_base_regs is
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  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_cyc_i             : in    std_logic;
    wb_stb_i             : in    std_logic;
    wb_adr_i             : in    std_logic_vector(12 downto 2);
    wb_sel_i             : in    std_logic_vector(3 downto 0);
    wb_we_i              : in    std_logic;
    wb_dat_i             : in    std_logic_vector(31 downto 0);
    wb_ack_o             : out   std_logic;
    wb_err_o             : out   std_logic;
    wb_rty_o             : out   std_logic;
    wb_stall_o           : out   std_logic;
    wb_dat_o             : out   std_logic_vector(31 downto 0);

    -- a ROM containing the carrier metadata
    metadata_addr_o      : out   std_logic_vector(5 downto 2);
    metadata_data_i      : in    std_logic_vector(31 downto 0);
    metadata_data_o      : out   std_logic_vector(31 downto 0);
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    metadata_wr_o        : out   std_logic;
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    -- offset to the application metadata
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    csr_app_offset_i     : in    std_logic_vector(31 downto 0);
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    csr_resets_global_o  : out   std_logic;
    csr_resets_appl_o    : out   std_logic;

    -- presence lines for the fmcs
    csr_fmc_presence_i   : in    std_logic_vector(31 downto 0);

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    -- status of gennum
    csr_gn4124_status_i  : in    std_logic_vector(31 downto 0);

    -- Set when calibration is done.
    csr_ddr_status_calib_done_i : in    std_logic;
    csr_pcb_rev_rev_i    : in    std_logic_vector(3 downto 0);

    -- Thermometer and unique id
    therm_id_i           : in    t_wishbone_master_in;
    therm_id_o           : out   t_wishbone_master_out;

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    -- i2c controllers to the fmcs
    fmc_i2c_i            : in    t_wishbone_master_in;
    fmc_i2c_o            : out   t_wishbone_master_out;

    -- spi controller to the flash
    flash_spi_i          : in    t_wishbone_master_in;
    flash_spi_o          : out   t_wishbone_master_out;

    -- dma registers for the gennum core
    dma_i                : in    t_wishbone_master_in;
    dma_o                : out   t_wishbone_master_out;

    -- vector interrupt controller
    vic_i                : in    t_wishbone_master_in;
    vic_o                : out   t_wishbone_master_out;

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    -- a ROM containing build information
    buildinfo_addr_o     : out   std_logic_vector(7 downto 2);
    buildinfo_data_i     : in    std_logic_vector(31 downto 0);
    buildinfo_data_o     : out   std_logic_vector(31 downto 0);
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    buildinfo_wr_o       : out   std_logic;
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    -- white-rabbit core registers
    wrc_regs_i           : in    t_wishbone_master_in;
    wrc_regs_o           : out   t_wishbone_master_out
  );
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end spec_base_regs;
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architecture syn of spec_base_regs is
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  signal rd_int                         : std_logic;
  signal wr_int                         : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal metadata_rack                  : std_logic;
  signal metadata_re                    : std_logic;
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  signal csr_resets_global_reg          : std_logic;
  signal csr_resets_appl_reg            : std_logic;
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  signal therm_id_re                    : std_logic;
  signal therm_id_wt                    : std_logic;
  signal therm_id_rt                    : std_logic;
  signal therm_id_tr                    : std_logic;
  signal therm_id_wack                  : std_logic;
  signal therm_id_rack                  : std_logic;
  signal fmc_i2c_re                     : std_logic;
  signal fmc_i2c_wt                     : std_logic;
  signal fmc_i2c_rt                     : std_logic;
  signal fmc_i2c_tr                     : std_logic;
  signal fmc_i2c_wack                   : std_logic;
  signal fmc_i2c_rack                   : std_logic;
  signal flash_spi_re                   : std_logic;
  signal flash_spi_wt                   : std_logic;
  signal flash_spi_rt                   : std_logic;
  signal flash_spi_tr                   : std_logic;
  signal flash_spi_wack                 : std_logic;
  signal flash_spi_rack                 : std_logic;
  signal dma_re                         : std_logic;
  signal dma_wt                         : std_logic;
  signal dma_rt                         : std_logic;
  signal dma_tr                         : std_logic;
  signal dma_wack                       : std_logic;
  signal dma_rack                       : std_logic;
  signal vic_re                         : std_logic;
  signal vic_wt                         : std_logic;
  signal vic_rt                         : std_logic;
  signal vic_tr                         : std_logic;
  signal vic_wack                       : std_logic;
  signal vic_rack                       : std_logic;
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  signal buildinfo_rack                 : std_logic;
  signal buildinfo_re                   : std_logic;
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  signal wrc_regs_re                    : std_logic;
  signal wrc_regs_wt                    : std_logic;
  signal wrc_regs_rt                    : std_logic;
  signal wrc_regs_tr                    : std_logic;
  signal wrc_regs_wack                  : std_logic;
  signal wrc_regs_rack                  : std_logic;
  signal reg_rdat_int                   : std_logic_vector(31 downto 0);
  signal rd_ack1_int                    : std_logic;
begin

  -- WB decode signals
  wb_en <= wb_cyc_i and wb_stb_i;

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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_we_i)) and not rd_ack_int;
      end if;
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    end if;
  end process;
  rd_int <= (wb_en and not wb_we_i) and not wb_rip;

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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_we_i)) and not wr_ack_int;
      end if;
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    end if;
  end process;
  wr_int <= (wb_en and wb_we_i) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_ack_o <= ack_int;
  wb_stall_o <= not ack_int and wb_en;
  wb_rty_o <= '0';
  wb_err_o <= '0';

  -- Assign outputs
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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        metadata_rack <= '0';
      else
        metadata_rack <= metadata_re and not metadata_rack;
      end if;
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    end if;
  end process;
  metadata_data_o <= wb_dat_i;
  metadata_addr_o <= wb_adr_i(5 downto 2);
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  csr_resets_global_o <= csr_resets_global_reg;
  csr_resets_appl_o <= csr_resets_appl_reg;
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  -- Assignments for submap therm_id
  therm_id_tr <= therm_id_wt or therm_id_rt;
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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        therm_id_rt <= '0';
      else
        therm_id_rt <= (therm_id_rt or therm_id_re) and not therm_id_rack;
      end if;
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    end if;
  end process;
  therm_id_o.cyc <= therm_id_tr;
  therm_id_o.stb <= therm_id_tr;
  therm_id_wack <= therm_id_i.ack and therm_id_wt;
  therm_id_rack <= therm_id_i.ack and therm_id_rt;
  therm_id_o.adr <= ((27 downto 0 => '0') & wb_adr_i(3 downto 2)) & (1 downto 0 => '0');
  therm_id_o.sel <= (others => '1');
  therm_id_o.we <= therm_id_wt;
  therm_id_o.dat <= wb_dat_i;

  -- Assignments for submap fmc_i2c
  fmc_i2c_tr <= fmc_i2c_wt or fmc_i2c_rt;
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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        fmc_i2c_rt <= '0';
      else
        fmc_i2c_rt <= (fmc_i2c_rt or fmc_i2c_re) and not fmc_i2c_rack;
      end if;
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    end if;
  end process;
  fmc_i2c_o.cyc <= fmc_i2c_tr;
  fmc_i2c_o.stb <= fmc_i2c_tr;
  fmc_i2c_wack <= fmc_i2c_i.ack and fmc_i2c_wt;
  fmc_i2c_rack <= fmc_i2c_i.ack and fmc_i2c_rt;
  fmc_i2c_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
  fmc_i2c_o.sel <= (others => '1');
  fmc_i2c_o.we <= fmc_i2c_wt;
  fmc_i2c_o.dat <= wb_dat_i;

  -- Assignments for submap flash_spi
  flash_spi_tr <= flash_spi_wt or flash_spi_rt;
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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        flash_spi_rt <= '0';
      else
        flash_spi_rt <= (flash_spi_rt or flash_spi_re) and not flash_spi_rack;
      end if;
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    end if;
  end process;
  flash_spi_o.cyc <= flash_spi_tr;
  flash_spi_o.stb <= flash_spi_tr;
  flash_spi_wack <= flash_spi_i.ack and flash_spi_wt;
  flash_spi_rack <= flash_spi_i.ack and flash_spi_rt;
  flash_spi_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
  flash_spi_o.sel <= (others => '1');
  flash_spi_o.we <= flash_spi_wt;
  flash_spi_o.dat <= wb_dat_i;

  -- Assignments for submap dma
  dma_tr <= dma_wt or dma_rt;
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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        dma_rt <= '0';
      else
        dma_rt <= (dma_rt or dma_re) and not dma_rack;
      end if;
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    end if;
  end process;
  dma_o.cyc <= dma_tr;
  dma_o.stb <= dma_tr;
  dma_wack <= dma_i.ack and dma_wt;
  dma_rack <= dma_i.ack and dma_rt;
  dma_o.adr <= ((25 downto 0 => '0') & wb_adr_i(5 downto 2)) & (1 downto 0 => '0');
  dma_o.sel <= (others => '1');
  dma_o.we <= dma_wt;
  dma_o.dat <= wb_dat_i;

  -- Assignments for submap vic
  vic_tr <= vic_wt or vic_rt;
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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        vic_rt <= '0';
      else
        vic_rt <= (vic_rt or vic_re) and not vic_rack;
      end if;
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    end if;
  end process;
  vic_o.cyc <= vic_tr;
  vic_o.stb <= vic_tr;
  vic_wack <= vic_i.ack and vic_wt;
  vic_rack <= vic_i.ack and vic_rt;
  vic_o.adr <= ((23 downto 0 => '0') & wb_adr_i(7 downto 2)) & (1 downto 0 => '0');
  vic_o.sel <= (others => '1');
  vic_o.we <= vic_wt;
  vic_o.dat <= wb_dat_i;
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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        buildinfo_rack <= '0';
      else
        buildinfo_rack <= buildinfo_re and not buildinfo_rack;
      end if;
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    end if;
  end process;
  buildinfo_data_o <= wb_dat_i;
  buildinfo_addr_o <= wb_adr_i(7 downto 2);
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  -- Assignments for submap wrc_regs
  wrc_regs_tr <= wrc_regs_wt or wrc_regs_rt;
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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wrc_regs_rt <= '0';
      else
        wrc_regs_rt <= (wrc_regs_rt or wrc_regs_re) and not wrc_regs_rack;
      end if;
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    end if;
  end process;
  wrc_regs_o.cyc <= wrc_regs_tr;
  wrc_regs_o.stb <= wrc_regs_tr;
  wrc_regs_wack <= wrc_regs_i.ack and wrc_regs_wt;
  wrc_regs_rack <= wrc_regs_i.ack and wrc_regs_rt;
  wrc_regs_o.adr <= ((19 downto 0 => '0') & wb_adr_i(11 downto 2)) & (1 downto 0 => '0');
  wrc_regs_o.sel <= (others => '1');
  wrc_regs_o.we <= wrc_regs_wt;
  wrc_regs_o.dat <= wb_dat_i;

  -- Process for write requests.
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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wr_ack_int <= '0';
        metadata_wr_o <= '0';
        csr_resets_global_reg <= '0';
        csr_resets_appl_reg <= '0';
        therm_id_wt <= '0';
        fmc_i2c_wt <= '0';
        flash_spi_wt <= '0';
        dma_wt <= '0';
        vic_wt <= '0';
        buildinfo_wr_o <= '0';
        wrc_regs_wt <= '0';
      else
        wr_ack_int <= '0';
        metadata_wr_o <= '0';
        therm_id_wt <= '0';
        fmc_i2c_wt <= '0';
        flash_spi_wt <= '0';
        dma_wt <= '0';
        vic_wt <= '0';
        buildinfo_wr_o <= '0';
        wrc_regs_wt <= '0';
        case wb_adr_i(12 downto 12) is
        when "0" => 
          case wb_adr_i(11 downto 8) is
          when "0000" => 
            case wb_adr_i(7 downto 6) is
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            when "00" => 
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              -- Submap metadata
              metadata_wr_o <= wr_int;
              wr_ack_int <= wr_int;
            when "01" => 
              case wb_adr_i(5 downto 4) is
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              when "00" => 
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                case wb_adr_i(3 downto 2) is
                when "00" => 
                  -- Register csr_app_offset
                when "01" => 
                  -- Register csr_resets
                  if wr_int = '1' then
                    csr_resets_global_reg <= wb_dat_i(0);
                    csr_resets_appl_reg <= wb_dat_i(1);
                  end if;
                  wr_ack_int <= wr_int;
                when "10" => 
                  -- Register csr_fmc_presence
                when "11" => 
                  -- Register csr_gn4124_status
                when others =>
                  wr_ack_int <= wr_int;
                end case;
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              when "01" => 
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                case wb_adr_i(3 downto 2) is
                when "00" => 
                  -- Register csr_ddr_status
                when "01" => 
                  -- Register csr_pcb_rev
                when others =>
                  wr_ack_int <= wr_int;
                end case;
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              when "11" => 
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                -- Submap therm_id
                therm_id_wt <= (therm_id_wt or wr_int) and not therm_id_wack;
                wr_ack_int <= therm_id_wack;
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              when others =>
                wr_ack_int <= wr_int;
              end case;
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            when "10" => 
              case wb_adr_i(5 downto 5) is
              when "0" => 
                -- Submap fmc_i2c
                fmc_i2c_wt <= (fmc_i2c_wt or wr_int) and not fmc_i2c_wack;
                wr_ack_int <= fmc_i2c_wack;
              when "1" => 
                -- Submap flash_spi
                flash_spi_wt <= (flash_spi_wt or wr_int) and not flash_spi_wack;
                wr_ack_int <= flash_spi_wack;
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              when others =>
                wr_ack_int <= wr_int;
              end case;
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            when "11" => 
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              -- Submap dma
              dma_wt <= (dma_wt or wr_int) and not dma_wack;
              wr_ack_int <= dma_wack;
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            when others =>
              wr_ack_int <= wr_int;
            end case;
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          when "0001" => 
            -- Submap vic
            vic_wt <= (vic_wt or wr_int) and not vic_wack;
            wr_ack_int <= vic_wack;
          when "0010" => 
            -- Submap buildinfo
            buildinfo_wr_o <= wr_int;
            wr_ack_int <= wr_int;
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          when others =>
            wr_ack_int <= wr_int;
          end case;
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        when "1" => 
          -- Submap wrc_regs
          wrc_regs_wt <= (wrc_regs_wt or wr_int) and not wrc_regs_wack;
          wr_ack_int <= wrc_regs_wack;
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        when others =>
          wr_ack_int <= wr_int;
        end case;
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      end if;
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    end if;
  end process;

  -- Process for registers read.
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  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack1_int <= '0';
      else
        reg_rdat_int <= (others => '0');
        case wb_adr_i(12 downto 12) is
        when "0" => 
          case wb_adr_i(11 downto 8) is
          when "0000" => 
            case wb_adr_i(7 downto 6) is
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            when "00" => 
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            when "01" => 
              case wb_adr_i(5 downto 4) is
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              when "00" => 
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                case wb_adr_i(3 downto 2) is
                when "00" => 
                  -- csr_app_offset
                  reg_rdat_int <= csr_app_offset_i;
                  rd_ack1_int <= rd_int;
                when "01" => 
                  -- csr_resets
                  reg_rdat_int(0) <= csr_resets_global_reg;
                  reg_rdat_int(1) <= csr_resets_appl_reg;
                  rd_ack1_int <= rd_int;
                when "10" => 
                  -- csr_fmc_presence
                  reg_rdat_int <= csr_fmc_presence_i;
                  rd_ack1_int <= rd_int;
                when "11" => 
                  -- csr_gn4124_status
                  reg_rdat_int <= csr_gn4124_status_i;
                  rd_ack1_int <= rd_int;
                when others =>
                  reg_rdat_int <= (others => 'X');
                  rd_ack1_int <= rd_int;
                end case;
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              when "01" => 
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                case wb_adr_i(3 downto 2) is
                when "00" => 
                  -- csr_ddr_status
                  reg_rdat_int(0) <= csr_ddr_status_calib_done_i;
                  rd_ack1_int <= rd_int;
                when "01" => 
                  -- csr_pcb_rev
                  reg_rdat_int(3 downto 0) <= csr_pcb_rev_rev_i;
                  rd_ack1_int <= rd_int;
                when others =>
                  reg_rdat_int <= (others => 'X');
                  rd_ack1_int <= rd_int;
                end case;
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              when "11" => 
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              when others =>
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                reg_rdat_int <= (others => 'X');
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                rd_ack1_int <= rd_int;
              end case;
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            when "10" => 
              case wb_adr_i(5 downto 5) is
              when "0" => 
              when "1" => 
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              when others =>
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                reg_rdat_int <= (others => 'X');
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                rd_ack1_int <= rd_int;
              end case;
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            when "11" => 
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            when others =>
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              reg_rdat_int <= (others => 'X');
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              rd_ack1_int <= rd_int;
            end case;
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          when "0001" => 
          when "0010" => 
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          when others =>
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            reg_rdat_int <= (others => 'X');
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            rd_ack1_int <= rd_int;
          end case;
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        when "1" => 
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        when others =>
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          reg_rdat_int <= (others => 'X');
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          rd_ack1_int <= rd_int;
        end case;
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      end if;
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    end if;
  end process;

  -- Process for read requests.
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  process (wb_adr_i, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_data_i, metadata_rack, rd_int, therm_id_i.dat, therm_id_rack, therm_id_rt, rd_int, fmc_i2c_i.dat, fmc_i2c_rack, fmc_i2c_rt, rd_int, flash_spi_i.dat, flash_spi_rack, flash_spi_rt, rd_int, dma_i.dat, dma_rack, dma_rt, rd_int, vic_i.dat, vic_rack, vic_rt, rd_int, buildinfo_data_i, buildinfo_rack, rd_int, wrc_regs_i.dat, wrc_regs_rack, wrc_regs_rt) begin
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    -- By default ack read requests
    wb_dat_o <= (others => '0');
    metadata_re <= '0';
    therm_id_re <= '0';
    fmc_i2c_re <= '0';
    flash_spi_re <= '0';
    dma_re <= '0';
    vic_re <= '0';
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    buildinfo_re <= '0';
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    wrc_regs_re <= '0';
    case wb_adr_i(12 downto 12) is
    when "0" => 
      case wb_adr_i(11 downto 8) is
      when "0000" => 
        case wb_adr_i(7 downto 6) is
        when "00" => 
          -- Submap metadata
          wb_dat_o <= metadata_data_i;
          rd_ack_int <= metadata_rack;
          metadata_re <= rd_int;
        when "01" => 
          case wb_adr_i(5 downto 4) is
          when "00" => 
            case wb_adr_i(3 downto 2) is
            when "00" => 
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              -- csr_app_offset
              wb_dat_o <= reg_rdat_int;
              rd_ack_int <= rd_ack1_int;
            when "01" => 
              -- csr_resets
              wb_dat_o <= reg_rdat_int;
              rd_ack_int <= rd_ack1_int;
            when "10" => 
              -- csr_fmc_presence
              wb_dat_o <= reg_rdat_int;
              rd_ack_int <= rd_ack1_int;
            when "11" => 
              -- csr_gn4124_status
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              wb_dat_o <= reg_rdat_int;
              rd_ack_int <= rd_ack1_int;
            when others =>
              rd_ack_int <= rd_int;
            end case;
          when "01" => 
            case wb_adr_i(3 downto 2) is
            when "00" => 
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              -- csr_ddr_status
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              wb_dat_o <= reg_rdat_int;
              rd_ack_int <= rd_ack1_int;
            when "01" => 
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              -- csr_pcb_rev
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              wb_dat_o <= reg_rdat_int;
              rd_ack_int <= rd_ack1_int;
            when others =>
              rd_ack_int <= rd_int;
            end case;
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          when "11" => 
            -- Submap therm_id
            therm_id_re <= rd_int;
            wb_dat_o <= therm_id_i.dat;
            rd_ack_int <= therm_id_rack;
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          when others =>
            rd_ack_int <= rd_int;
          end case;
        when "10" => 
          case wb_adr_i(5 downto 5) is
          when "0" => 
            -- Submap fmc_i2c
            fmc_i2c_re <= rd_int;
            wb_dat_o <= fmc_i2c_i.dat;
            rd_ack_int <= fmc_i2c_rack;
          when "1" => 
            -- Submap flash_spi
            flash_spi_re <= rd_int;
            wb_dat_o <= flash_spi_i.dat;
            rd_ack_int <= flash_spi_rack;
          when others =>
            rd_ack_int <= rd_int;
          end case;
        when "11" => 
          -- Submap dma
          dma_re <= rd_int;
          wb_dat_o <= dma_i.dat;
          rd_ack_int <= dma_rack;
        when others =>
          rd_ack_int <= rd_int;
        end case;
      when "0001" => 
        -- Submap vic
        vic_re <= rd_int;
        wb_dat_o <= vic_i.dat;
        rd_ack_int <= vic_rack;
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      when "0010" => 
        -- Submap buildinfo
        wb_dat_o <= buildinfo_data_i;
        rd_ack_int <= buildinfo_rack;
        buildinfo_re <= rd_int;
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      when others =>
        rd_ack_int <= rd_int;
      end case;
    when "1" => 
      -- Submap wrc_regs
      wrc_regs_re <= rd_int;
      wb_dat_o <= wrc_regs_i.dat;
      rd_ack_int <= wrc_regs_rack;
    when others =>
      rd_ack_int <= rd_int;
    end case;
  end process;
end syn;