CHANGELOG.rst 4.11 KB
Newer Older
1
..
Federico Vaga's avatar
Federico Vaga committed
2
  SPDX-License-Identifier: CC0-1.0
3 4
  SPDX-FileCopyrightText: 2019 CERN

Federico Vaga's avatar
Federico Vaga committed
5 6 7
=========
Changelog
=========
8

Federico Vaga's avatar
Federico Vaga committed
9 10 11 12 13 14
2.1.1 - 2020-11-09
==================
Fixed
-----
- hdl: report the correct version in spec-golden design

Federico Vaga's avatar
Federico Vaga committed
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2.1.0 - 2020-11-09
==================
Fixed
-----
- hdl: cross-page DMA failure
- sw: DMA pool memory leak
- sw: fix concurrent DMA tasklet

Changed
-------
- tst: keep the DMA interface open while testing to avoid continuos
  memory re-allocation

Added
-----
- sw: tool to firmware version inspection
- sw: FLASH partitions

33
2.0.2 - 2020-09-29
34 35 36
==================
Fixed
-----
37 38 39 40 41 42 43
- hdl: L2P DMA issues reported with slower hosts

2.0.1 - 2020-08-20
==================
Fixed
-----
- sw: program 2 or more SPEC FPGAs in parallel. There is a bug in the
44 45 46
  GN412x chip that we fixed in software by serializing any attempt of
  parallel programming

47
2.0.0 - 2020-07-30
48
==================
49 50
Added
-----
51 52 53 54
- hdl: new testbench to test the DMA feature (read/write to DDR memory) in the new golden.
- sw: basic Python module to handle DMA and FPGA programming
- sw: user-space DMA interface in debugfs (read/write)
- tst: add integration tests for DMA transfers
55 56 57

Changed
-------
58 59
- hdl: Switch to 125MHz (from 62.5MHz before) clock for DMA transfers.
- hdl: Cleanup of top-levels, addition of DMA to the golden.
60 61 62

Fixed
-----
63 64
- hdl: DMA misalignment issue due to loss of 32-bit words, caused in turn by inadequate flow control.
- hdl: typo in synthesis constraints.
65

66
1.4.15 - 2020-06-03
67 68
===================
Added
69 70
-----
- hdl: ignore autogenerated files to build metadata (otherwise the repository
71 72
  is always marked as dirty)

73
1.4.14 - 2020-05-28
74 75 76
===================
Added
-----
77
- hdl: export DDMTD clock output
78

79
1.4.13 - 2020-05-12
80 81 82
===================
Fixed
-----
83
- hdl: report correct version in spec-base metadata
84 85


86
1.4.12 - 2020-05-12
87 88 89
===================
Added
-----
90
- hdl: metadata source-id automatic assignment
91 92

Changed
93 94
-------
- sw: do not double remap memory
95

96
1.4.11 - 2020-05-04
97 98 99
===================
Added
-----
100
- sw: added DMA engine channel for application to the list of resources
101 102

Changed
103 104
-------
- sw: little code improvements
105

106
1.4.10 - 2020-04-24
107 108 109
===================
Changed
-------
110 111
- bld: assign dependencies path based on REPO_PARENT
- bld: check for missing dependencies
112 113 114

Fixed
-----
115
- sw: fix kernel crash when programming new bitstream
116

117
1.4.9 - 2020-03-10
118 119 120
==================
Added
-----
121
- sw: support for kernel version more recent than 3.10 (RedHat)
122 123 124

Fixed
-----
125
- sw: reduce allocation on stack
126

127
1.4.8 - 2020-02-12
128 129 130
==================
Fixed
-----
131
- sw: fix kernel crash when programming new bitstream
132

133
1.4.7 - 2020-01-15
134 135 136
==================
Fixed
-------
137 138
- doc: sysfs paths were wrong
- doc: incomplete driver loading list of commands
139

140
1.4.6 - 2020-01-13
141 142 143
==================
Changed
-------
144 145
- doc: improve documentation
- sw: better error reporting on I2C errors
146

147
1.4.5 - 2019-12-17
148 149 150 151 152
==================
Something happened while synchronizing different branches and version 1.4.4
could be inconsistent on different repositories. This release increment realign
all repositories

153
1.4.4 - 2019-12-17
154 155
==================
Changed
156 157 158
-------
- sw: better integration in coht, rename environment variable to FPGA_MGR

159 160
Fixed
-----
161 162
- sw: suggested fixed reported by checkpatch and coccicheck
- hdl: restore lost references to git submodules
163

164 165
1.4.3 - 2019-10-17
==================
166 167
Fixed
-----
168
- sw: fix SPEC GPIO get_direction
169

170 171
1.4.2 - 2019-10-15
==================
172 173
Fixed
-----
174
- sw: fix SPEC driver dependency with I2C OCores
175

176 177
1.4.1 - 2019-09-23
==================
Federico Vaga's avatar
Federico Vaga committed
178 179
Changed
-------
180 181
- sw: do not used devm_* operations (it seems to solve problems)

Federico Vaga's avatar
Federico Vaga committed
182 183
Removed
-------
184 185
- sw: Removed IRQ line assignment to FCL (not used)

Federico Vaga's avatar
Federico Vaga committed
186 187
Fixed
-----
188 189 190
- sw: kcalloc usage
- sw:  memcpy(), memset() usage
- sw: checkpatch style fixes
Federico Vaga's avatar
Federico Vaga committed
191

192 193
1.4.0 2019-09-11
================
Federico Vaga's avatar
Federico Vaga committed
194 195
Added
-----
196 197 198 199 200 201
- hdl: spec-base IP-core to support SPEC based designs
- sw: Driver for GN4124 FCL using Linux FPGA manager
- sw: Driver for GN4124 GPIO using Linux GPIOlib
- sw: Driver for gn412x-core DMA using Linux DMA engine
- sw: Support for spec-base IP-core
- sw: Support for FMC
202

203 204
0.0.0
=====
Federico Vaga's avatar
Federico Vaga committed
205
Start the development of a new SPEC driver and SPEC HDL support layer