pax_global_header 0000666 0000000 0000000 00000000064 13451647003 0014515 g ustar 00root root 0000000 0000000 52 comment=3f8b3d4a2e5bb0152f6534681a61e37c4524c3be
spec-v0.3.2/ 0000775 0000000 0000000 00000000000 13451647003 0012637 5 ustar 00root root 0000000 0000000 spec-v0.3.2/.gitignore 0000664 0000000 0000000 00000000152 13451647003 0014625 0 ustar 00root root 0000000 0000000 *.o
*.ko
*.mod.c
.*.o.cmd
.*.ko.cmd
*.mod.d
*.o.d
*.tmp
.tmp_versions
modules.order
Module.symvers
\#*
*~
spec-v0.3.2/CHANGELOG 0000664 0000000 0000000 00000000154 13451647003 0014051 0 ustar 00root root 0000000 0000000 # Changelog
## [0.1.0] 2017-11-15
### Added
- Linux Device Driver skeleton
## [0.0.0]
Start the development
spec-v0.3.2/LICENSES/ 0000775 0000000 0000000 00000000000 13451647003 0014044 5 ustar 00root root 0000000 0000000 spec-v0.3.2/LICENSES/GPL-2.0.txt 0000664 0000000 0000000 00000043172 13451647003 0015533 0 ustar 00root root 0000000 0000000 GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
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When we speak of free software, we are referring to freedom, not
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The precise terms and conditions for copying, distribution and
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GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
a notice placed by the copyright holder saying it may be distributed
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Whether that is true depends on what the Program does.
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END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
fmc-spec
Copyright (C) 2017 Federico Vaga
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
{signature of Ty Coon}, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.
spec-v0.3.2/Makefile 0000664 0000000 0000000 00000001155 13451647003 0014301 0 ustar 00root root 0000000 0000000 -include Makefile.specific
# include parent_common.mk for buildsystem's defines
#use absolute path for REPO_PARENT
REPO_PARENT ?= $(shell /bin/pwd)/..
-include $(REPO_PARENT)/parent_common.mk
DIRS = kernel
.PHONY: all clean modules install modules_install $(DIRS)
all clean modules install modules_install: $(DIRS)
clean: TARGET = clean
modules: TARGET = modules
install: TARGET = install
modules_install: TARGET = modules_install
ENV_VAR := CONFIG_FPGA_MGR_BACKPORT_PATH=$(CONFIG_FPGA_MGR_BACKPORT_PATH)
ENV_VAR += CONFIG_FPGA_MGR_BACKPORT=$(CONFIG_FPGA_MGR_BACKPORT)
$(DIRS):
$(MAKE) -C $@ $(ENV_VAR) $(TARGET)
spec-v0.3.2/README.rst 0000664 0000000 0000000 00000001067 13451647003 0014332 0 ustar 00root root 0000000 0000000 .. image:: ./doc/spec-logo.png
SPEC Driver
===========
This is the simplified version of the SPEC driver which only purpose is
to export an interface to enable the users to program their bitstream on
the SPEC FPGA.
Build Sources
=============
There are no special requirements to build the SPEC.
The documentation is written in reStructuredText and it generates HTML files
and man pages. For this you need the python docutils package installed
If the requirements are satified you can run the following commant in
the project root directory:
.. code::
make
spec-v0.3.2/kernel/ 0000775 0000000 0000000 00000000000 13451647003 0014117 5 ustar 00root root 0000000 0000000 spec-v0.3.2/kernel/Kbuild 0000664 0000000 0000000 00000002105 13451647003 0015252 0 ustar 00root root 0000000 0000000 # add versions of supermodule. It is useful when spec is included as sub-module
# of a bigger project that we want to track
ifdef CONFIG_SUPER_REPO
ifdef CONFIG_SUPER_REPO_VERSION
SUBMODULE_VERSIONS += MODULE_INFO(version_$(CONFIG_SUPER_REPO),\"$(CONFIG_SUPER_REPO_VERSION)\");
endif
endif
# add versions of used submodules
CONFIG_FPGA_MGR_BACKPORT_INCLUDE := -I$(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS)/include
CONFIG_FPGA_MGR_BACKPORT_INCLUDE += -I$(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS)/include/linux
ccflags-y += -DADDITIONAL_VERSIONS="$(SUBMODULE_VERSIONS)"
ccflags-y += -DGIT_VERSION=\"$(GIT_VERSION)\"
ccflags-y += -Wall -Werror
ccflags-$(CONFIG_FPGA_MGR_BACKPORT) += -DCONFIG_FPGA_MGR_BACKPORT
ccflags-$(CONFIG_FPGA_MGR_BACKPORT) += $(CONFIG_FPGA_MGR_BACKPORT_INCLUDE)
ifeq ($(CONFIG_FPGA_MGR_BACKPORT), y)
LINUXINCLUDE := $(CONFIG_FPGA_MGR_BACKPORT_INCLUDE) $(LINUXINCLUDE)
KBUILD_EXTRA_SYMBOLS += $(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS)/drivers/fpga/Module.symvers
endif
obj-m := spec.o
spec-objs := spec-core.o
spec-objs += spec-fpga.o
spec-objs += spec-irq.o
spec-objs += spec-compat.o
spec-v0.3.2/kernel/Makefile 0000664 0000000 0000000 00000001520 13451647003 0015555 0 ustar 00root root 0000000 0000000 # include parent_common.mk for buildsystem's defines
#use absolute path for REPO_PARENT
REPO_PARENT ?= $(shell /bin/pwd)/../..
-include $(REPO_PARENT)/parent_common.mk
LINUX ?= /lib/modules/$(shell uname -r)/build
CONFIG_FPGA_MGR_BACKPORT_PATH_ABS ?= $(abspath $(CONFIG_FPGA_MGR_BACKPORT_PATH))
GIT_VERSION = $(shell git describe --dirty --long --tags)
all: modules
.PHONY: all modules clean help install modules_install
modules help install modules_install:
$(MAKE) -C $(LINUX) M=$(shell pwd) GIT_VERSION=$(GIT_VERSION) CONFIG_FPGA_MGR_BACKPORT_PATH_ABS=$(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS) CONFIG_FPGA_MGR_BACKPORT=$(CONFIG_FPGA_MGR_BACKPORT) $@
# be able to run the "clean" rule even if $(LINUX) is not valid
clean:
rm -rf *.o *~ .*.cmd *.ko *.mod.c .tmp_versions Module.symvers \
Module.markers modules.order
spec-v0.3.2/kernel/spec-compat.c 0000664 0000000 0000000 00000010461 13451647003 0016500 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2017 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#include
#include
#include
#include
#include "spec-compat.h"
int compat_get_fpga_last_word_size(struct fpga_image_info *info, size_t count)
{
#if KERNEL_VERSION(4,16,0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
return count;
#else
return info ? info->count : count;
#endif
}
#if KERNEL_VERSION(4,10,0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
int compat_spec_fpga_write_init(struct fpga_manager *mgr,
u32 flags,
const char *buf, size_t count)
{
return spec_fpga_write_init(mgr, NULL, buf, count);
}
int compat_spec_fpga_write_complete(struct fpga_manager *mgr,
u32 flags)
{
return spec_fpga_write_complete(mgr, NULL);
}
#else
int compat_spec_fpga_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count)
{
return spec_fpga_write_init(mgr, info, buf, count);
}
int compat_spec_fpga_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info)
{
return spec_fpga_write_complete(mgr, info);
}
#endif
#if KERNEL_VERSION(4,18,0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
struct fpga_manager *compat_fpga_mgr_create(struct device *dev, const char *name,
const struct fpga_manager_ops *mops,
void *priv)
{
int err;
err = fpga_mgr_register(dev, name, mops, priv);
if (err)
return NULL;
return (struct fpga_manager *)dev;
}
void compat_fpga_mgr_free(struct fpga_manager *mgr)
{
fpga_mgr_unregister((struct device *)mgr);
}
int compat_fpga_mgr_register(struct fpga_manager *mgr)
{
return mgr ? 0 : 1;
}
void compat_fpga_mgr_unregister(struct fpga_manager *mgr)
{
fpga_mgr_unregister((struct device *)mgr);
}
#else
struct fpga_manager *compat_fpga_mgr_create(struct device *dev,
const char *name,
const struct fpga_manager_ops *mops,
void *priv)
{
return fpga_mgr_create(dev, name, mops, priv);
}
void compat_fpga_mgr_free(struct fpga_manager *mgr)
{
fpga_mgr_free(mgr);
}
int compat_fpga_mgr_register(struct fpga_manager *mgr)
{
return fpga_mgr_register(mgr);
}
void compat_fpga_mgr_unregister(struct fpga_manager *mgr)
{
fpga_mgr_unregister(mgr);
}
#endif
#if KERNEL_VERSION(4,10,0) > LINUX_VERSION_CODE
struct fpga_manager *__fpga_mgr_get(struct device *dev)
{
struct fpga_manager *mgr;
int ret = -ENODEV;
mgr = to_fpga_manager(dev);
if (!mgr)
goto err_dev;
/* Get exclusive use of fpga manager */
if (!mutex_trylock(&mgr->ref_mutex)) {
ret = -EBUSY;
goto err_dev;
}
if (!try_module_get(dev->parent->driver->owner))
goto err_ll_mod;
return mgr;
err_ll_mod:
mutex_unlock(&mgr->ref_mutex);
err_dev:
put_device(dev);
return ERR_PTR(ret);
}
static int fpga_mgr_dev_match(struct device *dev, const void *data)
{
return dev->parent == data;
}
/**
* fpga_mgr_get - get an exclusive reference to a fpga mgr
* @dev:parent device that fpga mgr was registered with
*
* Given a device, get an exclusive reference to a fpga mgr.
*
* Return: fpga manager struct or IS_ERR() condition containing error code.
*/
struct fpga_manager *fpga_mgr_get(struct device *dev)
{
void *fpga_mgr_class = (void*) kallsyms_lookup_name("fpga_mgr_class");
struct device *mgr_dev = class_find_device(fpga_mgr_class, NULL, dev,
fpga_mgr_dev_match);
if (!mgr_dev)
return ERR_PTR(-ENODEV);
return __fpga_mgr_get(mgr_dev);
}
#endif
static int __compat_spec_fw_load(struct fpga_manager *mgr, const char *name)
{
#if KERNEL_VERSION(4,16,0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
#if KERNEL_VERSION(4,10,0) > LINUX_VERSION_CODE
return fpga_mgr_firmware_load(mgr, 0, name);
#else
struct fpga_image_info image;
memset(&image, 0, sizeof(image));
return fpga_mgr_firmware_load(mgr, &image, name);
#endif
#else
struct fpga_image_info image;
memset(&image, 0, sizeof(image));
image.firmware_name = (char *)name;
image.dev = mgr->dev.parent;
return fpga_mgr_load(mgr, &image);
#endif
}
int compat_spec_fw_load(struct spec_dev *spec, const char *name)
{
struct fpga_manager *mgr;
int err;
mgr = fpga_mgr_get(&spec->dev);
if (IS_ERR(mgr))
return -ENODEV;
err = __compat_spec_fw_load(mgr, name);
fpga_mgr_put(mgr);
return err;
}
spec-v0.3.2/kernel/spec-compat.h 0000664 0000000 0000000 00000005170 13451647003 0016506 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2017 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#include
#include
#include
#include "spec.h"
#if KERNEL_VERSION(4,10,0) <= LINUX_VERSION_CODE
#if KERNEL_VERSION(4,16,0) > LINUX_VERSION_CODE
/* So that we select the buffer size because smaller */
#define compat_fpga_ops_initial_header_size .initial_header_size = 0xFFFFFFFF,
#else
#define compat_fpga_ops_initial_header_size .initial_header_size = 0,
#endif
#else
#define compat_fpga_ops_initial_header_size
#endif
#if KERNEL_VERSION(4,16,0) > LINUX_VERSION_CODE && ! defined(CONFIG_FPGA_MGR_BACKPORT)
#define compat_fpga_ops_groups
#else
#define compat_fpga_ops_groups .groups = NULL,
#endif
#if KERNEL_VERSION(4,10,0) > LINUX_VERSION_CODE && ! defined(CONFIG_FPGA_MGR_BACKPORT)
struct fpga_image_info;
#endif
int spec_fpga_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count);
int spec_fpga_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info);
#if KERNEL_VERSION(4,10,0) > LINUX_VERSION_CODE && ! defined(CONFIG_FPGA_MGR_BACKPORT)
int compat_spec_fpga_write_init(struct fpga_manager *mgr, u32 flags,
const char *buf, size_t count);
int compat_spec_fpga_write_complete(struct fpga_manager *mgr, u32 flags);
#else
int compat_spec_fpga_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count);
int compat_spec_fpga_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info);
#endif
int compat_get_fpga_last_word_size(struct fpga_image_info *info,
size_t count);
struct fpga_manager *compat_fpga_mgr_create(struct device *dev,
const char *name,
const struct fpga_manager_ops *mops,
void *priv);
void compat_fpga_mgr_free(struct fpga_manager *mgr);
int compat_fpga_mgr_register(struct fpga_manager *mgr);
void compat_fpga_mgr_unregister(struct fpga_manager *mgr);
int compat_spec_fw_load(struct spec_dev *spec, const char *name);
#if KERNEL_VERSION(3, 11, 0) > LINUX_VERSION_CODE
#define __ATTR_RW(_name) __ATTR(_name, (S_IWUSR | S_IRUGO), \
_name##_show, _name##_store)
#define __ATTR_WO(_name) { \
.attr = { .name = __stringify(_name), .mode = S_IWUSR }, \
.store = _name##_store, \
}
#define DEVICE_ATTR_RW(_name) \
struct device_attribute dev_attr_##_name = __ATTR_RW(_name)
#define DEVICE_ATTR_RO(_name) \
struct device_attribute dev_attr_##_name = __ATTR_RO(_name)
#define DEVICE_ATTR_WO(_name) \
struct device_attribute dev_attr_##_name = __ATTR_WO(_name)
#endif
spec-v0.3.2/kernel/spec-core.c 0000664 0000000 0000000 00000012016 13451647003 0016143 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2017 CERN (www.cern.ch)
* Author: Federico Vaga
*
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Driver for SPEC (Simple PCI FMC carrier) board.
*/
#include
#include
#include
#include
#include
#include
#include "spec.h"
#include "spec-compat.h"
static char *spec_fw_name_45t = "spec-init-45T.bin";
static char *spec_fw_name_100t = "spec-init-100T.bin";
static char *spec_fw_name_150t = "spec-init-150T.bin";
char *spec_fw_name = "";
module_param_named(fw_name, spec_fw_name, charp, 0444);
/**
* Return the SPEC defult FPGA firmware name based on PCI ID
* @spec: SPEC device
*
* Return: FPGA firmware name
*/
static const char *spec_fw_name_init_get(struct spec_dev *spec)
{
struct pci_dev *pdev = to_pci_dev(spec->dev.parent);
if (strlen(spec_fw_name) > 0)
return spec_fw_name;
switch (pdev->device) {
case PCI_DEVICE_ID_SPEC_45T:
return spec_fw_name_45t;
case PCI_DEVICE_ID_SPEC_100T:
return spec_fw_name_100t;
case PCI_DEVICE_ID_SPEC_150T:
return spec_fw_name_150t;
default:
return NULL;
}
}
/**
* Load FPGA code
* @spec: SPEC device
* @name: FPGA bitstream file name
*
* Return: 0 on success, otherwise a negative error number
*/
static int spec_fw_load(struct spec_dev *spec, const char *name)
{
pr_info("%s:%d %s\n", __func__, __LINE__, name);
return compat_spec_fw_load(spec, name);
}
/**
* Return: True if the FPGA is programmed, otherwise false
*/
static bool spec_fw_is_pre_programmed(struct spec_dev *spec)
{
return false;
}
/**
* Load default FPGA code
* @spec: SPEC device
*
* Return: 0 on success, otherwise a negative error number
*/
static int spec_fw_load_init(struct spec_dev *spec)
{
if (spec_fw_is_pre_programmed(spec))
return 0;
return spec_fw_load(spec, spec_fw_name_init_get(spec));
}
static ssize_t fpga_load_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
int err;
err = spec_fw_load(to_spec_dev(dev), buf);
return err ? err : count;
}
static DEVICE_ATTR_WO(fpga_load);
static struct attribute *spec_attrs[] = {
&dev_attr_fpga_load.attr,
NULL,
};
static struct attribute_group spec_attr_group = {
.attrs = spec_attrs,
};
static const struct attribute_group *spec_attr_groups[] = {
&spec_attr_group,
NULL,
};
static void spec_release(struct device *dev)
{
}
static int spec_uevent(struct device *dev, struct kobj_uevent_env *env)
{
return 0;
}
static const struct device_type spec_dev_type = {
.name = "spec",
.release = spec_release,
.groups = spec_attr_groups,
.uevent = spec_uevent,
};
static int spec_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct spec_dev *spec;
int err, i;
spec = kzalloc(sizeof(*spec), GFP_KERNEL);
if (!spec)
return -ENOMEM;
err = pci_enable_device(pdev);
if (err)
goto err_enable;
pci_set_master(pdev);
/* Remap our 3 bars */
for (i = err = 0; i < 3; i++) {
struct resource *r = pdev->resource + (2 * i);
if (!r->start)
continue;
if (r->flags & IORESOURCE_MEM) {
spec->remap[i] = ioremap(r->start,
r->end + 1 - r->start);
if (!spec->remap[i])
err = -ENOMEM;
}
}
if (err)
goto err_remap;
spec->dev.parent = &pdev->dev;
spec->dev.type = &spec_dev_type;
err = dev_set_name(&spec->dev, "spec-%s", dev_name(&pdev->dev));
if (err)
goto err_name;
err = device_register(&spec->dev);
if (err)
goto err_dev;
/* This virtual device is assciated with this driver */
spec->dev.driver = pdev->dev.driver;
err = spec_fpga_init(spec);
if (err)
goto err_fpga;
err = spec_irq_init(spec);
if (err)
goto err_irq;
err = spec_fw_load_init(spec);
if (err)
goto err_fw;
pci_set_drvdata(pdev, spec);
dev_info(spec->dev.parent, "Spec registered devptr=0x%p\n", spec->dev.parent);
return 0;
err_fw:
spec_irq_exit(spec);
err_irq:
spec_fpga_exit(spec);
err_fpga:
device_unregister(&spec->dev);
err_dev:
err_name:
for (i = 0; i < 3; i++) {
if (spec->remap[i])
iounmap(spec->remap[i]);
}
err_remap:
pci_disable_device(pdev);
err_enable:
kfree(spec);
return err;
}
static void spec_remove(struct pci_dev *pdev)
{
struct spec_dev *spec = pci_get_drvdata(pdev);
int i;
spec_irq_exit(spec);
spec_fpga_exit(spec);
for (i = 0; i < 3; i++)
if (spec->remap[i])
iounmap(spec->remap[i]);
device_unregister(&spec->dev);
pci_disable_device(pdev);
kfree(spec);
}
static const struct pci_device_id spec_pci_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_45T)},
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_100T)},
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_150T)},
{0,},
};
static struct pci_driver spec_driver = {
.driver = {
.owner = THIS_MODULE,
},
.name = "spec",
.probe = spec_probe,
.remove = spec_remove,
.id_table = spec_pci_tbl,
};
module_pci_driver(spec_driver);
MODULE_AUTHOR("Federico Vaga ");
MODULE_LICENSE("GPL v2");
MODULE_VERSION(GIT_VERSION);
MODULE_DESCRIPTION("spec driver");
ADDITIONAL_VERSIONS;
spec-v0.3.2/kernel/spec-fpga.c 0000664 0000000 0000000 00000016551 13451647003 0016140 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2017 CERN (www.cern.ch)
* Author: Federico Vaga
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include
#include
#include "spec.h"
#include "spec-compat.h"
static inline uint8_t reverse_bits8(uint8_t x)
{
x = ((x >> 1) & 0x55) | ((x & 0x55) << 1);
x = ((x >> 2) & 0x33) | ((x & 0x33) << 2);
x = ((x >> 4) & 0x0f) | ((x & 0x0f) << 4);
return x;
}
static uint32_t unaligned_bitswap_le32(const uint32_t *ptr32)
{
static uint32_t tmp32;
static uint8_t *tmp8 = (uint8_t *) &tmp32;
static uint8_t *ptr8;
ptr8 = (uint8_t *) ptr32;
*(tmp8 + 0) = reverse_bits8(*(ptr8 + 0));
*(tmp8 + 1) = reverse_bits8(*(ptr8 + 1));
*(tmp8 + 2) = reverse_bits8(*(ptr8 + 2));
*(tmp8 + 3) = reverse_bits8(*(ptr8 + 3));
return tmp32;
}
static inline void gpio_out(struct spec_dev *spec, const uint32_t addr,
const int bit, const int value)
{
uint32_t reg;
reg = gennum_readl(spec, addr);
if(value)
reg |= (1<FPGA configuration mode
* @spec: spec device instance
*/
static void gn4124_fpga_gpio_config(struct spec_dev *spec)
{
gpio_out(spec, GNGPIO_DIRECTION_MODE, GPIO_BOOTSEL0, 0);
gpio_out(spec, GNGPIO_DIRECTION_MODE, GPIO_BOOTSEL1, 0);
gpio_out(spec, GNGPIO_OUTPUT_ENABLE, GPIO_BOOTSEL0, 1);
gpio_out(spec, GNGPIO_OUTPUT_ENABLE, GPIO_BOOTSEL1, 1);
gpio_out(spec, GNGPIO_OUTPUT_VALUE, GPIO_BOOTSEL0, 1);
gpio_out(spec, GNGPIO_OUTPUT_VALUE, GPIO_BOOTSEL1, 0);
}
/**
* After programming, we fix gpio lines so pci can access the flash
* @spec: spec device instance
*/
static void gn4124_fpga_gpio_restore(struct spec_dev *spec)
{
gpio_out(spec, GNGPIO_OUTPUT_VALUE, GPIO_BOOTSEL0, 0);
gpio_out(spec, GNGPIO_OUTPUT_VALUE, GPIO_BOOTSEL1, 0);
gpio_out(spec, GNGPIO_OUTPUT_ENABLE, GPIO_BOOTSEL0, 0);
gpio_out(spec, GNGPIO_OUTPUT_ENABLE, GPIO_BOOTSEL1, 0);
}
/**
* Initialize the gennum
* @spec: spec device instance
* @last_word_size: last word size in the FPGA bitstream
*
* Return: 0 on success, otherwise a negative error code
*/
static int gn4124_fpga_fcl_init(struct spec_dev *spec, int last_word_size)
{
uint32_t ctrl;
int i;
gennum_writel(spec, 0x00, FCL_CLK_DIV);
gennum_writel(spec, 0x40, FCL_CTRL); /* Reset */
i = gennum_readl(spec, FCL_CTRL);
if (i != 0x40) {
printk(KERN_ERR "%s: %i: error\n", __func__, __LINE__);
return -EIO;
}
gennum_writel(spec, 0x00, FCL_CTRL);
gennum_writel(spec, 0x00, FCL_IRQ); /* clear pending irq */
switch(last_word_size) {
case 3: ctrl = 0x116; break;
case 2: ctrl = 0x126; break;
case 1: ctrl = 0x136; break;
case 0: ctrl = 0x106; break;
default: return -EINVAL;
}
gennum_writel(spec, ctrl, FCL_CTRL);
gennum_writel(spec, 0x00, FCL_CLK_DIV); /* again? maybe 1 or 2? */
gennum_writel(spec, 0x00, FCL_TIMER_CTRL); /* "disable FCL timr fun" */
gennum_writel(spec, 0x10, FCL_TIMER_0); /* "pulse width" */
gennum_writel(spec, 0x00, FCL_TIMER_1);
/*
* Set delay before data and clock is applied by FCL
* after SPRI_STATUS is detected being assert.
*/
gennum_writel(spec, 0x08, FCL_TIMER2_0); /* "delay before data/clk" */
gennum_writel(spec, 0x00, FCL_TIMER2_1);
gennum_writel(spec, 0x17, FCL_EN); /* "output enable" */
ctrl |= 0x01; /* "start FSM configuration" */
gennum_writel(spec, ctrl, FCL_CTRL);
return 0;
}
/**
* Wait for the FPGA to be configured and ready
* @spec: device instance
*
* Return: 0 on success,-ETIMEDOUT on failure
*/
static int gn4124_fpga_fcl_waitdone(struct spec_dev *spec)
{
unsigned long j;
uint32_t val;
j = jiffies + 2 * HZ;
while (1) {
val = gennum_readl(spec, FCL_IRQ);
/* Done */
if (val & 0x8)
return 0;
/* Fail */
if (val & 0x4)
return -EIO;
/* Timeout */
if (time_after(jiffies, j))
return -ETIMEDOUT;
udelay(100);
}
}
/**
* It configures the FPGA with the given image
* @spec: spec instance
* @data: FPGA configuration code
* @len: image length in bytes
*
* Return: 0 on success, otherwise a negative error code
*/
static int gn4124_fpga_load(struct spec_dev *spec, const void *data, int len)
{
int size32 = (len + 3) >> 2;
int done = 0, wrote = 0, i;
const uint32_t *data32 = data;
while(size32 > 0)
{
/* Check to see if FPGA configuation has error */
i = gennum_readl(spec, FCL_IRQ);
if ( (i & 8) && wrote) {
done = 1;
printk("%s: %i: done after %i\n", __func__, __LINE__,
wrote);
} else if ( (i & 0x4) && !done) {
printk("%s: %i: error after %i\n", __func__, __LINE__,
wrote);
return -EIO;
}
/* Wait until at least 1/2 of the fifo is empty */
while (gennum_readl(spec, FCL_IRQ) & (1<<5))
;
/* Write a few dwords into FIFO at a time. */
for (i = 0; size32 && i < 32; i++) {
gennum_writel(spec, unaligned_bitswap_le32(data32),
FCL_FIFO);
data32++; size32--; wrote++;
}
}
return 0;
}
/**
* It notifies the gennum that the configuration is over
* @spec: spec device instance
*/
static void gn4124_fpga_fcl_complete(struct spec_dev *spec)
{
gennum_writel(spec, 0x186, FCL_CTRL); /* "last data written" */
}
static enum fpga_mgr_states spec_fpga_state(struct fpga_manager *mgr)
{
return mgr->state;
}
int spec_fpga_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count)
{
struct spec_dev *spec = mgr->priv;
int err = 0, last_word_size;
gn4124_fpga_gpio_config(spec);
last_word_size = compat_get_fpga_last_word_size(info, count) & 0x3;
err = gn4124_fpga_fcl_init(spec, last_word_size);
if (err < 0)
goto err;
return 0;
err:
gn4124_fpga_gpio_restore(spec);
return err;
}
static int spec_fpga_write(struct fpga_manager *mgr, const char *buf, size_t count)
{
struct spec_dev *spec = mgr->priv;
return gn4124_fpga_load(spec, buf, count);
}
int spec_fpga_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info)
{
struct spec_dev *spec = mgr->priv;
int err;
gn4124_fpga_fcl_complete(spec);
err = gn4124_fpga_fcl_waitdone(spec);
if (err < 0)
return err;
gn4124_fpga_gpio_restore(spec);
gn4124_fpga_reset(spec);
return 0;
}
static void spec_fpga_remove(struct fpga_manager *mgr)
{
/* do nothing */
}
static const struct fpga_manager_ops spec_fpga_ops = {
compat_fpga_ops_initial_header_size
compat_fpga_ops_groups
.state = spec_fpga_state,
.write_init = compat_spec_fpga_write_init,
.write = spec_fpga_write,
.write_complete = compat_spec_fpga_write_complete,
.fpga_remove = spec_fpga_remove,
};
int spec_fpga_init(struct spec_dev *spec)
{
int err;
spec->mgr = compat_fpga_mgr_create(&spec->dev,
dev_name(&spec->dev),
&spec_fpga_ops, spec);
if (!spec || !spec->mgr)
return -EPERM;
err = compat_fpga_mgr_register(spec->mgr);
if (err) {
compat_fpga_mgr_free(spec->mgr);
return err;
}
return 0;
}
void spec_fpga_exit(struct spec_dev *spec)
{
if (!spec)
return;
compat_fpga_mgr_unregister(spec->mgr);
}
spec-v0.3.2/kernel/spec-irq.c 0000664 0000000 0000000 00000027614 13451647003 0016020 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2017 CERN (www.cern.ch)
* Author: Federico Vaga
*
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Driver for SPEC (Simple PCI FMC carrier) board.
*/
#include
#include
#include
#include
#include
#include
#include "spec.h"
#define CHAIN 0
#define GN4124_GPIO_IRQ_MAX 16
static int spec_use_msi = 0;
module_param_named(use_msi, spec_use_msi, int, 0444);
static int spec_test_irq = 1;
module_param_named(test_irq, spec_test_irq, int, 0444);
/**
* This bitmask describes the GPIO which can be used as interrupt lines.
* By default SPEC uses GPIO8 and GPIO9
*/
static int spec_gpio_int = 0x00000300;
static int spec_irq_dbg_info(struct seq_file *s, void *offset)
{
struct spec_dev *spec = s->private;
int i;
seq_printf(s, "'%s':\n",dev_name(spec->dev.parent));
seq_printf(s, " redirect: %d\n", to_pci_dev(spec->dev.parent)->irq);
seq_printf(s, " irq-mapping:\n");
for (i = 0; i < GN4124_GPIO_IRQ_MAX; ++i) {
seq_printf(s, " - hardware: %d\n", i);
seq_printf(s, " linux: %d\n",
irq_find_mapping(spec->gpio_domain, i));
}
return 0;
}
static int spec_irq_dbg_info_open(struct inode *inode, struct file *file)
{
struct spec_dev *spec = inode->i_private;
return single_open(file, spec_irq_dbg_info, spec);
}
static const struct file_operations spec_irq_dbg_info_ops = {
.owner = THIS_MODULE,
.open = spec_irq_dbg_info_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
/**
* It initializes the debugfs interface
* @spec: SPEC instance
*
* Return: 0 on success, otherwise a negative error number
*/
static int spec_irq_debug_init(struct spec_dev *spec)
{
spec->dbg_dir = debugfs_create_dir(dev_name(&spec->dev), NULL);
if (IS_ERR_OR_NULL(spec->dbg_dir)) {
dev_err(&spec->dev,
"Cannot create debugfs directory (%ld)\n",
PTR_ERR(spec->dbg_dir));
return PTR_ERR(spec->dbg_dir);
}
spec->dbg_info = debugfs_create_file(SPEC_DBG_INFO_NAME, 0444,
spec->dbg_dir, spec,
&spec_irq_dbg_info_ops);
if (IS_ERR_OR_NULL(spec->dbg_info)) {
dev_err(&spec->dev,
"Cannot create debugfs file \"%s\" (%ld)\n",
SPEC_DBG_INFO_NAME, PTR_ERR(spec->dbg_info));
return PTR_ERR(spec->dbg_info);
}
return 0;
}
/**
* It removes the debugfs interface
* @spec: SPEC instance
*/
static void spec_irq_debug_exit(struct spec_dev *spec)
{
debugfs_remove_recursive(spec->dbg_dir);
}
/**
* (disable)
*/
static void spec_irq_gpio_mask(struct irq_data *d)
{
struct spec_dev *spec = irq_data_get_irq_chip_data(d);
gennum_writel(spec, BIT(d->hwirq), GNGPIO_INT_MASK_SET);
}
/**
* (enable)
*/
static void spec_irq_gpio_unmask(struct irq_data *d)
{
struct spec_dev *spec = irq_data_get_irq_chip_data(d);
gennum_writel(spec, BIT(d->hwirq), GNGPIO_INT_MASK_CLR);
}
static int spec_irq_gpio_set_type(struct irq_data *d, unsigned int flow_type)
{
struct spec_dev *spec = irq_data_get_irq_chip_data(d);
int bit;
/*
* detect errors:
* - level and edge together cannot work
*/
if ((flow_type & IRQ_TYPE_LEVEL_MASK) &&
(flow_type & IRQ_TYPE_EDGE_BOTH)) {
dev_err(&spec->dev,
"Impossible to set GPIO IRQ %ld to both LEVEL and EDGE (0x%x)\n",
d->hwirq, flow_type);
return -EINVAL;
}
bit = BIT(d->hwirq);
/* Configure: level or edge (default)? */
if (flow_type & IRQ_TYPE_LEVEL_MASK) {
gennum_mask_val(spec, bit, bit, GNGPIO_INT_TYPE);
#if CHAIN
irq_set_handler(d->irq, handle_level_irq);
#endif
} else {
gennum_mask_val(spec, bit, 0, GNGPIO_INT_TYPE);
/* if we want to trigger on any edge */
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
gennum_mask_val(spec, bit, bit, GNGPIO_INT_ON_ANY);
#if CHAIN
irq_set_handler(d->irq, handle_edge_irq);
#endif
}
/* Configure: level-low or falling-edge, level-high or raising-edge (default)? */
if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
gennum_mask_val(spec, bit, 0, GNGPIO_INT_VALUE);
else
gennum_mask_val(spec, bit, bit, GNGPIO_INT_VALUE);
return IRQ_SET_MASK_OK;
}
/**
* A new IRQ interrupt has been requested
* @d IRQ related data
*
* We need to set the GPIO line to be input and disable completely any
* kind of output. We do not want any alternative function (bypass mode).
*/
static unsigned int spec_irq_gpio_startup(struct irq_data *d)
{
struct spec_dev *spec = irq_data_get_irq_chip_data(d);
unsigned int bit = BIT(d->hwirq);
gennum_mask_val(spec, bit, 0, GNGPIO_BYPASS_MODE);
gennum_mask_val(spec, bit, bit, GNGPIO_DIRECTION_MODE);
gennum_mask_val(spec, bit, 0, GNGPIO_OUTPUT_ENABLE);
/* FIXME in the original code we had this? What is it? */
/* !!(gennum_readl(spec, GNGPIO_INPUT_VALUE) & bit); */
spec_irq_gpio_unmask(d);
return 0;
}
/**
* It disables the GPIO interrupt by masking it
*/
static void spec_irq_gpio_disable(struct irq_data *d)
{
spec_irq_gpio_mask(d);
}
static struct irq_chip spec_irq_gpio_chip = {
.name = "GN4124-GPIO",
.irq_startup = spec_irq_gpio_startup,
.irq_disable = spec_irq_gpio_disable,
.irq_mask = spec_irq_gpio_mask,
.irq_unmask = spec_irq_gpio_unmask,
.irq_set_type = spec_irq_gpio_set_type,
};
/**
* Given the hardware IRQ and the Linux IRQ number (virtirq), configure the
* Linux IRQ number in order to handle properly the incoming interrupts
* on the hardware IRQ line.
*/
static int spec_irq_gpio_domain_map(struct irq_domain *h,
unsigned int virtirq,
irq_hw_number_t hwirq)
{
struct spec_dev *spec = h->host_data;
irq_set_chip_data(virtirq, spec);
irq_set_chip(virtirq, &spec_irq_gpio_chip);
/* all handlers are directly nested to our handler */
irq_set_nested_thread(virtirq, 1);
return 0;
}
static struct irq_domain_ops spec_irq_gpio_domain_ops = {
.map = spec_irq_gpio_domain_map,
};
/**
* Handle IRQ from the GPIO block
*/
static irqreturn_t spec_irq_gpio_handler(int irq, void *arg)
{
struct spec_dev *spec = arg;
unsigned int cascade_irq;
uint32_t gpio_int_status;
unsigned long loop;
irqreturn_t ret = IRQ_NONE;
int i;
gpio_int_status = gennum_readl(spec, GNGPIO_INT_STATUS);
if (!gpio_int_status)
goto out_enable_irq;
loop = gpio_int_status;
for_each_set_bit(i, &loop, GN4124_GPIO_IRQ_MAX) {
cascade_irq = irq_find_mapping(spec->gpio_domain, i);
/*
* Ok, now we execute the handler for the given IRQ. Please
* note that this is not the action requested by the device driver
* but it is the handler defined during the IRQ mapping
*/
handle_nested_irq(cascade_irq);
}
ret = IRQ_HANDLED;
out_enable_irq:
/* Re-enable the GPIO interrupts, we are done here */
gennum_mask_val(spec, GNINT_STAT_GPIO, GNINT_STAT_GPIO, GNINT_CFG(0));
return ret;
}
/**
* This will run in hard-IRQ context since we do not have much to do
*/
static irqreturn_t spec_irq_sw_handler(int irq, void *arg)
{
struct spec_dev *spec = arg;
uint32_t int_stat;
/* Ack the interrupts */
int_stat = gennum_readl(spec, GNINT_STAT);
gennum_writel(spec, 0x0000, GNINT_STAT);
complete(&spec->compl);
return IRQ_HANDLED;
}
#if CHAIN
static void spec_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
{
}
#endif
static irqreturn_t spec_irq_handler(int irq, void *arg)
{
struct spec_dev *spec = arg;
uint32_t int_stat, int_cfg;
int_cfg = gennum_readl(spec, GNINT_CFG(0));
int_stat = gennum_readl(spec, GNINT_STAT);
if (unlikely(!(int_stat & int_cfg)))
return IRQ_NONE;
if (unlikely(int_stat & GNINT_STAT_SW_ALL)) /* only for testing */
return spec_irq_sw_handler(irq, spec);
/*
* Do not listen to new interrupts while handling the current GPIOs.
* This may take a while since the chain behind each GPIO can be long.
* If the IRQ behind is level, we do not want this IRQ handeler to be
* called continuously. But on the other hand we do not want other
* devices sharing the same IRQ to wait for us; just to play safe,
* let's disable interrupts. Within the thread we will re-enable them
* when we are ready (like IRQF_ONESHOT).
*/
gennum_mask_val(spec, GNINT_STAT_GPIO, 0, GNINT_CFG(0));
return IRQ_WAKE_THREAD;
}
/**
* Configure GPIO interrupts
* @spec SPEC instance
*
* Return: 0 on success, otherwise a negative error code
*/
static int spec_irq_gpio_init(struct spec_dev *spec)
{
unsigned long loop;
int i, irq;
/* Disable eery possible GPIO interrupt */
gennum_writel(spec, 0xFFFF, GNGPIO_INT_MASK_SET);
spec->gpio_domain = irq_domain_add_linear(NULL, GN4124_GPIO_IRQ_MAX,
&spec_irq_gpio_domain_ops,
spec);
if (!spec->gpio_domain)
return -ENOMEM;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,11,0)
spec->gpio_domain->name = kasprintf(GFP_KERNEL, "%s-gn4124-gpio-irq",
dev_name(&spec->dev));
#endif
/*
* Create the mapping between HW irq and virtual IRQ number. On SPEC
* we have recuded set of GPIOs which can be used as interrupt:
* activate only these ones
*/
loop = spec_gpio_int;
for_each_set_bit(i, &loop, GN4124_GPIO_IRQ_MAX) {
irq = irq_create_mapping(spec->gpio_domain, i);
if (irq <= 0)
goto err;
}
gennum_mask_val(spec, GNINT_STAT_GPIO, GNINT_STAT_GPIO, GNINT_CFG(0));
return 0;
err:
irq_domain_remove(spec->gpio_domain);
return irq;
}
/**
* Disable GPIO IRQ
* @spec SPEC instance
*/
static void spec_irq_gpio_exit(struct spec_dev *spec)
{
gennum_mask_val(spec, GNINT_STAT_GPIO, 0, GNINT_CFG(0));
gennum_writel(spec, 0xFFFF, GNGPIO_INT_MASK_SET);
gennum_readl(spec, GNINT_STAT); /* ack any pending GPIO interrupt */
irq_domain_remove(spec->gpio_domain);
}
/**
* Configure software interrupts
* @spec SPEC instance
*
* This kind on interrupt is used only for testing purpose
*
* Return: 0 on success, otherwise a negative error code
*/
static int spec_irq_sw_init(struct spec_dev *spec)
{
gennum_mask_val(spec, GNINT_STAT_SW_ALL, GNINT_STAT_SW_ALL,
GNINT_CFG(0));
return 0;
}
/**
* Disable software IRQ
* @spec SPEC instance
*/
static void spec_irq_sw_exit(struct spec_dev *spec)
{
gennum_mask_val(spec, GNINT_STAT_SW_ALL, 0, GNINT_CFG(0));
}
static int spec_irq_sw_test(struct spec_dev *spec)
{
long ret;
if (!spec_test_irq)
return 0;
/* produce a software interrupt on SW1 and wait for its completion */
init_completion(&spec->compl);
gennum_writel(spec, 0x0008, GNINT_STAT);
ret = wait_for_completion_timeout(&spec->compl,
msecs_to_jiffies(10000));
if (ret == 0) {
gennum_writel(spec, 0x0000, GNINT_STAT); /* disable */
dev_err(&spec->dev, "Cannot receive interrupts\n");
return -EINVAL;
}
return 0;
}
/**
* Initialize interrupts
* @spec SPEC instance
*
* Return: 0 on success, otherwise a negative error number
*/
int spec_irq_init(struct spec_dev *spec)
{
int irq = to_pci_dev(spec->dev.parent)->irq;
int err;
int i;
if (!spec)
return -EINVAL;
/* disable all source of interrupts */
for (i = 0; i < 7; i++)
gennum_writel(spec, 0, GNINT_CFG(i));
err = spec_irq_gpio_init(spec);
if (err)
goto err_gpio;
err = spec_irq_sw_init(spec);
if (err)
goto err_sw;
#if CHAIN
irq_set_chained_handler(irq, spec_irq_chain_handler);
irq_set_handler_data(irq, spec);
#else
/*
* It depends on the platform and on the IRQ on which we are connecting to
* but most likely our interrupt handler will be a thread.
*/
err = request_threaded_irq(irq,
spec_irq_handler,
spec_irq_gpio_handler,
IRQF_SHARED,
dev_name(&spec->dev),
spec);
if (err) {
dev_err(&spec->dev, "Can't request IRQ %d (%d)\n", irq, err);
goto err_req;
}
#endif
spec_irq_debug_init(spec);
err = spec_irq_sw_test(spec);
if (err)
goto err_test;
return 0;
err_test:
spec_irq_debug_exit(spec);
free_irq(irq, spec);
err_req:
spec_irq_sw_exit(spec);
err_sw:
spec_irq_gpio_exit(spec);
err_gpio:
return err;
}
void spec_irq_exit(struct spec_dev *spec)
{
int i;
int irq = to_pci_dev(spec->dev.parent)->irq;
if (!spec)
return;
/* disable all source of interrupts */
for (i = 0; i < 7; i++)
gennum_writel(spec, 0, GNINT_CFG(i));
spec_irq_debug_exit(spec);
free_irq(irq, spec);
spec_irq_sw_exit(spec);
spec_irq_gpio_exit(spec);
}
spec-v0.3.2/kernel/spec.h 0000664 0000000 0000000 00000011525 13451647003 0015226 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2010-2018 CERN (www.cern.ch)
* Author: Federico Vaga
* Author: Alessandro Rubini
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef __SPEC_H__
#define __SPEC_H__
#include
#include
#include
#include
#include
#include
#include
#include
#include
#define SPEC_FMC_SLOTS 1
/* On FPGA components */
#define SPEC_I2C_MASTER_ADDR 0x0
#define SPEC_I2C_MASTER_SIZE 8
/* These must be set to choose the FPGA configuration mode */
#define GPIO_BOOTSEL0 15
#define GPIO_BOOTSEL1 14
#define PCI_VENDOR_ID_CERN (0x10DC)
#define PCI_DEVICE_ID_SPEC_45T (0x018D)
#define PCI_DEVICE_ID_SPEC_100T (0x01A2)
#define PCI_DEVICE_ID_SPEC_150T (0x01A3)
#define PCI_VENDOR_ID_GENNUM (0x1A39)
#define PCI_DEVICE_ID_GN4124 (0x0004)
#define SPEC_MINOR_MAX (64)
#define SPEC_FLAG_BITS (8)
#define SPEC_FLAG_UNLOCK BIT(0)
/* Registers for GN4124 access */
enum {
/* page 106 */
GNPPCI_MSI_CONTROL = 0x48, /* actually, 3 smaller regs */
GNPPCI_MSI_ADDRESS_LOW = 0x4c,
GNPPCI_MSI_ADDRESS_HIGH = 0x50,
GNPPCI_MSI_DATA = 0x54,
GNPCI_SYS_CFG_SYSTEM = 0x800,
/* page 130 ff */
GNINT_CTRL = 0x810,
GNINT_STAT = 0x814,
GNINT_CFG_0 = 0x820,
GNINT_CFG_1 = 0x824,
GNINT_CFG_2 = 0x828,
GNINT_CFG_3 = 0x82c,
GNINT_CFG_4 = 0x830,
GNINT_CFG_5 = 0x834,
GNINT_CFG_6 = 0x838,
GNINT_CFG_7 = 0x83c,
#define GNINT_CFG(x) (GNINT_CFG_0 + 4 * (x))
/* page 146 ff */
GNGPIO_BASE = 0xA00,
GNGPIO_BYPASS_MODE = GNGPIO_BASE,
GNGPIO_DIRECTION_MODE = GNGPIO_BASE + 0x04, /* 0 == output */
GNGPIO_OUTPUT_ENABLE = GNGPIO_BASE + 0x08,
GNGPIO_OUTPUT_VALUE = GNGPIO_BASE + 0x0C,
GNGPIO_INPUT_VALUE = GNGPIO_BASE + 0x10,
GNGPIO_INT_MASK = GNGPIO_BASE + 0x14, /* 1 == disabled */
GNGPIO_INT_MASK_CLR = GNGPIO_BASE + 0x18, /* irq enable */
GNGPIO_INT_MASK_SET = GNGPIO_BASE + 0x1C, /* irq disable */
GNGPIO_INT_STATUS = GNGPIO_BASE + 0x20,
GNGPIO_INT_TYPE = GNGPIO_BASE + 0x24, /* 1 == level */
GNGPIO_INT_VALUE = GNGPIO_BASE + 0x28, /* 1 == high/rise */
GNGPIO_INT_ON_ANY = GNGPIO_BASE + 0x2C, /* both edges */
/* page 158 ff */
FCL_BASE = 0xB00,
FCL_CTRL = FCL_BASE,
FCL_STATUS = FCL_BASE + 0x04,
FCL_IODATA_IN = FCL_BASE + 0x08,
FCL_IODATA_OUT = FCL_BASE + 0x0C,
FCL_EN = FCL_BASE + 0x10,
FCL_TIMER_0 = FCL_BASE + 0x14,
FCL_TIMER_1 = FCL_BASE + 0x18,
FCL_CLK_DIV = FCL_BASE + 0x1C,
FCL_IRQ = FCL_BASE + 0x20,
FCL_TIMER_CTRL = FCL_BASE + 0x24,
FCL_IM = FCL_BASE + 0x28,
FCL_TIMER2_0 = FCL_BASE + 0x2C,
FCL_TIMER2_1 = FCL_BASE + 0x30,
FCL_DBG_STS = FCL_BASE + 0x34,
FCL_FIFO = 0xE00,
PCI_SYS_CFG_SYSTEM = 0x800
};
#define GNINT_STAT_GPIO BIT(15)
#define GNINT_STAT_SW0 BIT(2)
#define GNINT_STAT_SW1 BIT(3)
#define GNINT_STAT_SW_ALL (GNINT_STAT_SW0 | GNINT_STAT_SW1)
/**
* struct spec_dev - SPEC instance
* It describes a SPEC device instance.
* @dev Linux device instance descriptor
* @gpio_domain: IRQ domain for GN4124 chip
* @flags collection of bit flags
* @remap ioremap of PCI bar 0, 2, 4
* @slot_info: information about FMC slot
* @i2c_pdev: platform device for I2C master
* @i2c_adapter: the I2C master device to be used
* @compl: for IRQ testing
*/
struct spec_dev {
struct device dev;
struct irq_domain *gpio_domain;
struct fpga_manager *mgr;
DECLARE_BITMAP(flags, SPEC_FLAG_BITS);
void __iomem *remap[3]; /* ioremap of bar 0, 2, 4 */
struct dentry *dbg_dir;
#define SPEC_DBG_INFO_NAME "info"
struct dentry *dbg_info;
struct completion compl;
};
static inline struct spec_dev *to_spec_dev(struct device *_dev)
{
return container_of(_dev, struct spec_dev, dev);
}
/**
* It reads a 32bit register from the gennum chip
* @spec spec device instance
* @reg gennum register offset
* Return: a 32bit value
*/
static inline uint32_t gennum_readl(struct spec_dev *spec, int reg)
{
return readl(spec->remap[2] + reg);
}
/**
* It writes a 32bit register to the gennum chip
* @spec spec device instance
* @val a 32bit valure
* @reg gennum register offset
*/
static inline void gennum_writel(struct spec_dev *spec, uint32_t val, int reg)
{
writel(val, spec->remap[2] + reg);
}
/**
* It writes a 32bit register to the gennum chip according to the given mask
* @spec spec device instance
* @mask bit mask of the bits to actually write
* @val a 32bit valure
* @reg gennum register offset
*/
static inline void gennum_mask_val(struct spec_dev *spec,
uint32_t mask, uint32_t val, int reg)
{
uint32_t v = gennum_readl(spec, reg);
v &= ~mask;
v |= val;
gennum_writel(spec, v, reg);
}
extern int spec_fpga_init(struct spec_dev *spec);
extern void spec_fpga_exit(struct spec_dev *spec);
extern int spec_irq_init(struct spec_dev *spec);
extern void spec_irq_exit(struct spec_dev *spec);
#endif /* __SPEC_H__ */