pax_global_header 0000666 0000000 0000000 00000000064 13707547500 0014522 g ustar 00root root 0000000 0000000 52 comment=f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/ 0000775 0000000 0000000 00000000000 13707547500 0020217 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/.gitignore 0000664 0000000 0000000 00000000245 13707547500 0022210 0 ustar 00root root 0000000 0000000 *.o
*.ko
*.mod.c
.*.o.cmd
.*.ko.cmd
*.mod.d
*.o.d
*.tmp
.tmp_versions
modules.order
Module.symvers
\#*
*~
GTAGS
GPATH
GRTAGS
Makefile.specific
compile_commands.json
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/.gitmodules 0000664 0000000 0000000 00000000743 13707547500 0022400 0 ustar 00root root 0000000 0000000 [submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/CHANGELOG.rst 0000664 0000000 0000000 00000005405 13707547500 0022244 0 ustar 00root root 0000000 0000000 =========
Changelog
=========
[1.4.15] 2020-06-03
===================
Added
----
- [hdl] ignore autogenerated files to build metadata (otherwise the repository
is always marked as dirty)
[1.4.14] 2020-05-28
===================
Added
-----
- [hdl] export DDMTD clock output
[1.4.13] 2020-05-12
===================
Fixed
-----
- [hdl] report correct version in spec-base metadata
[1.4.12] 2020-05-12
===================
Added
-----
- [hdl] metadata source-id automatic assignment
Changed
-----
- [sw] do not double remap memory
[1.4.11] 2020-05-04
===================
Added
-----
- [sw] added DMA engine channel for application to the list of resources
Changed
-----
- [sw] little code improvements
[1.4.10] 2020-04-24
===================
Changed
-------
- [bld] assign dependencies path based on REPO_PARENT
- [bld] check for missing dependencies
Fixed
-----
- [sw] fix kernel crash when programming new bitstream
[1.4.9] 2020-03-10
==================
Added
-----
- [sw] support for kernel version more recent than 3.10 (RedHat)
Fixed
-----
- [sw] reduce allocation on stack
[1.4.8] 2020-02-12
==================
Fixed
-----
- [sw] fix kernel crash when programming new bitstream
[1.4.7] 2020-01-15
==================
Fixed
-------
- [doc] sysfs paths were wrong
- [doc] incomplete driver loading list of commands
[1.4.6] 2020-01-13
==================
Changed
-------
- [doc] improve documentation
- [sw] better error reporting on I2C errors
[1.4.5] 2019-12-17
==================
Something happened while synchronizing different branches and version 1.4.4
could be inconsistent on different repositories. This release increment realign
all repositories
[1.4.4] 2019-12-17
==================
Changed
-----
- [sw] better integration in coht, rename environment variable to FPGA_MGR
Fixed
-----
- [sw] suggested fixed reported by checkpatch and coccicheck
- [hdl] restore lost references to git submodules
[1.4.3] - 2019-10-17
====================
Fixed
-----
- [sw] fix SPEC GPIO get_direction
[1.4.2] - 2019-10-15
====================
Fixed
-----
- [sw] fix SPEC driver dependency with I2C OCores
[1.4.1] - 2019-09-23
====================
Changed
-------
- [sw] do not used devm_* operations (it seems to solve problems)
Removed
-------
- [sw] Removed IRQ line assignment to FCL (not used)
Fixed
-----
- [sw] kcalloc usage
- [sw] memcpy(), memset() usage
- [sw] checkpatch style fixes
[1.4.0] 2019-09-11
==================
Added
-----
- [hdl] spec-base IP-core to support SPEC based designs
- [sw] Driver for GN4124 FCL using Linux FPGA manager
- [sw] Driver for GN4124 GPIO using Linux GPIOlib
- [sw] Driver for gn412x-core DMA using Linux DMA engine
- [sw] Support for spec-base IP-core
- [sw] Support for FMC
[0.0.0]
=======
Start the development of a new SPEC driver and SPEC HDL support layer
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/LICENSES/ 0000775 0000000 0000000 00000000000 13707547500 0021424 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/LICENSES/GPL-2.0.txt 0000664 0000000 0000000 00000043215 13707547500 0023111 0 ustar 00root root 0000000 0000000 GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
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GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
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END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
spec-fmc-carrier
Copyright (C) 2019 CERN (https://home.cern)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
{signature of Ty Coon}, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/Manifest.py 0000664 0000000 0000000 00000000157 13707547500 0022342 0 ustar 00root root 0000000 0000000 modules = { "local" : [ "hdl/rtl" ] }
if action == "synthesis":
modules["local"].append("hdl/syn/common")
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/README.rst 0000664 0000000 0000000 00000000332 13707547500 0021704 0 ustar 00root root 0000000 0000000 ==============================
Simple PCIe FMC Carrier - SPEC
==============================
This git repository contains the HDL code necessary to enable most of
the SPEC features and the correspondent Linux driver.
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/distribution/ 0000775 0000000 0000000 00000000000 13707547500 0022736 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/distribution/.gitignore 0000664 0000000 0000000 00000000007 13707547500 0024723 0 ustar 00root root 0000000 0000000 build
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/distribution/Makefile 0000664 0000000 0000000 00000002772 13707547500 0024406 0 ustar 00root root 0000000 0000000 TOP_DIR ?= $(shell pwd)/../
HDL_DIR ?= $(TOP_DIR)/hdl
DRIVER_NAME := spec-fmc-carrier
VERSION := $(shell git describe --abbrev=0)
DIR_NAME := $(DRIVER_NAME)-$(VERSION)
KEEP_TEMP ?= n
BUILD ?= $(abspath build)
BUILD_DKMS := $(BUILD)/dkms
BUILD_DKMSSOURCE := $(BUILD_DKMS)/source
BUILD_DKMSTREE := $(BUILD_DKMS)/tree
DKMS_OPT := --dkmstree $(BUILD_DKMSTREE) -m $(DRIVER_NAME)/$(VERSION)
all: kernel
CHEBY ?= /usr/bin/cheby
spec-core-fpga.h:
$(CHEBY) --gen-c -i $(HDL_DIR)/rtl/spec_base_regs.cheby > /tmp/$@
kernel: dkms-tar dkms-rpm
dkms-tree:
@mkdir -p $(BUILD_DKMSSOURCE)
@mkdir -p $(BUILD_DKMSTREE)
dkms-src: dkms-tree spec-core-fpga.h
$(eval $@_src := $(shell git ls-tree -r --name-only HEAD $(TOP_DIR) | grep "kernel" | tr '\n' ' '))
$(eval $@_dir := $(BUILD_DKMSSOURCE)/$(DRIVER_NAME)-$(VERSION))
@mkdir -p $($@_dir)/platform_data
@mv /tmp/spec-core-fpga.h $($@_dir)
@cp -a $($@_src) $(TOP_DIR)/distribution/dkms.conf $($@_dir)
@mv $($@_dir)/gn412x-gpio.h $($@_dir)/platform_data
@cp -a $(TOP_DIR)/LICENSES/GPL-2.0.txt $($@_dir)/LICENSE
@sed -r -i -e "s/^VERSION\s=\s.*/VERSION = $(VERSION)/" $($@_dir)/Makefile
@sed -r -i -e "s/@PKGNAME@/$(DRIVER_NAME)/" $($@_dir)/dkms.conf
@sed -r -i -e "s/@PKGVER@/$(VERSION)/" $($@_dir)/dkms.conf
dkms-add: dkms-src
@dkms add $(DKMS_OPT) --sourcetree $(BUILD_DKMSSOURCE)
dkms-tar: dkms-add
@dkms mktarball $(DKMS_OPT) --source-only
dkms-rpm: dkms-add
@dkms mkrpm $(DKMS_OPT) --source-only
clean:
@rm -rf $(BUILD)
.PHONY: dkmstree dkms-add kernel-dkms-tar
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/distribution/dkms.conf 0000664 0000000 0000000 00000001372 13707547500 0024546 0 ustar 00root root 0000000 0000000 PACKAGE_NAME="@PKGNAME@"
PACKAGE_VERSION="@PKGVER@"
CLEAN="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 clean"
MAKE[0]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
MAKE[1]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
MAKE[2]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
MAKE[3]="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 all"
BUILT_MODULE_NAME[0]="@PKGNAME@"
BUILT_MODULE_NAME[1]="gn412x-gpio"
BUILT_MODULE_NAME[2]="gn412x-fcl"
BUILT_MODULE_NAME[3]="spec-gn412x-dma"
DEST_MODULE_LOCATION[0]="/updates"
DEST_MODULE_LOCATION[1]="/updates"
DEST_MODULE_LOCATION[2]="/updates"
DEST_MODULE_LOCATION[3]="/updates"
BUILD_DEPENDS[0]="fmc"
BUILD_DEPENDS[1]="fpga_mgr"
BUILD_DEPENDS[2]="i2c-ocores"
AUTOINSTALL="yes"
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/doc/ 0000775 0000000 0000000 00000000000 13707547500 0020764 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/doc/.gitignore 0000664 0000000 0000000 00000000010 13707547500 0022743 0 ustar 00root root 0000000 0000000 _build/
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/doc/Makefile 0000664 0000000 0000000 00000001104 13707547500 0022420 0 ustar 00root root 0000000 0000000 # Minimal makefile for Sphinx documentation
#
# You can set these variables from the command line.
SPHINXOPTS =
SPHINXBUILD = sphinx-build
SOURCEDIR = .
BUILDDIR = _build
# Put it first so that "make" without argument is like "make help".
help:
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: help Makefile
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/doc/conf.py 0000664 0000000 0000000 00000013025 13707547500 0022264 0 ustar 00root root 0000000 0000000 # -*- coding: utf-8 -*-
#
# Configuration file for the Sphinx documentation builder.
#
# This file does only contain a selection of the most common options. For a
# full list see the documentation:
# http://www.sphinx-doc.org/en/master/config
# -- Path setup --------------------------------------------------------------
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
#
import os
import sys
sys.path.insert(0, os.path.abspath('../software/PySPEC/PySPEC'))
# -- Project information -----------------------------------------------------
project = 'SPEC'
copyright = '2019-2020, Federico Vaga , Tristan Gingold , Dimitris Lampridis '
author = 'Federico Vaga , Tristan Gingold , Dimitris Lampridis '
# The short X.Y version
version = '1.4'
# The full version, including alpha/beta/rc tags
release = 'v1.4'
# -- General configuration ---------------------------------------------------
# If your documentation needs a minimal Sphinx version, state it here.
#
# needs_sphinx = '1.0'
# Add any Sphinx extension module names here, as strings. They can be
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
extensions = [
'sphinx.ext.autodoc'
]
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
# The suffix(es) of source filenames.
# You can specify multiple suffix as a list of string:
#
# source_suffix = ['.rst', '.md']
source_suffix = '.rst'
# The master toctree document.
master_doc = 'index'
# The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages.
#
# This is also used if you do content translation via gettext catalogs.
# Usually you set "language" from the command line for these cases.
language = None
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
# This pattern also affects html_static_path and html_extra_path.
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
# The name of the Pygments (syntax highlighting) style to use.
pygments_style = None
# -- Options for HTML output -------------------------------------------------
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#
html_theme = 'alabaster'
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the
# documentation.
#
# html_theme_options = {}
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
html_static_path = ['_static']
# Custom sidebar templates, must be a dictionary that maps document names
# to template names.
#
# The default sidebars (for documents that don't match any pattern) are
# defined by theme itself. Builtin themes are using these templates by
# default: ``['localtoc.html', 'relations.html', 'sourcelink.html',
# 'searchbox.html']``.
#
# html_sidebars = {}
# -- Options for HTMLHelp output ---------------------------------------------
# Output file base name for HTML help builder.
htmlhelp_basename = 'SPECdoc'
# -- Options for LaTeX output ------------------------------------------------
latex_elements = {
# The paper size ('letterpaper' or 'a4paper').
#
# 'papersize': 'letterpaper',
# The font size ('10pt', '11pt' or '12pt').
#
# 'pointsize': '10pt',
# Additional stuff for the LaTeX preamble.
#
# 'preamble': '',
# Latex figure (float) alignment
#
# 'figure_align': 'htbp',
}
# Grouping the document tree into LaTeX files. List of tuples
# (source start file, target name, title,
# author, documentclass [howto, manual, or own class]).
latex_documents = [
(master_doc, 'SPEC.tex', 'SPEC Documentation',
'Federico Vaga \\textless{}federico.vaga@cern.ch\\textgreater{}, Tristan Gingold \\textless{}tristan.gingold@cern.ch\\textgreater{}, Dimitris Lampridis \\textless{}dimitrios.lampridis@cern.ch\\textgreater{}', 'manual'),
]
# -- Options for manual page output ------------------------------------------
# One entry per manual page. List of tuples
# (source start file, name, description, authors, manual section).
man_pages = [
(master_doc, 'spec', 'SPEC Documentation',
[author], 1)
]
# -- Options for Texinfo output ----------------------------------------------
# Grouping the document tree into Texinfo files. List of tuples
# (source start file, target name, title, author,
# dir menu entry, description, category)
texinfo_documents = [
(master_doc, 'SPEC', 'SPEC Documentation',
author, 'SPEC', 'One line description of project.',
'Miscellaneous'),
]
# -- Options for Epub output -------------------------------------------------
# Bibliographic Dublin Core info.
epub_title = project
# The unique identifier of the text. This can be a ISBN number
# or the project homepage.
#
# epub_identifier = ''
# A unique identification for the text.
#
# epub_uid = ''
# A list of files that should not be packed into the epub file.
epub_exclude_files = ['search.html']
autodoc_default_options = {
'member-order': 'bysource',
}
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/doc/hdl-spec-base.rst 0000664 0000000 0000000 00000011550 13707547500 0024127 0 ustar 00root root 0000000 0000000 ..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2019-2020 CERN
.. _spec_hdl_spec_base:
SPEC Base HDL Component
=======================
The ``SPEC base`` HDL component provides the basic support for the SPEC card
and it is strongly recommended for any SPEC based design, even though it
is not mandatory. This component groups together a set of ip-cores which
are required to drive hardware chips and FPGA ip-cores that are handy to
develop SPEC based designs.
The ``SPEC base`` is compliant with the `FPGA device identification`_ rules.
Components
----------
The following table summarizes the ``SPEC base`` components and after that
you have a brief description of each of them. We do not expect to add or
remove components in the future so this should be an exhaustive list.
=================== ============ ========== =============
Component Start End Cap. Mask Bit
CSR 0x00000040 0x0000005F (Mandatory)
Therm. & ID 0x00000070 0x0000007F 1
Gen-Core I2C Ocore 0x00000080 0x0000009F (Mandatory)
Gen-Core SPI Ocore 0x000000A0 0x000000BF 2
DMA for DDR 0x000000C0 0x000000FF 5
Gen-Core VIC 0x00000100 0x000001FF 0
Build info 0x00000200 0x000002FF 4
White-Rabbit 0x00001000 0x00001FFF 3
=================== ============ ========== =============
.. note::
The *Capability Mask Bit* (Cap. Mask Bit) refers to the bit in the
capability mask described in the `FPGA device identification`_
rules.
CSR
Control and Status register for the ``SPEC base`` device.
Therm. & ID
A onewire interface from `general cores`_ that accesses the SPEC
thermometer to get temperature and serial number.
General Cores I2C OpenCore
An I2C controller from `general cores`_ which bus is wired to the FMC
connector to access the I2C EEPROM on the FMC module.
General Cores SPI OpenCore
An SPI controller from `general cores`_ which bus is wired to the SPI
flash memory on which we store FPGA configurations.
DMA for DDR
A DMA engine from `GN4124 core`_.
General Cores VIC
An interrupt controller from `general cores`_ that routes FPGA
interrupts to PCIe bridge (``GPIO 8`` on the GN4124 chip). The interrupt
lines from 0 to 5 are reserved for internal use as described in the
following table. All other lines are available for users.
============== ===================
Interrupt Line Component
0 Gen-Core I2C Ocore
1 Gen-Core SPI Ocore
2 DMA for DDR - DONE
3 (reserved)
4 (reserved)
5 (reserved)
============== ===================
Build Info
Free format information (ASCII) about the FPGA synthesis.
White-Rabbit
The `White-Rabbit core`_.
.. note::
If the `White-Rabbit core`_ is instantiated then the components
*Therm. & ID* and *General Cores SPI OpenCore* get disabled because
they are incompatible. This because the `White-Rabbit core`_ needs
the OneWire bus and the SPI bus for internal use, therefore those
resources can't be used.
Usage
-----
The ``SPEC base`` component is in ``hdl/rtl/spec_base_wr.vhd`` and
examples of its usage are available in ``hdl/top/``.
Remember that the Linux driver expects the ``SPEC base`` at offset
``0x00000000``.
Meta-Data ROM
-------------
Fixed Part
~~~~~~~~~~
========== ========== ================== ============
Offset Size (bit) Name Default (LE)
0x00000000 32 Vendor ID 0x000010DC
0x00000004 32 Device ID 0x53504543
0x00000008 32 Version
0x0000000C 32 Byte Order Mark 0xFFFE0000
0x00000010 128 Source ID
0x00000020 32 Capability Mask
0x00000030 128 Vendor UUID 0x00000000
========== ========== ================== ============
Version 1.4
~~~~~~~~~~~
========== ========== ================== ============
Offset Size (bit) Name Default (LE)
0x00000000 32 Vendor ID 0x000010DC
0x00000004 32 Device ID 0x53504543
0x00000008 32 Version 0x0104xxxx
0x0000000C 32 Byte Order Mark 0xFFFE0000
0x00000010 128 Source ID
0x00000020 32 Capability Mask 0x0000000x
0x00000030 128 Vendor UUID 0x00000000
========== ========== ================== ============
.. _`SPEC project`: https://ohwr.org/project/spec
.. _`FPGA device identification`: https://www.ohwr.org/project/fpga-dev-id/
.. _`general cores`: https://www.ohwr.org/projects/general-cores
.. _`GN4124 core`: https://www.ohwr.org/project/gn4124-core/
.. _`White-Rabbit core`: https://ohwr.org/project/wr-cores
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/doc/index.rst 0000664 0000000 0000000 00000001715 13707547500 0022631 0 ustar 00root root 0000000 0000000 ..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2019-2020 CERN
================================
Welcome to SPEC's documentation!
================================
The Simple PCIe FMC Carrier (SPEC) is a 4 lane PCIe card that has an
FPGA and can hold one FMC module and one SFP connector.
Its bridge to the PCIe bus is the Gennum GN4124 chip and its purpose
is to create a bridge between the PCIe bus and the FPGA. With the
exception of the M25P32 FLASH memory, all components are connected to
the FPGA. This implies that an FPGA configuration is necessary to
fully use the card.
The `SPEC project`_ is hosted on the `Open HardWare Repository`_
You can clone the GIT project with the following command::
git clone https://ohwr.org/project/spec.git
.. toctree::
:maxdepth: 2
:caption: Contents:
hdl-spec-base
sw-driver
sw-python
.. _`Open HardWare Repository`: https://ohwr.org/
.. _`SPEC project`: https://ohwr.org/project/spec
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/doc/sw-driver.rst 0000664 0000000 0000000 00000025443 13707547500 0023450 0 ustar 00root root 0000000 0000000 ..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2019-2020 CERN
.. _spec_driver:
SPEC Driver(s)
==============
Driver(s) Structure
-------------------
There are drivers for the GN4124 chip and there are drivers for the
:ref:`SPEC base` component.
.. _spec_fmc_carrier:
SPEC FMC Carrier
This is the driver that wrap up all the physical components and the
:ref:`SPEC base` ones. It configures the card so
that all components cooperate correctly.
The driver for the GN4124 chip are always present and distributed as
part of the SPEC driver. They must work no matter what FPGA design has
been loaded on FPGA.
.. _gn4124_gpio:
GN4124 GPIO
This driver provides support for the GN4124 GPIOs. It uses the standard
Linux `GPIO interface`_ and it export a dedicated IRQ domain.
.. _gn4124_fcl:
GN4124 FCL
This driver provides support for the GN4124 FCL (FPGA Configuration Loader).
It uses the `FPGA manager interface`_ to program the FPGA at run-time.
If the SPEC based application is using the :ref:`SPEC
base` component then it can profit from the
following driver. They are not all mandatory, it depends on the
application, and most of them are distributed separately:
.. _gn4124_fpga_dma:
SPEC GN412x DMA
This driver provides for DMA transfers to/from the SPEC DDR. It uses
the standard Linux `DMA Engine`_. It is part of the `SPEC project`_
.. _i2c_ocore:
I2C OCORE
This is the driver for the I2C OCORE IP-core. It is used to communicate with
the standard FMC EEPROM available what on FMC modules. The driver is
available in Linux but also (as a backport) in `general cores`_.
.. _spi_ocore:
SPI OCORE
This is the driver for the SPI OCORE IP-core. It is used to communicate with
the M25P32 FLASH memory where FPGA bitstreams are stored. The driver is
distributed separately in `general cores`_.
.. _vic:
VIC
The driver for the VIC interrupt controller IP-core. The driver is
distributed separately in `general cores`_.
.. _`OHWR`: https://ohwr.org
.. _`SPEC project`: https://ohwr.org/project/spec
.. _`FMC`: https://www.ohwr.org/projects/fmc-sw
.. _`GPIO interface`: https://www.kernel.org/doc/html/latest/driver-api/gpio/index.html
.. _`FPGA manager interface`: https://www.kernel.org/doc/html/latest/driver-api/fpga/index.html
.. _`DMA Engine`: https://www.kernel.org/doc/html/latest/driver-api/dmaengine/index.html
.. _`general cores`: https://www.ohwr.org/projects/general-cores
Drivers(s) Build and Install
----------------------------
From the project top level directory, you can find the driver(s) source files
under ``software/kernel``.
The SPEC software uses plain ``Makefile`` to build drivers. Therefore, you can
build the driver by executing ``make``. To successfully build the SPEC driver
you need to install the `cheby`_ tool that will generate on fly part of the
code for the :ref:`SPEC base`. If you do not want to
install `cheby`_ you can define the path to it with the environment
variable ``CHEBY``. Following an example on how to build the driver(s).::
# define CHEBY only if it is not installed
export CHEBY=/path/to/cheby/proto/cheby.py
cd /path/to/spec/
make -C software/kernel modules
make -C software/kernel modules_install
This will build and install 4 drivers:
- :ref:`spec-fmc-carrier.ko`,
- :ref:`gn412x-gpio.ko`,
- :ref:`gn412x-fcl.ko`,
- :ref:`spec-gn412x-dma.ko `.
::
find software -name "*.ko"
software/kernel/gn412x-fcl.ko
software/kernel/gn412x-gpio.ko
software/kernel/spec-fmc-carrier.ko
software/kernel/spec-gn412x-dma.ko
Please note that this will not install all soft dependencies which are
distributed separately (:ref:`I2C OpenCore`,
:ref:`SPI OpenCore`, :ref:`HT Vector Interrupt Controller`,
`FMC`_).
.. _`cheby`: https://gitlab.cern.ch/cohtdrivers/cheby
Driver(s) Loading
-----------------
When the card is plugged and the driver(s) installed, the Linux kernel will
load automatically all necessary drivers.
If you need to manually install/remove the driver and its dependencies, you
can use `modprobe(8)`_.::
sudo modprobe spec-fmc-carrier
If you did not install the drivers you can use `insmod(8)`_ and `rmmod(8)`_.
In this case is useful to know what drivers to load (dependencies) and their
(un)loading order.::
# typically part of the distribution
modprobe at24
modprobe mtd
modprobe m25p80
# from OHWR
insmod /path/to/fmc-sw/drivers/fmc/fmc.ko
insmod /path/to/general-cores/software/htvic/drivers/htvic.ko
insmod /path/to/general-cores/software/i2c-ocores/drivers/i2c/busses/i2c-ocores.ko
insmod /path/to/general-cores/software/spi-ocores/drivers/spi/spi-ocores.ko
insmod /path/to/spec/software/kernel/gn412x-fcl.ko
insmod /path/to/spec/software/kernel/gn412x-gpio.ko
insmod /path/to/spec/software/kernel/spec-gn412x-dma.ko
# Actually the order above does not really matter, what matters
# it is that spec-fmc-carrier.ko is loaded as last
insmod /path/to/spec/software/kernel/spec-fmc-carrier.ko
.. _`modprobe(8)`: https://linux.die.net/man/8/modprobe
.. _`insmod(8)`: https://linux.die.net/man/8/insmod
.. _`rmmod(8)`: https://linux.die.net/man/8/rmmod
Attributes From *sysfs*
-----------------------
In addition to standard *sysfs* attributes for PCI, `DMA Engine`_,
`FPGA manager`_, `GPIO`_, and `FMC`_ there more SPEC specific *sysfs*
attributes. Here we focus only on those.
At PCI device top-level we can see the `DMA Engine`_ interface and the
GN412x sub-devices for :ref:`GPIO` and :ref:`FCL`.
Still at the PCI device top-level there is the directory ``fpga-options``
that contains additional attributes to control the FPGA.
``fpga-options/bootselect`` [R/W]
It selects (returns) the FPGA access mode. Possible values are:
- fpga-flash: (default) the FPGA has access to the SPI flash, it uses it
to load the pre-programmed FPGA configuration;
- gn4124-fpga: the FPGA is accessible from the PCI bridge, it is used to
dynamically load an FPGA configuration;
- gn4124-flash: the SPI flash is accessible form the PCI bridge, it is used
to load an FPGA configuration on the SPI flash
``fpga-options/load_golden_fpga`` [W]
It loads the SPEC golden FPGA (if installed). Just write '1' to this file.
If the FPGA is correctly programmed (an FPGA configuration that uses the
:ref:`SPEC base`) then there will be a directory named
``spec-`` that contains the reference to all FPGA sub-devices and the
following *sysfs* attributes.
``spec-/application_offset`` [R]
It shows the relative offset (from FPGA base address - resource0) to the
user application loaded.
``spec-/pcb_rev`` [R]
It shows the SPEC carrier PCB revision number.
``spec-/reset_app`` [R/W]
It puts in *reset* (1) or *unreset* (0) the user application.
.. _`GPIO`: https://www.kernel.org/doc/html/latest/driver-api/gpio/index.html
.. _`FPGA manager`: https://www.kernel.org/doc/html/latest/driver-api/fpga/index.html
Attributes From *debugfs*
-------------------------
In addition to standard *debugfs* attributes for PCI, `DMA Engine`_,
`FPGA manager`_, `GPIO`_, and `FMC`_ there more SPEC specific *debugfs*
attributes. Here we focus only on those.
``gn412x-gpio..auto/regs`` [R]
It dumps the GN412X registers controlling the GPIO module.
``gn412x-fcl..auto/regs`` [R]
It dumps the GN412X registers controlling the FCL module.
``spec-gn412x-dma..auto/regs`` [R]
It dumps the GN412X DMA FPGA registers controlling the DMA ip-core.
``/fpga_device_metadata`` [R]
It dumps the FPGA device metadata information for the
:ref:`SPEC base` and, when it exists, the user
application one.
``/info`` [R]
Miscellaneous information about the card status: IRQ mapping.
``/fpga_firmware`` [W]
It configures the FPGA with a bitstream which name is provided as input.
Remember that firmwares are installed in ``/lib/firmware`` and alternatively
you can provide your own path by setting it in
``/sys/module/firmware_class/parameters/path``.
``/spec-/csr_regs`` [R]
It dumps the Control/Status register for
the :ref:`SPEC base`
``/spec-/build_info`` [R]
It shows the FPGA configuration synthesis information
``/spec-/dma`` [RW]
It exports DMA capabilities to user-space. The user can ``open(2)``
and ``close(2)`` to request and release a DMA engine channel. Then,
the user can use ``lseek(2)`` to set the offset in the DDR, and
``read(2)``/``write(2)`` to start the DMA transfer.
Module Parameters
-----------------
``user_dma_coherent_size`` [RW]
It sets the maximum size for a coherent DMA memory allocation. A
change to this value is applied on ``open(2)``
(file ``/spec-/dma``).
``user_dma_max_segment`` [RW]
It sets the maximum size for a DMA transfer in a scatterlist. A
change to this value is applied on the next ``read(2)`` or ``write(2)``
(file ``/spec-/dma``).
DMA
---
On SPEC-Based designs the DMA engine is implemented in HDL. This means
that you can't perform a DMA transfer without a *spec-base* device
on the FPGA.
The SPEC driver(s) implements the dmaengine API for the HDL DMA
engine. To request a dmaengine channel the user must provide a filter
function. The SPEC driver assigns to the application driver a
IORESOURCE_DMA which value is ``dma_device->dev_id << 16 |
channel_number``. Therefore, the user can use the following filter
function.::
static bool filter_function(struct dma_chan *dchan, void *arg)
{
struct dma_device *ddev = dchan->device;
int dev_id = (*((int *)arg) >> 16) & 0xFFFF;
int chan_id = *((int *)arg) & 0xFFFF;
return ddev->dev_id == dev_id && dchan->chan_id == chan_id;
}
void function(void)
{
struct resource *r;
int dma_dev_id;
dma_cap_mask_t dma_mask;
/* ... */
r = platform_get_resource(pdev, IORESOURCE_DMA, TDC_DMA);
dma_dev_id = r->start;
dma_cap_zero(dma_mask);
dma_cap_set(DMA_SLAVE, dma_mask);
dma_cap_set(DMA_PRIVATE, dma_mask);
dchan = dma_request_channel(dma_mask, filter_function,
dma_dev_id);
/* ... */
}
You can get the maximum transfer size by calling ``dma_get_max_seg_size()``.::
dma_get_max_seg_size(dchan->device->dev);
.. warning::
The GN4124 chip has a 4KiB payload. When doing a ``DMA_DEV_TO_MEM``
the HDL DMA engine splits transfers in 4KiB chunks, but for
``DMA_MEM_TO_DEV`` transfers the split should happen in the
driver: it does not happen. The DMA engine implementation
supports ``DMA_MEM_TO_DEV`` manly for testing purposes; to avoid
complications in the driver the 4KiB split is left to users.
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/doc/sw-python.rst 0000664 0000000 0000000 00000000272 13707547500 0023467 0 ustar 00root root 0000000 0000000 ..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2019-2020 CERN
.. _spec_python:
SPEC Python: PySPEC
===================
.. autoclass:: PySPEC.PySPEC
:members:
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/ 0000775 0000000 0000000 00000000000 13707547500 0020766 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/ip_cores/ 0000775 0000000 0000000 00000000000 13707547500 0022571 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/ip_cores/ddr3-sp6-core/ 0000775 0000000 0000000 00000000000 13707547500 0025061 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/ip_cores/general-cores/ 0000775 0000000 0000000 00000000000 13707547500 0025317 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/ip_cores/gn4124-core/ 0000775 0000000 0000000 00000000000 13707547500 0024436 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/ip_cores/wr-cores/ 0000775 0000000 0000000 00000000000 13707547500 0024332 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/rtl/ 0000775 0000000 0000000 00000000000 13707547500 0021567 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/rtl/.gitignore 0000664 0000000 0000000 00000000033 13707547500 0023553 0 ustar 00root root 0000000 0000000 sourceid_spec_base_pkg.vhd
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/rtl/Manifest.py 0000664 0000000 0000000 00000001232 13707547500 0023705 0 ustar 00root root 0000000 0000000 files = [
"spec_base_regs.vhd",
"spec_base_wr.vhd",
"sourceid_spec_base_pkg.vhd",
]
try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open("../../../" + "general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'spec_base'})
except Exception as e:
try:
# Otherwise look for the local submodule of general-cores
exec(open("../ip_cores/" + "general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'spec_base'})
except Exception as e:
print("Error: cannot generate source id file")
raise
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/rtl/spec_base_regs.cheby 0000664 0000000 0000000 00000005457 13707547500 0025562 0 ustar 00root root 0000000 0000000 memory-map:
name: spec_base_regs
bus: wb-32-be
size: 0x2000
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
size: 0x40
interface: sram
- block:
name: csr
description: carrier and fmc status and control
address: 0x40
children:
- reg:
name: app_offset
description: offset to the application metadata
access: ro
width: 32
- reg:
name: resets
description: global and application resets
access: rw
width: 32
children:
- field:
name: global
range: 0
- field:
name: appl
range: 1
- reg:
name: fmc_presence
description: presence lines for the fmcs
access: ro
width: 32
- reg:
name: gn4124_status
description: status of gennum
access: ro
width: 32
# field 0: pll locked.
- reg:
name: ddr_status
description: status of the ddr3 controller
access: ro
width: 32
children:
- field:
description: Set when calibration is done.
name: calib_done
range: 0
- reg:
name: pcb_rev
description: pcb revision
access: ro
width: 32
children:
- field:
name: rev
range: 3-0
- submap:
name: therm_id
description: Thermometer and unique id
address: 0x70
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: fmc_i2c
description: i2c controllers to the fmcs
address: 0x80
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: flash_spi
description: spi controller to the flash
address: 0xa0
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: dma
description: dma registers for the gennum core
address: 0xc0
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: vic
description: vector interrupt controller
address: 0x100
size: 0x100
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: buildinfo
description: a ROM containing build information
size: 0x100
interface: sram
- submap:
name: wrc_regs
address: 0x1000
description: white-rabbit core registers
size: 0x1000
interface: wb-32-be
x-hdl:
busgroup: True
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/rtl/spec_base_regs.vhd 0000664 0000000 0000000 00000051660 13707547500 0025246 0 ustar 00root root 0000000 0000000 -- Do not edit; this file was generated by Cheby using these options:
-- --gen-hdl=spec_base_regs.vhd -i spec_base_regs.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_base_regs is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_adr_i : in std_logic_vector(12 downto 2);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_dat_i : in std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(31 downto 0);
-- a ROM containing the carrier metadata
metadata_addr_o : out std_logic_vector(5 downto 2);
metadata_data_i : in std_logic_vector(31 downto 0);
metadata_data_o : out std_logic_vector(31 downto 0);
metadata_wr_o : out std_logic;
-- offset to the application metadata
csr_app_offset_i : in std_logic_vector(31 downto 0);
csr_resets_global_o : out std_logic;
csr_resets_appl_o : out std_logic;
-- presence lines for the fmcs
csr_fmc_presence_i : in std_logic_vector(31 downto 0);
-- status of gennum
csr_gn4124_status_i : in std_logic_vector(31 downto 0);
-- Set when calibration is done.
csr_ddr_status_calib_done_i : in std_logic;
csr_pcb_rev_rev_i : in std_logic_vector(3 downto 0);
-- Thermometer and unique id
therm_id_i : in t_wishbone_master_in;
therm_id_o : out t_wishbone_master_out;
-- i2c controllers to the fmcs
fmc_i2c_i : in t_wishbone_master_in;
fmc_i2c_o : out t_wishbone_master_out;
-- spi controller to the flash
flash_spi_i : in t_wishbone_master_in;
flash_spi_o : out t_wishbone_master_out;
-- dma registers for the gennum core
dma_i : in t_wishbone_master_in;
dma_o : out t_wishbone_master_out;
-- vector interrupt controller
vic_i : in t_wishbone_master_in;
vic_o : out t_wishbone_master_out;
-- a ROM containing build information
buildinfo_addr_o : out std_logic_vector(7 downto 2);
buildinfo_data_i : in std_logic_vector(31 downto 0);
buildinfo_data_o : out std_logic_vector(31 downto 0);
buildinfo_wr_o : out std_logic;
-- white-rabbit core registers
wrc_regs_i : in t_wishbone_master_in;
wrc_regs_o : out t_wishbone_master_out
);
end spec_base_regs;
architecture syn of spec_base_regs is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_rack : std_logic;
signal metadata_re : std_logic;
signal csr_resets_global_reg : std_logic;
signal csr_resets_appl_reg : std_logic;
signal therm_id_re : std_logic;
signal therm_id_wt : std_logic;
signal therm_id_rt : std_logic;
signal therm_id_tr : std_logic;
signal therm_id_wack : std_logic;
signal therm_id_rack : std_logic;
signal fmc_i2c_re : std_logic;
signal fmc_i2c_wt : std_logic;
signal fmc_i2c_rt : std_logic;
signal fmc_i2c_tr : std_logic;
signal fmc_i2c_wack : std_logic;
signal fmc_i2c_rack : std_logic;
signal flash_spi_re : std_logic;
signal flash_spi_wt : std_logic;
signal flash_spi_rt : std_logic;
signal flash_spi_tr : std_logic;
signal flash_spi_wack : std_logic;
signal flash_spi_rack : std_logic;
signal dma_re : std_logic;
signal dma_wt : std_logic;
signal dma_rt : std_logic;
signal dma_tr : std_logic;
signal dma_wack : std_logic;
signal dma_rack : std_logic;
signal vic_re : std_logic;
signal vic_wt : std_logic;
signal vic_rt : std_logic;
signal vic_tr : std_logic;
signal vic_wack : std_logic;
signal vic_rack : std_logic;
signal buildinfo_rack : std_logic;
signal buildinfo_re : std_logic;
signal wrc_regs_re : std_logic;
signal wrc_regs_wt : std_logic;
signal wrc_regs_rt : std_logic;
signal wrc_regs_tr : std_logic;
signal wrc_regs_wack : std_logic;
signal wrc_regs_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_cyc_i and wb_stb_i;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_we_i)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_we_i) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_we_i)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_we_i) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_ack_o <= ack_int;
wb_stall_o <= not ack_int and wb_en;
wb_rty_o <= '0';
wb_err_o <= '0';
-- Assign outputs
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rack <= '0';
else
metadata_rack <= metadata_re and not metadata_rack;
end if;
end if;
end process;
metadata_data_o <= wb_dat_i;
metadata_addr_o <= wb_adr_i(5 downto 2);
csr_resets_global_o <= csr_resets_global_reg;
csr_resets_appl_o <= csr_resets_appl_reg;
-- Assignments for submap therm_id
therm_id_tr <= therm_id_wt or therm_id_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
therm_id_rt <= '0';
else
therm_id_rt <= (therm_id_rt or therm_id_re) and not therm_id_rack;
end if;
end if;
end process;
therm_id_o.cyc <= therm_id_tr;
therm_id_o.stb <= therm_id_tr;
therm_id_wack <= therm_id_i.ack and therm_id_wt;
therm_id_rack <= therm_id_i.ack and therm_id_rt;
therm_id_o.adr <= ((27 downto 0 => '0') & wb_adr_i(3 downto 2)) & (1 downto 0 => '0');
therm_id_o.sel <= (others => '1');
therm_id_o.we <= therm_id_wt;
therm_id_o.dat <= wb_dat_i;
-- Assignments for submap fmc_i2c
fmc_i2c_tr <= fmc_i2c_wt or fmc_i2c_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_i2c_rt <= '0';
else
fmc_i2c_rt <= (fmc_i2c_rt or fmc_i2c_re) and not fmc_i2c_rack;
end if;
end if;
end process;
fmc_i2c_o.cyc <= fmc_i2c_tr;
fmc_i2c_o.stb <= fmc_i2c_tr;
fmc_i2c_wack <= fmc_i2c_i.ack and fmc_i2c_wt;
fmc_i2c_rack <= fmc_i2c_i.ack and fmc_i2c_rt;
fmc_i2c_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
fmc_i2c_o.sel <= (others => '1');
fmc_i2c_o.we <= fmc_i2c_wt;
fmc_i2c_o.dat <= wb_dat_i;
-- Assignments for submap flash_spi
flash_spi_tr <= flash_spi_wt or flash_spi_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
flash_spi_rt <= '0';
else
flash_spi_rt <= (flash_spi_rt or flash_spi_re) and not flash_spi_rack;
end if;
end if;
end process;
flash_spi_o.cyc <= flash_spi_tr;
flash_spi_o.stb <= flash_spi_tr;
flash_spi_wack <= flash_spi_i.ack and flash_spi_wt;
flash_spi_rack <= flash_spi_i.ack and flash_spi_rt;
flash_spi_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
flash_spi_o.sel <= (others => '1');
flash_spi_o.we <= flash_spi_wt;
flash_spi_o.dat <= wb_dat_i;
-- Assignments for submap dma
dma_tr <= dma_wt or dma_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dma_rt <= '0';
else
dma_rt <= (dma_rt or dma_re) and not dma_rack;
end if;
end if;
end process;
dma_o.cyc <= dma_tr;
dma_o.stb <= dma_tr;
dma_wack <= dma_i.ack and dma_wt;
dma_rack <= dma_i.ack and dma_rt;
dma_o.adr <= ((25 downto 0 => '0') & wb_adr_i(5 downto 2)) & (1 downto 0 => '0');
dma_o.sel <= (others => '1');
dma_o.we <= dma_wt;
dma_o.dat <= wb_dat_i;
-- Assignments for submap vic
vic_tr <= vic_wt or vic_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
vic_rt <= '0';
else
vic_rt <= (vic_rt or vic_re) and not vic_rack;
end if;
end if;
end process;
vic_o.cyc <= vic_tr;
vic_o.stb <= vic_tr;
vic_wack <= vic_i.ack and vic_wt;
vic_rack <= vic_i.ack and vic_rt;
vic_o.adr <= ((23 downto 0 => '0') & wb_adr_i(7 downto 2)) & (1 downto 0 => '0');
vic_o.sel <= (others => '1');
vic_o.we <= vic_wt;
vic_o.dat <= wb_dat_i;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
buildinfo_rack <= '0';
else
buildinfo_rack <= buildinfo_re and not buildinfo_rack;
end if;
end if;
end process;
buildinfo_data_o <= wb_dat_i;
buildinfo_addr_o <= wb_adr_i(7 downto 2);
-- Assignments for submap wrc_regs
wrc_regs_tr <= wrc_regs_wt or wrc_regs_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wrc_regs_rt <= '0';
else
wrc_regs_rt <= (wrc_regs_rt or wrc_regs_re) and not wrc_regs_rack;
end if;
end if;
end process;
wrc_regs_o.cyc <= wrc_regs_tr;
wrc_regs_o.stb <= wrc_regs_tr;
wrc_regs_wack <= wrc_regs_i.ack and wrc_regs_wt;
wrc_regs_rack <= wrc_regs_i.ack and wrc_regs_rt;
wrc_regs_o.adr <= ((19 downto 0 => '0') & wb_adr_i(11 downto 2)) & (1 downto 0 => '0');
wrc_regs_o.sel <= (others => '1');
wrc_regs_o.we <= wrc_regs_wt;
wrc_regs_o.dat <= wb_dat_i;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
metadata_wr_o <= '0';
csr_resets_global_reg <= '0';
csr_resets_appl_reg <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
dma_wt <= '0';
vic_wt <= '0';
buildinfo_wr_o <= '0';
wrc_regs_wt <= '0';
else
wr_ack_int <= '0';
metadata_wr_o <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
dma_wt <= '0';
vic_wt <= '0';
buildinfo_wr_o <= '0';
wrc_regs_wt <= '0';
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
-- Submap metadata
metadata_wr_o <= wr_int;
wr_ack_int <= wr_int;
when "01" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- Register csr_app_offset
when "01" =>
-- Register csr_resets
if wr_int = '1' then
csr_resets_global_reg <= wb_dat_i(0);
csr_resets_appl_reg <= wb_dat_i(1);
end if;
wr_ack_int <= wr_int;
when "10" =>
-- Register csr_fmc_presence
when "11" =>
-- Register csr_gn4124_status
when others =>
wr_ack_int <= wr_int;
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- Register csr_ddr_status
when "01" =>
-- Register csr_pcb_rev
when others =>
wr_ack_int <= wr_int;
end case;
when "11" =>
-- Submap therm_id
therm_id_wt <= (therm_id_wt or wr_int) and not therm_id_wack;
wr_ack_int <= therm_id_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
-- Submap fmc_i2c
fmc_i2c_wt <= (fmc_i2c_wt or wr_int) and not fmc_i2c_wack;
wr_ack_int <= fmc_i2c_wack;
when "1" =>
-- Submap flash_spi
flash_spi_wt <= (flash_spi_wt or wr_int) and not flash_spi_wack;
wr_ack_int <= flash_spi_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "11" =>
-- Submap dma
dma_wt <= (dma_wt or wr_int) and not dma_wack;
wr_ack_int <= dma_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "0001" =>
-- Submap vic
vic_wt <= (vic_wt or wr_int) and not vic_wack;
wr_ack_int <= vic_wack;
when "0010" =>
-- Submap buildinfo
buildinfo_wr_o <= wr_int;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
when "1" =>
-- Submap wrc_regs
wrc_regs_wt <= (wrc_regs_wt or wr_int) and not wrc_regs_wack;
wr_ack_int <= wrc_regs_wack;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
when "01" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_app_offset
reg_rdat_int <= csr_app_offset_i;
rd_ack1_int <= rd_int;
when "01" =>
-- csr_resets
reg_rdat_int(0) <= csr_resets_global_reg;
reg_rdat_int(1) <= csr_resets_appl_reg;
rd_ack1_int <= rd_int;
when "10" =>
-- csr_fmc_presence
reg_rdat_int <= csr_fmc_presence_i;
rd_ack1_int <= rd_int;
when "11" =>
-- csr_gn4124_status
reg_rdat_int <= csr_gn4124_status_i;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_ddr_status
reg_rdat_int(0) <= csr_ddr_status_calib_done_i;
rd_ack1_int <= rd_int;
when "01" =>
-- csr_pcb_rev
reg_rdat_int(3 downto 0) <= csr_pcb_rev_rev_i;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "11" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
when "1" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "11" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "0001" =>
when "0010" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "1" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
end process;
-- Process for read requests.
process (wb_adr_i, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_data_i, metadata_rack, rd_int, therm_id_i.dat, therm_id_rack, therm_id_rt, rd_int, fmc_i2c_i.dat, fmc_i2c_rack, fmc_i2c_rt, rd_int, flash_spi_i.dat, flash_spi_rack, flash_spi_rt, rd_int, dma_i.dat, dma_rack, dma_rt, rd_int, vic_i.dat, vic_rack, vic_rt, rd_int, buildinfo_data_i, buildinfo_rack, rd_int, wrc_regs_i.dat, wrc_regs_rack, wrc_regs_rt) begin
-- By default ack read requests
wb_dat_o <= (others => '0');
metadata_re <= '0';
therm_id_re <= '0';
fmc_i2c_re <= '0';
flash_spi_re <= '0';
dma_re <= '0';
vic_re <= '0';
buildinfo_re <= '0';
wrc_regs_re <= '0';
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
-- Submap metadata
wb_dat_o <= metadata_data_i;
rd_ack_int <= metadata_rack;
metadata_re <= rd_int;
when "01" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_app_offset
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- csr_resets
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "10" =>
-- csr_fmc_presence
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "11" =>
-- csr_gn4124_status
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_ddr_status
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- csr_pcb_rev
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "11" =>
-- Submap therm_id
therm_id_re <= rd_int;
wb_dat_o <= therm_id_i.dat;
rd_ack_int <= therm_id_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
-- Submap fmc_i2c
fmc_i2c_re <= rd_int;
wb_dat_o <= fmc_i2c_i.dat;
rd_ack_int <= fmc_i2c_rack;
when "1" =>
-- Submap flash_spi
flash_spi_re <= rd_int;
wb_dat_o <= flash_spi_i.dat;
rd_ack_int <= flash_spi_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "11" =>
-- Submap dma
dma_re <= rd_int;
wb_dat_o <= dma_i.dat;
rd_ack_int <= dma_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "0001" =>
-- Submap vic
vic_re <= rd_int;
wb_dat_o <= vic_i.dat;
rd_ack_int <= vic_rack;
when "0010" =>
-- Submap buildinfo
wb_dat_o <= buildinfo_data_i;
rd_ack_int <= buildinfo_rack;
buildinfo_re <= rd_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "1" =>
-- Submap wrc_regs
wrc_regs_re <= rd_int;
wb_dat_o <= wrc_regs_i.dat;
rd_ack_int <= wrc_regs_rack;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/rtl/spec_base_wr.vhd 0000664 0000000 0000000 00000122062 13707547500 0024731 0 ustar 00root root 0000000 0000000 --------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_base_wr
--
-- description: SPEC carrier base.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.ddr3_ctrl_pkg.all;
use work.gn4124_core_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
use work.buildinfo_pkg.all;
use work.wr_fabric_pkg.all;
use work.streamers_pkg.all;
use work.sourceid_spec_base_pkg;
library unisim;
use unisim.vcomponents.all;
entity spec_base_wr is
generic (
-- If true, instantiate a VIC/ONEWIRE/SPI/WR/DDRAM+DMA.
g_WITH_VIC : boolean := True;
g_WITH_ONEWIRE : boolean := True;
g_WITH_SPI : boolean := True;
g_WITH_WR : boolean := True;
g_WITH_DDR : boolean := True;
-- Size of the DDR data port in bits (32 or 64)
g_DDR_DATA_SIZE : natural := 64;
-- Address of the application meta-data. 0 if none.
g_APP_OFFSET : std_logic_vector(31 downto 0) := x"0000_0000";
-- Number of user interrupts
g_NUM_USER_IRQ : natural := 1;
-- WR PTP firmware.
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Number of aux clocks syntonized by WRPC to WR timebase
g_AUX_CLKS : integer := 0;
-- Fabric interface selection for WR Core:
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_FABRIC_IFACE : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_STREAMERS_OP_MODE : t_streamers_op_mode := TX_AND_RX;
g_TX_STREAMER_PARAMS : t_tx_streamer_params := c_TX_STREAMER_PARAMS_DEFAUT;
g_RX_STREAMER_PARAMS : t_rx_streamer_params := c_RX_STREAMER_PARAMS_DEFAUT;
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := False;
-- Increase information messages during simulation
g_VERBOSE : boolean := False;
g_SIM_BYPASS_GENNUM : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- 125 MHz PLL reference
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
-- 20MHz VCXO clock (for WR)
clk_20m_vcxo_i : in std_logic := '0';
-- 125 MHz GTP reference
clk_125m_gtp_n_i : in std_logic := '0';
clk_125m_gtp_p_i : in std_logic := '0';
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_AUX_CLKS-1 downto 0) := (others => '0');
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- Presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Miscellanous SPEC pins
---------------------------------------------------------------------------
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '0';
sfp_mod_def0_i : in std_logic := '0'; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
------------------------------------------
-- DDR (bank 3)
------------------------------------------
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic;
------------------------------------------
-- User part
------------------------------------------
-- Direct access to the DDR-3
-- Classic wishbone
ddr_dma_clk_i : in std_logic := '0';
ddr_dma_rst_n_i : in std_logic := '0';
ddr_dma_wb_cyc_i : in std_logic := '0';
ddr_dma_wb_stb_i : in std_logic := '0';
ddr_dma_wb_adr_i : in std_logic_vector(31 downto 0) := (others => '0');
ddr_dma_wb_sel_i : in std_logic_vector((g_DDR_DATA_SIZE / 8) - 1 downto 0) := (others => '0');
ddr_dma_wb_we_i : in std_logic := '0';
ddr_dma_wb_dat_i : in std_logic_vector(g_DDR_DATA_SIZE - 1 downto 0) := (others => '0');
ddr_dma_wb_ack_o : out std_logic;
ddr_dma_wb_stall_o : out std_logic;
ddr_dma_wb_dat_o : out std_logic_vector(g_DDR_DATA_SIZE - 1 downto 0);
-- DDR FIFO empty flag
ddr_wr_fifo_empty_o : out std_logic;
-- Clocks and reset.
clk_dmtd_125m_o : out std_logic;
clk_62m5_sys_o : out std_logic;
rst_62m5_sys_n_o : out std_logic;
clk_125m_ref_o : out std_logic;
rst_125m_ref_n_o : out std_logic;
-- Interrupts
irq_user_i : in std_logic_vector(g_NUM_USER_IRQ + 5 downto 6) := (others => '0');
-- WR fabric interface (when g_fabric_iface = "plain")
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_DUMMY_SRC_IN;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_DUMMY_SNK_IN;
-- WR streamers (when g_fabric_iface = "streamers")
wrs_tx_data_i : in std_logic_vector(g_TX_STREAMER_PARAMS.DATA_WIDTH-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_TX_STREAMER_CFG_DEFAULT;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_RX_STREAMER_CFG_DEFAULT;
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
-- Timecode I/F
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
-- Aux clocks control
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_AUX_CLKS-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_AUX_CLKS-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_AUX_CLKS-1 downto 0);
-- PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic;
-- The wishbone bus from the gennum/host to the application
-- Addresses 0-0x1fff are not available (used by the carrier).
-- This is a pipelined wishbone with byte granularity.
app_wb_o : out t_wishbone_master_out;
app_wb_i : in t_wishbone_master_in;
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out
);
end entity spec_base_wr;
architecture top of spec_base_wr is
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
signal clk_62m5_sys : std_logic; -- 62.5Mhz
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
-- DDR
signal clk_333m_ddr : std_logic;
signal rst_333m_ddr_n : std_logic := '0';
signal ddr_rst : std_logic := '1';
signal ddr_status : std_logic_vector(31 downto 0);
signal ddr_calib_done : std_logic;
-- GN4124 core DMA port to DDR wishbone bus
signal gn_wb_ddr_in : t_wishbone_master_in;
signal gn_wb_ddr_out : t_wishbone_master_out;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
-- The wishbone bus to the carrier part.
signal carrier_wb_out : t_wishbone_slave_out;
signal carrier_wb_in : t_wishbone_slave_in;
signal gennum_status : std_logic_vector(31 downto 0);
signal metadata_addr : std_logic_vector(5 downto 2);
signal metadata_data : std_logic_vector(31 downto 0);
signal buildinfo_addr : std_logic_vector(7 downto 2);
signal buildinfo_data : std_logic_vector(31 downto 0);
signal therm_id_in : t_wishbone_master_in;
signal therm_id_out : t_wishbone_master_out;
-- i2c controllers to the fmcs
signal fmc_i2c_in : t_wishbone_master_in;
signal fmc_i2c_out : t_wishbone_master_out;
-- dma registers for the gennum core
signal dma_in : t_wishbone_master_in;
signal dma_out : t_wishbone_master_out;
-- spi controller to the flash
signal flash_spi_in : t_wishbone_master_in;
signal flash_spi_out : t_wishbone_master_out;
-- vector interrupt controller
signal vic_in : t_wishbone_master_in;
signal vic_out : t_wishbone_master_out;
-- white-rabbit core
signal wrc_in : t_wishbone_master_in;
signal wrc_out : t_wishbone_master_out;
signal wrc_out_sh : t_wishbone_master_out;
signal csr_rst_gbl : std_logic;
signal csr_rst_app : std_logic;
signal rst_csr_app_n : std_logic;
signal rst_csr_app_sync_n : std_logic;
signal rst_gbl_n : std_logic;
signal fmc0_scl_out, fmc0_sda_out : std_logic;
signal fmc0_scl_oen, fmc0_sda_oen : std_logic;
signal fmc_presence : std_logic_vector(31 downto 0);
signal irq_master : std_logic;
constant num_interrupts : natural := 6 + g_NUM_USER_IRQ;
signal irqs : std_logic_vector(num_interrupts - 1 downto 0);
-- clock and reset
signal rst_62m5_sys_n : std_logic;
signal rst_125m_ref_n : std_logic;
signal clk_125m_ref : std_logic;
signal clk_10m_ext : std_logic;
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
signal eeprom_sda_out : std_logic;
signal eeprom_scl_in : std_logic;
signal eeprom_scl_out : std_logic;
-- SFP
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- LEDs and GPIO
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
attribute keep : string;
attribute keep of clk_62m5_sys : signal is "TRUE";
attribute keep of clk_125m_ref : signal is "TRUE";
attribute keep of clk_333m_ddr : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE";
begin -- architecture top
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
gn_gpio_b(1) <= 'Z';
gen_with_gennum : if g_SIMULATION = false or g_sim_bypass_gennum = false generate
cmp_gn4124_core : entity work.xwb_gn4124_core
generic map (
g_WITH_DMA => g_WITH_DDR,
g_WBM_TO_WB_FIFO_SIZE => 16,
g_WBM_TO_WB_FIFO_FULL_THRES => 12,
g_WBM_FROM_WB_FIFO_SIZE => 16,
g_WBM_FROM_WB_FIFO_FULL_THRES => 12
)
port map (
---------------------------------------------------------
-- Control and status
rst_n_a_i => gn_rst_n_i,
status_o => gennum_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
-- P2L Control
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
vc_rdy_i => gn_vc_rdy_i,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => gn_l2p_clk_p_o,
l2p_clk_n_o => gn_l2p_clk_n_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
-- L2P Control
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
---------------------------------------------------------
-- Interrupt interface
-- Note: the dma_irq are synchronized with the wb_master_clk clock
-- inside the gn4124 core.
dma_irq_o => irqs(2),
-- Note: this is a simple assignment.
irq_p_i => irq_master,
irq_p_o => gn_gpio_b(0),
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
wb_dma_cfg_clk_i => clk_62m5_sys,
wb_dma_cfg_rst_n_i => rst_62m5_sys_n,
wb_dma_cfg_i => dma_out,
wb_dma_cfg_o => dma_in,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
wb_master_clk_i => clk_62m5_sys,
wb_master_rst_n_i => rst_62m5_sys_n,
wb_master_o => gn_wb_out,
wb_master_i => gn_wb_in,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
wb_dma_dat_clk_i => clk_125m_ref,
wb_dma_dat_rst_n_i => rst_125m_ref_n,
wb_dma_dat_o => gn_wb_ddr_out,
wb_dma_dat_i => gn_wb_ddr_in
);
end generate gen_with_gennum;
gen_without_gennum: if g_SIMULATION = true and g_sim_bypass_gennum = true generate
gn_wb_out <= sim_wb_i;
sim_wb_o <= gn_wb_in;
end generate gen_without_gennum;
-- Mini-crossbar from gennum to carrier and application bus.
inst_split: entity work.xwb_split
generic map (
g_mask => x"ffff_e000"
)
port map (
clk_sys_i => clk_62m5_sys,
rst_n_i => rst_62m5_sys_n,
slave_i => gn_wb_out,
slave_o => gn_wb_in,
master_i (0) => carrier_wb_out,
master_i (1) => app_wb_i,
master_o (0) => carrier_wb_in,
master_o (1) => app_wb_o
);
inst_devs: entity work.spec_base_regs
port map (
rst_n_i => rst_62m5_sys_n,
clk_i => clk_62m5_sys,
wb_cyc_i => carrier_wb_in.cyc,
wb_stb_i => carrier_wb_in.stb,
wb_adr_i => carrier_wb_in.adr (12 downto 2), -- Bytes address from gennum
wb_sel_i => carrier_wb_in.sel,
wb_we_i => carrier_wb_in.we,
wb_dat_i => carrier_wb_in.dat,
wb_ack_o => carrier_wb_out.ack,
wb_err_o => carrier_wb_out.err,
wb_rty_o => carrier_wb_out.rty,
wb_stall_o => carrier_wb_out.stall,
wb_dat_o => carrier_wb_out.dat,
-- a ROM containing the carrier metadata
metadata_addr_o => metadata_addr,
metadata_data_i => metadata_data,
metadata_data_o => open,
-- offset to the application metadata
csr_app_offset_i => g_APP_OFFSET,
csr_resets_global_o => csr_rst_gbl,
csr_resets_appl_o => csr_rst_app,
-- presence lines for the fmcs
csr_fmc_presence_i => fmc_presence,
csr_gn4124_status_i => gennum_status,
csr_ddr_status_calib_done_i => ddr_calib_done,
csr_pcb_rev_rev_i => pcbrev_i,
-- Thermometer and unique id
therm_id_i => therm_id_in,
therm_id_o => therm_id_out,
-- i2c controllers to the fmcs
fmc_i2c_i => fmc_i2c_in,
fmc_i2c_o => fmc_i2c_out,
-- dma registers for the gennum core
dma_i => dma_in,
dma_o => dma_out,
-- spi controller to the flash
flash_spi_i => flash_spi_in,
flash_spi_o => flash_spi_out,
-- vector interrupt controller
vic_i => vic_in,
vic_o => vic_out,
-- a ROM containing build info
buildinfo_addr_o => buildinfo_addr,
buildinfo_data_i => buildinfo_data,
buildinfo_data_o => open,
-- white-rabbit core
wrc_regs_i => wrc_in,
wrc_regs_o => wrc_out
);
fmc_presence (0) <= not fmc0_prsnt_m2c_n_i;
fmc_presence (31 downto 1) <= (others => '0');
-- Metadata
p_metadata: process (clk_62m5_sys) is
begin
if rising_edge(clk_62m5_sys) then
case metadata_addr is
when x"0" =>
-- Vendor ID
metadata_data <= x"000010dc";
when x"1" =>
-- Device ID
metadata_data <= x"53504543";
when x"2" =>
-- Version
metadata_data <= x"0104000d";
when x"3" =>
-- BOM
metadata_data <= x"fffe0000";
when x"4" =>
-- source id
metadata_data <= sourceid_spec_base_pkg.sourceid(127 downto 96);
when x"5" =>
-- source id
metadata_data <= sourceid_spec_base_pkg.sourceid(95 downto 64);
when x"6" =>
-- source id
metadata_data <= sourceid_spec_base_pkg.sourceid(63 downto 32);
when x"7" =>
-- source id
metadata_data <= sourceid_spec_base_pkg.sourceid(31 downto 0);
when x"8" =>
-- capability mask
metadata_data <= x"00000000";
if g_WITH_VIC then
metadata_data(0) <= '1';
end if;
if g_WITH_ONEWIRE and not g_WITH_WR then
metadata_data(1) <= '1';
end if;
if g_WITH_SPI and not g_WITH_WR then
metadata_data(2) <= '1';
end if;
if g_WITH_WR then
metadata_data(3) <= '1';
end if;
-- Buildinfo
metadata_data(4) <= '1';
if g_WITH_DDR then
metadata_data(5) <= '1';
end if;
when others =>
metadata_data <= x"00000000";
end case;
end if;
end process;
-- Build information
p_buildinfo: process (clk_62m5_sys) is
variable addr : natural;
variable b : std_logic_vector(7 downto 0);
begin
if rising_edge(clk_62m5_sys) then
addr := to_integer(unsigned(buildinfo_addr)) * 4;
for i in 0 to 3 loop
if addr + i < buildinfo'length then
b := std_logic_vector(to_unsigned(character'pos(
buildinfo(buildinfo'left + addr + i)), 8));
else
b := x"00";
end if;
buildinfo_data (7 + i * 8 downto i * 8) <= b;
end loop;
end if;
end process;
rst_gbl_n <= rst_62m5_sys_n and (not csr_rst_gbl);
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
ddr_rst <= not rst_333m_ddr_n or csr_rst_gbl;
rst_csr_app_n <= not (csr_rst_gbl or csr_rst_app);
rst_62m5_sys_n_o <= rst_62m5_sys_n and rst_csr_app_n;
clk_62m5_sys_o <= clk_62m5_sys;
inst_rst_csr_app_sync : gc_sync_ffs
port map (
clk_i => clk_125m_ref,
rst_n_i => '1',
data_i => rst_csr_app_n,
synced_o => rst_csr_app_sync_n);
rst_125m_ref_n_o <= rst_125m_ref_n and rst_csr_app_sync_n;
clk_125m_ref_o <= clk_125m_ref;
inst_i2c: entity work.xwb_i2c_master
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_interfaces => 1)
port map (
clk_sys_i => clk_62m5_sys,
rst_n_i => rst_gbl_n,
slave_i => fmc_i2c_out,
slave_o => fmc_i2c_in,
desc_o => open,
int_o => irqs(0),
scl_pad_i (0) => fmc0_scl_b,
scl_pad_o (0) => fmc0_scl_out,
scl_padoen_o (0) => fmc0_scl_oen,
sda_pad_i (0) => fmc0_sda_b,
sda_pad_o (0) => fmc0_sda_out,
sda_padoen_o (0) => fmc0_sda_oen
);
fmc0_scl_b <= fmc0_scl_out when fmc0_scl_oen = '0' else 'Z';
fmc0_sda_b <= fmc0_sda_out when fmc0_sda_oen = '0' else 'Z';
gen_user_irq: if g_NUM_USER_IRQ > 0 generate
irqs(irq_user_i'range) <= irq_user_i;
end generate gen_user_irq;
gen_vic: if g_with_vic generate
inst_vic: entity work.xwb_vic
generic map (
g_address_granularity => BYTE,
g_num_interrupts => num_interrupts,
g_FIXED_POLARITY => True,
g_POLARITY => '1'
)
port map (
clk_sys_i => clk_62m5_sys,
rst_n_i => rst_gbl_n,
slave_i => vic_out,
slave_o => vic_in,
irqs_i => irqs,
irq_master_o => irq_master
);
end generate;
gen_no_vic: if not g_with_vic generate
vic_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
irq_master <= '0';
end generate;
irqs(3) <= '0';
irqs(4) <= '0';
irqs(5) <= '0';
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master #2 (Etherbone))
-----------------------------------------------------------------------------
gen_wr: if g_WITH_WR generate
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
begin
-- Remap WR registers.
wrc_out_sh <= (cyc => wrc_out.cyc, stb => wrc_out.stb,
adr => wrc_out.adr or x"00020000",
sel => wrc_out.sel, we => wrc_out.we, dat => wrc_out.dat);
cmp_xwrc_board_spec : xwrc_board_spec
generic map (
g_simulation => boolean'pos(g_SIMULATION),
g_VERBOSE => g_VERBOSE,
g_with_external_clock_input => TRUE,
g_dpram_initf => g_DPRAM_INITF,
g_AUX_CLKS => g_AUX_CLKS,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG,
g_STREAMERS_OP_MODE => g_STREAMERS_OP_MODE,
g_TX_STREAMER_PARAMS => g_TX_STREAMER_PARAMS,
g_RX_STREAMER_PARAMS => g_RX_STREAMER_PARAMS,
g_FABRIC_IFACE => g_FABRIC_IFACE)
port map (
areset_n_i => button1_n_i,
areset_edge_n_i => gn_rst_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_aux_i => clk_aux_i,
clk_10m_ext_i => clk_10m_ext,
clk_sys_62m5_o => clk_62m5_sys,
clk_ref_125m_o => clk_125m_ref,
clk_pll_aux_o => clk_pll_aux,
rst_sys_62m5_n_o => rst_62m5_sys_n,
rst_ref_125m_n_o => rst_125m_ref_n,
clk_dmtd_125m_o => clk_dmtd_125m_o,
rst_pll_aux_n_o => rst_pll_aux_n,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_in,
eeprom_sda_o => eeprom_sda_out,
eeprom_scl_i => eeprom_scl_in,
eeprom_scl_o => eeprom_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
-- Uart
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- SPI Flash
flash_sclk_o => spi_sclk_o,
flash_ncs_o => spi_ncs_o,
flash_mosi_o => spi_mosi_o,
flash_miso_i => spi_miso_i,
wb_slave_o => wrc_in,
wb_slave_i => wrc_out_sh,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
wrf_snk_i => wrf_snk_i,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_i,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_i,
wb_eth_master_o => wb_eth_master_o,
wb_eth_master_i => wb_eth_master_i,
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => wrc_abscal_rxts_out,
tm_link_up_o => tm_link_up_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o,
led_link_o => led_link_o,
led_act_o => led_act_o);
clk_333m_ddr <= clk_pll_aux(0);
rst_333m_ddr_n <= rst_pll_aux_n(0);
clk_10m_ext <= '0';
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- tri-state onewire access
onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= onewire_b;
-- WR means neither onewire nor spi.
assert not g_WITH_ONEWIRE report "WR is not yet compatible with ONEWIRE"
severity failure;
assert not g_WITH_SPI report "WR is not yet compatible with SPI"
severity failure;
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0',
dat => (others => '0'));
flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0',
dat => (others => '0'));
irqs(1) <= '0';
end generate;
gen_no_wr: if not g_WITH_WR generate
signal clk_125m_pllref : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_62m5 : std_logic;
signal pllout_clk_125m : std_logic;
signal pllout_clk_333m : std_logic;
signal pllout_locked : std_logic;
signal rstlogic_arst : std_logic;
begin
-- Input clock
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3, -- 333 MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_62m5,
CLKOUT1 => pllout_clk_125m,
CLKOUT2 => pllout_clk_333m,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => pllout_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_clk_62m5_buf : BUFG
port map (
O => clk_62m5_sys,
I => pllout_clk_62m5);
cmp_clk_125m_buf : BUFG
port map (
O => clk_125m_ref,
I => pllout_clk_125m);
cmp_clk_333m_buf : BUFG
port map (
O => clk_333m_ddr,
I => pllout_clk_333m);
-- logic AND of all async reset sources (active high)
rstlogic_arst <= (not pllout_locked) and (not gn_rst_n_i);
-- Clocks required to have synced resets
cmp_rstlogic_reset : gc_reset_multi_aasd
generic map (
g_CLOCKS => 3,
g_RST_LEN => 16) -- 16 clock cycles
port map (
arst_i => rstlogic_arst,
clks_i (0) => clk_62m5_sys,
clks_i (1) => clk_125m_ref,
clks_i (2) => clk_333m_ddr,
rst_n_o (0) => rst_62m5_sys_n,
rst_n_o (1) => rst_125m_ref_n,
rst_n_o (2) => rst_333m_ddr_n);
-- Not used.
wrc_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
end generate;
gen_onewire: if g_WITH_ONEWIRE and not g_WITH_WR generate
inst_onewire: entity work.xwb_ds182x_readout
generic map (
g_CLOCK_FREQ_KHZ => 62_500,
g_USE_INTERNAL_PPS => True)
port map (
clk_i => clk_62m5_sys,
rst_n_i => rst_gbl_n,
wb_i => therm_id_out,
wb_o => therm_id_in,
pps_p_i => '0',
onewire_b => onewire_b
);
end generate;
gen_no_onewire: if not g_WITH_ONEWIRE and not g_WITH_WR generate
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
onewire_b <= 'Z';
end generate;
gen_spi: if g_WITH_SPI and not g_WITH_WR generate
inst_spi: entity work.xwb_spi
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_divider_len => open,
g_max_char_len => open,
g_num_slaves => 1
)
port map (
clk_sys_i => clk_62m5_sys,
rst_n_i => rst_gbl_n,
slave_i => flash_spi_out,
slave_o => flash_spi_in,
desc_o => open,
int_o => irqs(1),
pad_cs_o(0) => spi_ncs_o,
pad_sclk_o => spi_sclk_o,
pad_mosi_o => spi_mosi_o,
pad_miso_i => spi_miso_i
);
end generate;
gen_no_spi: if not g_WITH_SPI and not g_WITH_WR generate
flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
end generate;
-- DDR3 controller
gen_with_ddr: if g_WITH_DDR generate
function get_ddr3_bank_port_select return string is
begin
case g_DDR_DATA_SIZE is
when 32 => return "SPEC_BANK3_32B_32B";
when 64 => return "SPEC_BANK3_64B_32B";
when others =>
assert false report "Invalid g_DDR_DATA_SIZE" severity error;
return "error";
end case;
end get_ddr3_bank_port_select;
begin
cmp_ddr_ctrl_bank3 : entity work.ddr3_ctrl
generic map(
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => get_ddr3_bank_port_select,
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => to_upper(boolean'image(g_SIMULATION)),
g_CALIB_SOFT_IP => to_upper(boolean'image(not g_SIMULATION)),
g_P0_MASK_SIZE => g_DDR_DATA_SIZE / 8,
g_P0_DATA_PORT_SIZE => g_DDR_DATA_SIZE,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => clk_333m_ddr,
rst_n_i => ddr_rst,
status_o => ddr_status,
ddr3_dq_b => ddr_dq_b,
ddr3_a_o => ddr_a_o,
ddr3_ba_o => ddr_ba_o,
ddr3_ras_n_o => ddr_ras_n_o,
ddr3_cas_n_o => ddr_cas_n_o,
ddr3_we_n_o => ddr_we_n_o,
ddr3_odt_o => ddr_odt_o,
ddr3_rst_n_o => ddr_reset_n_o,
ddr3_cke_o => ddr_cke_o,
ddr3_dm_o => ddr_ldm_o,
ddr3_udm_o => ddr_udm_o,
ddr3_dqs_p_b => ddr_ldqs_p_b,
ddr3_dqs_n_b => ddr_ldqs_n_b,
ddr3_udqs_p_b => ddr_udqs_p_b,
ddr3_udqs_n_b => ddr_udqs_n_b,
ddr3_clk_p_o => ddr_ck_p_o,
ddr3_clk_n_o => ddr_ck_n_o,
ddr3_rzq_b => ddr_rzq_b,
wb0_rst_n_i => ddr_dma_rst_n_i,
wb0_clk_i => ddr_dma_clk_i,
wb0_sel_i => ddr_dma_wb_sel_i,
wb0_cyc_i => ddr_dma_wb_cyc_i,
wb0_stb_i => ddr_dma_wb_stb_i,
wb0_we_i => ddr_dma_wb_we_i,
wb0_addr_i => ddr_dma_wb_adr_i,
wb0_data_i => ddr_dma_wb_dat_i,
wb0_data_o => ddr_dma_wb_dat_o,
wb0_ack_o => ddr_dma_wb_ack_o,
wb0_stall_o => ddr_dma_wb_stall_o,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty_o,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_125m_ref_n,
wb1_clk_i => clk_125m_ref,
wb1_sel_i => gn_wb_ddr_out.sel,
wb1_cyc_i => gn_wb_ddr_out.cyc,
wb1_stb_i => gn_wb_ddr_out.stb,
wb1_we_i => gn_wb_ddr_out.we,
wb1_addr_i => gn_wb_ddr_out.adr,
wb1_data_i => gn_wb_ddr_out.dat,
wb1_data_o => gn_wb_ddr_in.dat,
wb1_ack_o => gn_wb_ddr_in.ack,
wb1_stall_o => gn_wb_ddr_in.stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
ddr_calib_done <= ddr_status(0);
-- unused Wishbone signals
gn_wb_ddr_in.err <= '0';
gn_wb_ddr_in.rty <= '0';
end generate gen_with_ddr;
gen_without_ddr : if not g_WITH_DDR generate
ddr_calib_done <= '0';
gn_wb_ddr_in <= c_DUMMY_WB_MASTER_IN;
ddr_a_o <= (others => '0');
ddr_ba_o <= (others => '0');
ddr_dq_b <= (others => 'Z');
ddr_cas_n_o <= '0';
ddr_ck_p_o <= '0';
ddr_ck_n_o <= '0';
ddr_cke_o <= '0';
ddr_ldm_o <= '0';
ddr_ldqs_n_b <= 'Z';
ddr_ldqs_p_b <= 'Z';
ddr_udqs_n_b <= 'Z';
ddr_udqs_p_b <= 'Z';
ddr_odt_o <= '0';
ddr_udm_o <= '0';
ddr_ras_n_o <= '0';
ddr_reset_n_o <= '0';
ddr_we_n_o <= '0';
ddr_rzq_b <= 'Z';
ddr_dma_wb_dat_o <= (others => '0');
ddr_dma_wb_ack_o <= '1';
ddr_dma_wb_stall_o <= '0';
ddr_wr_fifo_empty_o <= '0';
end generate gen_without_ddr;
end architecture top;
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/ 0000775 0000000 0000000 00000000000 13707547500 0021577 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/common/ 0000775 0000000 0000000 00000000000 13707547500 0023067 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/common/Manifest.py 0000664 0000000 0000000 00000000552 13707547500 0025211 0 ustar 00root root 0000000 0000000 files = ["spec_base_common.ucf"]
ucf_dict = {'wr': "spec_base_wr.ucf",
'onewire': "spec_base_onewire.ucf",
'spi': "spec_base_spi.ucf",
'ddr3': "spec_base_ddr3.ucf"}
for p in spec_base_ucf:
f = ucf_dict.get(p, None)
assert f is not None, "unknown name {} in 'spec_base_ucf'".format(p)
files.append(f)
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/common/spec_base_common.ucf 0000664 0000000 0000000 00000014726 13707547500 0027074 0 ustar 00root root 0000000 0000000 #===============================================================================
# IO Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# GN4124 PCIe bridge signals
#----------------------------------------
NET "gn_rst_n_i" LOC = N20;
NET "gn_p2l_clk_n_i" LOC = M19;
NET "gn_p2l_clk_p_i" LOC = M20;
NET "gn_p2l_rdy_o" LOC = J16;
NET "gn_p2l_dframe_i" LOC = J22;
NET "gn_p2l_valid_i" LOC = L19;
NET "gn_p2l_data_i[0]" LOC = K20;
NET "gn_p2l_data_i[1]" LOC = H22;
NET "gn_p2l_data_i[2]" LOC = H21;
NET "gn_p2l_data_i[3]" LOC = L17;
NET "gn_p2l_data_i[4]" LOC = K17;
NET "gn_p2l_data_i[5]" LOC = G22;
NET "gn_p2l_data_i[6]" LOC = G20;
NET "gn_p2l_data_i[7]" LOC = K18;
NET "gn_p2l_data_i[8]" LOC = K19;
NET "gn_p2l_data_i[9]" LOC = H20;
NET "gn_p2l_data_i[10]" LOC = J19;
NET "gn_p2l_data_i[11]" LOC = E22;
NET "gn_p2l_data_i[12]" LOC = E20;
NET "gn_p2l_data_i[13]" LOC = F22;
NET "gn_p2l_data_i[14]" LOC = F21;
NET "gn_p2l_data_i[15]" LOC = H19;
NET "gn_p_wr_req_i[0]" LOC = M22;
NET "gn_p_wr_req_i[1]" LOC = M21;
NET "gn_p_wr_rdy_o[0]" LOC = L15;
NET "gn_p_wr_rdy_o[1]" LOC = K16;
NET "gn_rx_error_o" LOC = J17;
NET "gn_l2p_clk_n_o" LOC = K22;
NET "gn_l2p_clk_p_o" LOC = K21;
NET "gn_l2p_dframe_o" LOC = U22;
NET "gn_l2p_valid_o" LOC = T18;
NET "gn_l2p_edb_o" LOC = U20;
NET "gn_l2p_data_o[0]" LOC = P16;
NET "gn_l2p_data_o[1]" LOC = P21;
NET "gn_l2p_data_o[2]" LOC = P18;
NET "gn_l2p_data_o[3]" LOC = T20;
NET "gn_l2p_data_o[4]" LOC = V21;
NET "gn_l2p_data_o[5]" LOC = V19;
NET "gn_l2p_data_o[6]" LOC = W22;
NET "gn_l2p_data_o[7]" LOC = Y22;
NET "gn_l2p_data_o[8]" LOC = P22;
NET "gn_l2p_data_o[9]" LOC = R22;
NET "gn_l2p_data_o[10]" LOC = T21;
NET "gn_l2p_data_o[11]" LOC = T19;
NET "gn_l2p_data_o[12]" LOC = V22;
NET "gn_l2p_data_o[13]" LOC = V20;
NET "gn_l2p_data_o[14]" LOC = W20;
NET "gn_l2p_data_o[15]" LOC = Y21;
NET "gn_l2p_rdy_i" LOC = U19;
NET "gn_l_wr_rdy_i[0]" LOC = R20;
NET "gn_l_wr_rdy_i[1]" LOC = T22;
NET "gn_p_rd_d_rdy_i[0]" LOC = N16;
NET "gn_p_rd_d_rdy_i[1]" LOC = P19;
NET "gn_tx_error_i" LOC = M17;
NET "gn_vc_rdy_i[0]" LOC = B21;
NET "gn_vc_rdy_i[1]" LOC = B22;
NET "gn_gpio_b[0]" LOC = U16; # GPIO8
NET "gn_gpio_b[1]" LOC = AB19; # GPIO9
NET "gn_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_clk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clk_n_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_clk_p_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error_i" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_gpio_b[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Misc
#----------------------------------------
NET "button1_n_i" LOC = C22;
NET "button1_n_i" IOSTANDARD = "LVCMOS18";
NET "pcbrev_i[0]" LOC = P5;
NET "pcbrev_i[1]" LOC = P4;
NET "pcbrev_i[2]" LOC = AA2;
NET "pcbrev_i[3]" LOC = AA1;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_scl_b" LOC = F7;
NET "fmc0_sda_b" LOC = F8;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i*" TIG;
NET "fmc0_prsnt_m2c_n_i" TIG;
#===============================================================================
# Timing Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "gn_p2l_clk_p_i" TNM_NET = "gn_p2l_clk";
NET "gn_p2l_clk_n_i" TNM_NET = "gn_p2l_clk";
TIMESPEC TS_gn_p2l_clk = PERIOD "gn_p2l_clk" 5 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref";
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref";
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_pllref" 8 ns HIGH 50%;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
NET "gn_rst_n_i" TIG;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "inst_spec_base/clk_62m5_sys" TNM_NET = sys_clk;
NET "inst_spec_base/clk_125m_ref" TNM_NET = ref_clk;
NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_clk;
TIMEGRP "sys_grp" = "sys_clk" "ref_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_grp";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMESPEC TS_sys_sync_ffs = FROM sys_grp TO "sys_sync_ffs" TIG;
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_grp";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/common/spec_base_ddr3.ucf 0000664 0000000 0000000 00000010773 13707547500 0026436 0 ustar 00root root 0000000 0000000 ## DDR-3
NET "ddr_rzq_b" LOC = K7;
NET "ddr_we_n_o" LOC = H2;
NET "ddr_udqs_p_b" LOC = V2;
NET "ddr_udqs_n_b" LOC = V1;
NET "ddr_udm_o" LOC = P3;
NET "ddr_reset_n_o" LOC = E3;
NET "ddr_ras_n_o" LOC = M5;
NET "ddr_odt_o" LOC = L6;
NET "ddr_ldqs_p_b" LOC = N3;
NET "ddr_ldqs_n_b" LOC = N1;
NET "ddr_ldm_o" LOC = N4;
NET "ddr_cke_o" LOC = F2;
NET "ddr_ck_p_o" LOC = K4;
NET "ddr_ck_n_o" LOC = K3;
NET "ddr_cas_n_o" LOC = M4;
NET "ddr_dq_b[15]" LOC = Y1;
NET "ddr_dq_b[14]" LOC = Y2;
NET "ddr_dq_b[13]" LOC = W1;
NET "ddr_dq_b[12]" LOC = W3;
NET "ddr_dq_b[11]" LOC = U1;
NET "ddr_dq_b[10]" LOC = U3;
NET "ddr_dq_b[9]" LOC = T1;
NET "ddr_dq_b[8]" LOC = T2;
NET "ddr_dq_b[7]" LOC = M1;
NET "ddr_dq_b[6]" LOC = M2;
NET "ddr_dq_b[5]" LOC = L1;
NET "ddr_dq_b[4]" LOC = L3;
NET "ddr_dq_b[3]" LOC = P1;
NET "ddr_dq_b[2]" LOC = P2;
NET "ddr_dq_b[1]" LOC = R1;
NET "ddr_dq_b[0]" LOC = R3;
NET "ddr_ba_o[2]" LOC = H1;
NET "ddr_ba_o[1]" LOC = J1;
NET "ddr_ba_o[0]" LOC = J3;
NET "ddr_a_o[13]" LOC = J6;
NET "ddr_a_o[12]" LOC = F1;
NET "ddr_a_o[11]" LOC = E1;
NET "ddr_a_o[10]" LOC = J4;
NET "ddr_a_o[9]" LOC = G1;
NET "ddr_a_o[8]" LOC = G3;
NET "ddr_a_o[7]" LOC = K6;
NET "ddr_a_o[6]" LOC = L4;
NET "ddr_a_o[5]" LOC = M3;
NET "ddr_a_o[4]" LOC = H3;
NET "ddr_a_o[3]" LOC = M6;
NET "ddr_a_o[2]" LOC = K5;
NET "ddr_a_o[1]" LOC = K1;
NET "ddr_a_o[0]" LOC = K2;
# DDR IO standards and terminations
NET "ddr_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_p_b" IN_TERM = NONE;
NET "ddr_ldqs_n_b" IN_TERM = NONE;
NET "ddr_udqs_p_b" IN_TERM = NONE;
NET "ddr_udqs_n_b" IN_TERM = NONE;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "inst_spec_base/*cmp_ddr_ctrl_bank?/*/c?_pll_lock" TIG;
NET "inst_spec_base/*cmp_ddr_ctrl_bank?/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_spec_base/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
# Ignore async reset to DDR controller
NET "inst_spec_base/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "inst_spec_base/clk_333m_ddr" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
# DDR does not use any sync modules
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
#---------------------------------------
# DMA
#---------------------------------------
NET "inst_spec_base/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma.cmp_dma_controller/dma_async_*" TNM = FFS "dma_ffs";
TIMESPEC TS_dma_async_ffs = FROM dma_ffs TO pci_clk 15ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_* (3x multicycle)
NET "*/gc_sync_word_data[*]" TNM = FFS "sync_word";
TIMESPEC TS_sys_sync_word = FROM sync_word TO sys_clk 48ns DATAPATHONLY;
TIMESPEC TS_ref_sync_word = FROM sync_word TO ref_clk 24ns DATAPATHONLY;
# no gc_sync_word used in GN4124
#TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/common/spec_base_onewire.ucf 0000664 0000000 0000000 00000000377 13707547500 0027251 0 ustar 00root root 0000000 0000000 ###########################################################################
## Onewire interface -> thermometer
###########################################################################
NET "onewire_b" LOC = D4;
NET "onewire_b" IOSTANDARD = "LVCMOS25";
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/common/spec_base_spi.ucf 0000664 0000000 0000000 00000000720 13707547500 0026364 0 ustar 00root root 0000000 0000000 ###########################################################################
## Flash memory SPI interface
###########################################################################
NET "spi_ncs_o" LOC = AA3;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS25";
NET "spi_sclk_o" LOC = Y20;
NET "spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "spi_mosi_o" LOC = AB20;
NET "spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "spi_miso_i" LOC = AA20;
NET "spi_miso_i" IOSTANDARD = "LVCMOS25";
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/common/spec_base_wr.ucf 0000664 0000000 0000000 00000010352 13707547500 0026223 0 ustar 00root root 0000000 0000000 #===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "plldac_sclk_o" LOC = A4;
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" LOC = C4;
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "pll25dac_cs_n_o" LOC = A3;
NET "pll25dac_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_cs_n_o" LOC = B3;
NET "pll20dac_cs_n_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_txp_o" LOC= B16;
NET "sfp_txn_o" LOC= A16;
NET "sfp_rxp_i" LOC= D15;
NET "sfp_rxn_i" LOC= C15;
NET "sfp_mod_def0_i" LOC = G15;
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" LOC = B18;
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_los_i" LOC = D18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD="LVCMOS25";
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD="LVCMOS25";
#----------------------------------------
# SFP LEDs
#----------------------------------------
NET "led_act_o" LOC = D5;
NET "led_act_o" IOSTANDARD = "LVCMOS25";
NET "led_link_o" LOC = E5;
NET "led_link_o" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
NET "clk_125m_gtp_p_i" TNM_NET = "clk_125m_gtp";
NET "clk_125m_gtp_n_i" TNM_NET = "clk_125m_gtp";
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "inst_spec_base/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int[1]" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
#-------------------------------------------------------------
# Constrain the phase between input and sampling clock in DMTD
#-------------------------------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1.25 ns DATAPATHONLY;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "*cmp_xwrc_board_spec*cmp_dmtd_clk_pll/CLKOUT0" TNM_NET = clk_dmtd;
NET "*cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
# no gc_sync_reg for DMTD
TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
# no gc_sync_word for DMTD or PHY
TIMESPEC TS_dmtd_sync_word = FROM sync_word TO clk_dmtd 48ns DATAPATHONLY;
TIMESPEC TS_phy_sync_word = FROM sync_word TO phy_clk 24ns DATAPATHONLY;
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/dma_test/ 0000775 0000000 0000000 00000000000 13707547500 0023377 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/dma_test/.gitignore 0000664 0000000 0000000 00000000067 13707547500 0025372 0 ustar 00root root 0000000 0000000 *
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/dma_test/Manifest.py 0000664 0000000 0000000 00000001656 13707547500 0025527 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_dma_test.xise"
syn_tool = "ise"
syn_top = "spec_dma_test"
board = "spec"
spec_base_ucf = ['ddr3']
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/dma_test", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/dma_test/syn_extra_steps.tcl 0000664 0000000 0000000 00000002013 13707547500 0027331 0 ustar 00root root 0000000 0000000 # get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/full/ 0000775 0000000 0000000 00000000000 13707547500 0022541 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/full/.gitignore 0000664 0000000 0000000 00000000067 13707547500 0024534 0 ustar 00root root 0000000 0000000 *
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/full/Manifest.py 0000664 0000000 0000000 00000001672 13707547500 0024667 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_full.xise"
syn_tool = "ise"
syn_top = "spec_full"
spec_base_ucf = ['wr', 'onewire', 'spi', 'ddr3']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/full", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/full/syn_extra_steps.tcl 0000664 0000000 0000000 00000002013 13707547500 0026473 0 ustar 00root root 0000000 0000000 # get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/golden/ 0000775 0000000 0000000 00000000000 13707547500 0023047 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/golden/Manifest.py 0000664 0000000 0000000 00000001661 13707547500 0025173 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden.xise"
syn_tool = "ise"
syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/golden/syn_extra_steps.tcl 0000664 0000000 0000000 00000002013 13707547500 0027001 0 ustar 00root root 0000000 0000000 # get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/golden_wr-150T/ 0000775 0000000 0000000 00000000000 13707547500 0024206 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/golden_wr-150T/.gitignore 0000664 0000000 0000000 00000000067 13707547500 0026201 0 ustar 00root root 0000000 0000000 *
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/golden_wr-150T/Manifest.py 0000664 0000000 0000000 00000001701 13707547500 0026325 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/golden_wr-150T/syn_extra_steps.tcl 0000664 0000000 0000000 00000002013 13707547500 0030140 0 ustar 00root root 0000000 0000000 # get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/golden_wr/ 0000775 0000000 0000000 00000000000 13707547500 0023557 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/golden_wr/.gitignore 0000664 0000000 0000000 00000000067 13707547500 0025552 0 ustar 00root root 0000000 0000000 *
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/golden_wr/Manifest.py 0000664 0000000 0000000 00000001700 13707547500 0025675 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/syn/golden_wr/syn_extra_steps.tcl 0000664 0000000 0000000 00000002013 13707547500 0027511 0 ustar 00root root 0000000 0000000 # get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/testbench/ 0000775 0000000 0000000 00000000000 13707547500 0022745 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/testbench/dma_test/ 0000775 0000000 0000000 00000000000 13707547500 0024545 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/testbench/dma_test/.gitignore 0000664 0000000 0000000 00000000113 13707547500 0026530 0 ustar 00root root 0000000 0000000 Makefile
work/
transcript
vsim.wlf
NullFile
modelsim.ini
buildinfo_pkg.vhd
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/testbench/dma_test/Manifest.py 0000664 0000000 0000000 00000001671 13707547500 0026672 0 ustar 00root root 0000000 0000000 board = "spec"
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
vcom_opt = "-93 -mixedsvvh"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
include_dirs = [
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
fetchto + "/general-cores/sim/",
fetchto + "/ddr3-sp6-core/hdl/sim/",
]
files = [
"main.sv",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/dma_test",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank3_32b_32b" ]
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/testbench/dma_test/main.sv 0000664 0000000 0000000 00000020670 13707547500 0026050 0 ustar 00root root 0000000 0000000 `timescale 1ns/1ps
`include "gn4124_bfm.svh"
`define DMA_BASE 'h00c0
`define VIC_BASE 'h0100
module main;
reg rst_n = 0;
reg clk_125m_pllref = 0;
reg clk_20m_vcxo = 0;
initial begin
repeat(20) @(posedge clk_125m_pllref);
rst_n = 1;
end
IGN4124PCIMaster i_gn4124 ();
wire ddr_cas_n, ddr_ck_p, ddr_ck_n, ddr_cke;
wire [1:0] ddr_dm, ddr_dqs_p, ddr_dqs_n;
wire ddr_odt, ddr_ras_n, ddr_reset_n, ddr_we_n;
wire [15:0] ddr_dq;
wire [13:0] ddr_a;
wire [2:0] ddr_ba;
wire ddr_rzq;
pulldown(ddr_rzq);
// 125Mhz
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
spec_dma_test
#(
.g_SIMULATION(1)
)
DUT
(
.button1_n_i (rst_n),
.clk_125m_pllref_p_i (clk_125m_pllref),
.clk_125m_pllref_n_i (~clk_125m_pllref),
.gn_rst_n_i (i_gn4124.rst_n),
.gn_p2l_clk_n_i (i_gn4124.p2l_clk_n),
.gn_p2l_clk_p_i (i_gn4124.p2l_clk_p),
.gn_p2l_rdy_o (i_gn4124.p2l_rdy),
.gn_p2l_dframe_i (i_gn4124.p2l_dframe),
.gn_p2l_valid_i (i_gn4124.p2l_valid),
.gn_p2l_data_i (i_gn4124.p2l_data),
.gn_p_wr_req_i (i_gn4124.p_wr_req),
.gn_p_wr_rdy_o (i_gn4124.p_wr_rdy),
.gn_rx_error_o (i_gn4124.rx_error),
.gn_l2p_clk_n_o (i_gn4124.l2p_clk_n),
.gn_l2p_clk_p_o (i_gn4124.l2p_clk_p),
.gn_l2p_dframe_o (i_gn4124.l2p_dframe),
.gn_l2p_valid_o (i_gn4124.l2p_valid),
.gn_l2p_edb_o (i_gn4124.l2p_edb),
.gn_l2p_data_o (i_gn4124.l2p_data),
.gn_l2p_rdy_i (i_gn4124.l2p_rdy),
.gn_l_wr_rdy_i (i_gn4124.l_wr_rdy),
.gn_p_rd_d_rdy_i (i_gn4124.p_rd_d_rdy),
.gn_tx_error_i (i_gn4124.tx_error),
.gn_vc_rdy_i (i_gn4124.vc_rdy),
.gn_gpio_b (),
.ddr_a_o (ddr_a),
.ddr_ba_o (ddr_ba),
.ddr_cas_n_o (ddr_cas_n),
.ddr_ck_n_o (ddr_ck_n),
.ddr_ck_p_o (ddr_ck_p),
.ddr_cke_o (ddr_cke),
.ddr_dq_b (ddr_dq),
.ddr_ldm_o (ddr_dm[0]),
.ddr_ldqs_n_b (ddr_dqs_n[0]),
.ddr_ldqs_p_b (ddr_dqs_p[0]),
.ddr_odt_o (ddr_odt),
.ddr_ras_n_o (ddr_ras_n),
.ddr_reset_n_o (ddr_reset_n),
.ddr_rzq_b (ddr_rzq),
.ddr_udm_o (ddr_dm[1]),
.ddr_udqs_n_b (ddr_dqs_n[1]),
.ddr_udqs_p_b (ddr_dqs_p[1]),
.ddr_we_n_o (ddr_we_n)
);
ddr3 #
(
.DEBUG(0),
.check_strict_timing(0),
.check_strict_mrbits(0)
)
cmp_ddr0
(
.rst_n (ddr_reset_n),
.ck (ddr_ck_p),
.ck_n (ddr_ck_n),
.cke (ddr_cke),
.cs_n (1'b0),
.ras_n (ddr_ras_n),
.cas_n (ddr_cas_n),
.we_n (ddr_we_n),
.dm_tdqs (ddr_dm),
.ba (ddr_ba),
.addr (ddr_a),
.dq (ddr_dq),
.dqs (ddr_dqs_p),
.dqs_n (ddr_dqs_n),
.tdqs_n (),
.odt (ddr_odt)
);
typedef enum bit {RD,WR} dma_dir_t;
task dma_xfer(input CBusAccessor acc,
input uint64_t host_addr,
input uint32_t start_addr,
input uint32_t length,
input dma_dir_t dma_dir,
input int timeout = 1ms);
real timeout_time;
// Configure the VIC
acc.write(`VIC_BASE + 'h8, 'h7f);
acc.write(`VIC_BASE + 'h0, 'h1);
// Setup DMA addresses
acc.write(`DMA_BASE + 'h08, start_addr); // dma start addr
acc.write(`DMA_BASE + 'h0C, host_addr & 'hffffffff); // host addr low
acc.write(`DMA_BASE + 'h10, host_addr >> 32); // host addr high
acc.write(`DMA_BASE + 'h14, length); // length in bytes
acc.write(`DMA_BASE + 'h18, 'h00000000); // next low
acc.write(`DMA_BASE + 'h1C, 'h00000000); // next high
// Setup DMA direction
if (dma_dir == RD)
begin
acc.write(`DMA_BASE + 'h20, 'h00000000); // attrib: pcie -> host
$display("<%t> START DMA READ from 0x%x, %0d bytes",
$realtime, start_addr, length);
end
else
begin
acc.write(`DMA_BASE + 'h20, 'h00000001); // attrib: host -> pcie
$display("<%t> START DMA WRITE to 0x%x, %0d bytes",
$realtime, start_addr, length);
end
// Start transfer
acc.write(`DMA_BASE + 'h00, 'h00000001);
// Check for completion/timeout
timeout_time = $realtime + timeout;
while (timeout_time > $realtime)
begin
if (DUT.inst_spec_base.irqs[2] == 1)
begin
$display("<%t> END DMA", $realtime);
acc.write(`DMA_BASE + 'h04, 'h04);
acc.write(`VIC_BASE + 'h1c, 'h0);
return;
end
#1us;
end
$fatal(1, "<%t> DMA TIMEOUT", $realtime);
endtask // dma_xfer
typedef virtual IGN4124PCIMaster vIGN4124PCIMaster;
task dma_read_pattern(vIGN4124PCIMaster i_gn4124);
int i;
uint64_t val, expected;
CBusAccessor acc;
acc = i_gn4124.get_accessor();
acc.set_default_xfer_size(4);
// Read pattern from device memory
dma_xfer(acc, 'h20000000, 'h0, 4 * 'h20, RD);
// Verify pattern
for (i = 'h00; i < 'h20; i++)
begin
expected = i+1;
expected |= (i+1) << 8;
expected |= (i+1) << 16;
expected |= (i+1) << 24;
i_gn4124.host_mem_read(i*4, val);
if (val != expected)
$fatal(1, "<%t> READ-BACK ERROR at host address 0x%x: expected 0x%8x, got 0x%8x",
$realtime, i*4, expected, val);
end
endtask // dma_read_pattern
task dma_test(vIGN4124PCIMaster i_gn4124,
input uint32_t word_count);
int i;
uint32_t word_addr, word_remain, word_ptr;
uint64_t val, expected, host_addr;
uint64_t data_queue[$];
CBusAccessor acc;
acc = i_gn4124.get_accessor();
acc.set_default_xfer_size(4);
word_addr = $urandom_range(65535 - word_count);
// Prepare host memory
for (i = 0; i < word_count; i++)
begin
val = $urandom();
i_gn4124.host_mem_write(i*4, val);
data_queue.push_back(val);
end
// Write data to device memory
word_ptr = word_addr;
word_remain = word_count;
host_addr = 'h20000000;
while (word_remain != 0)
begin
if (word_remain > 1024)
begin
dma_xfer(acc, host_addr, word_ptr * 4, 4096, WR);
word_remain -= 1024;
word_ptr += 1024;
host_addr += 4096;
end
else
begin
dma_xfer(acc, host_addr, word_ptr * 4, word_remain * 4, WR);
word_ptr += word_remain;
word_remain = 0;
host_addr = 'h20000000;
end
end
// Clear host memory
for (i = 0; i < word_count; i++)
begin
i_gn4124.host_mem_write(i*4, 0);
end
// Read data from device memory
dma_xfer(acc, host_addr, word_addr * 4, word_count * 4, RD);
// Compare against written data
for (i = 0; i < word_count; i++)
begin
i_gn4124.host_mem_read(i*4, val);
expected = data_queue.pop_front();
if (val != expected)
$fatal(1, "<%t> READ-BACK ERROR at host address 0x%x: expected 0x%8x, got 0x%8x",
$realtime, i*4, expected, val);
end
endtask // dma_test
initial begin
int i;
uint64_t val, expected;
vIGN4124PCIMaster vi_gn4124;
vi_gn4124= i_gn4124;
$timeformat (-6, 3, "us", 10);
$display();
$display ("Simulation START");
$display();
#10us;
dma_read_pattern(vi_gn4124);
for (i = 2; i < 13; i++)
begin
#1us;
dma_test(vi_gn4124, 2**i);
end
$display();
$display ("Simulation PASSED");
$display();
$finish;
end
endmodule // main
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/testbench/dma_test/run.do 0000664 0000000 0000000 00000000312 13707547500 0025671 0 ustar 00root root 0000000 0000000 vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822 -voptargs="+acc" -sv_seed random
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run -all
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/testbench/dma_test/run_ci.do 0000664 0000000 0000000 00000000231 13707547500 0026344 0 ustar 00root root 0000000 0000000 vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822 -sv_seed random
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
run -all
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/testbench/dma_test/wave.do 0000664 0000000 0000000 00000027533 13707547500 0026045 0 ustar 00root root 0000000 0000000 onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -group {App DDR port} -color Coral /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/rst_n_i
add wave -noupdate -group {App DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_clk_o
add wave -noupdate -group {App DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_en_o
add wave -noupdate -group {App DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr_o
add wave -noupdate -group {App DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl_o
add wave -noupdate -group {App DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr_o
add wave -noupdate -group {App DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_empty_i
add wave -noupdate -group {App DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_full_i
add wave -noupdate -group {App DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_clk_o
add wave -noupdate -group {App DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_en_o
add wave -noupdate -group {App DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_mask_o
add wave -noupdate -group {App DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_data_o
add wave -noupdate -group {App DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_full_i
add wave -noupdate -group {App DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_empty_i
add wave -noupdate -group {App DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_count_i
add wave -noupdate -group {App DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_underrun_i
add wave -noupdate -group {App DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_error_i
add wave -noupdate -group {App DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_clk_o
add wave -noupdate -group {App DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_en_o
add wave -noupdate -group {App DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_data_i
add wave -noupdate -group {App DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_full_i
add wave -noupdate -group {App DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_empty_i
add wave -noupdate -group {App DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_count_i
add wave -noupdate -group {App DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_overflow_i
add wave -noupdate -group {App DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_error_i
add wave -noupdate -group {App DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_clk_i
add wave -noupdate -group {App DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_sel_i
add wave -noupdate -group {App DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_cyc_i
add wave -noupdate -group {App DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_stb_i
add wave -noupdate -group {App DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_we_i
add wave -noupdate -group {App DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_addr_i
add wave -noupdate -group {App DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_data_i
add wave -noupdate -group {App DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_data_o
add wave -noupdate -group {App DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_ack_o
add wave -noupdate -group {App DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_stall_o
add wave -noupdate -group {Host DDR port} -color Coral /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/rst_n_i
add wave -noupdate -group {Host DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_clk_o
add wave -noupdate -group {Host DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_o
add wave -noupdate -group {Host DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr_o
add wave -noupdate -group {Host DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl_o
add wave -noupdate -group {Host DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr_o
add wave -noupdate -group {Host DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_empty_i
add wave -noupdate -group {Host DDR port} -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_full_i
add wave -noupdate -group {Host DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_clk_o
add wave -noupdate -group {Host DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_en_o
add wave -noupdate -group {Host DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_mask_o
add wave -noupdate -group {Host DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_data_o
add wave -noupdate -group {Host DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_full_i
add wave -noupdate -group {Host DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_empty_i
add wave -noupdate -group {Host DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_count_i
add wave -noupdate -group {Host DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_underrun_i
add wave -noupdate -group {Host DDR port} -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_error_i
add wave -noupdate -group {Host DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_clk_o
add wave -noupdate -group {Host DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_en_o
add wave -noupdate -group {Host DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_data_i
add wave -noupdate -group {Host DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_full_i
add wave -noupdate -group {Host DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_empty_i
add wave -noupdate -group {Host DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_count_i
add wave -noupdate -group {Host DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_overflow_i
add wave -noupdate -group {Host DDR port} -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_error_i
add wave -noupdate -group {Host DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_clk_i
add wave -noupdate -group {Host DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_sel_i
add wave -noupdate -group {Host DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_cyc_i
add wave -noupdate -group {Host DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_stb_i
add wave -noupdate -group {Host DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_we_i
add wave -noupdate -group {Host DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_addr_i
add wave -noupdate -group {Host DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_data_i
add wave -noupdate -group {Host DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_data_o
add wave -noupdate -group {Host DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_ack_o
add wave -noupdate -group {Host DDR port} -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_stall_o
add wave -noupdate -group {P2L DATA} -color {Blue Violet} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/p2l_data_i
add wave -noupdate -group {P2L DATA} -color {Blue Violet} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/p2l_dframe_i
add wave -noupdate -group {P2L DATA} -color {Blue Violet} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/p2l_valid_i
add wave -noupdate -group {L2P DATA} -color {Steel Blue} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/l2p_data_o
add wave -noupdate -group {L2P DATA} -color {Steel Blue} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/l2p_dframe_o
add wave -noupdate -group {L2P DATA} -color {Steel Blue} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/l2p_valid_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {11653084600 fs} 0}
quietly wave cursor active 1
configure wave -namecolwidth 350
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 2
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 400000
configure wave -gridperiod 800000
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {57075202950 fs}
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/ 0000775 0000000 0000000 00000000000 13707547500 0021570 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/dma_test/ 0000775 0000000 0000000 00000000000 13707547500 0023370 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/dma_test/Manifest.py 0000664 0000000 0000000 00000000101 13707547500 0025500 0 ustar 00root root 0000000 0000000 files = ["spec_dma_test.vhd"]
modules = {'local': ["../../rtl"]}
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/dma_test/spec_dma_test.vhd 0000664 0000000 0000000 00000022352 13707547500 0026711 0 ustar 00root root 0000000 0000000 --------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_dma_test
--
-- description: A bitstream for testing DMA with a dummy application that pre-
-- loads the first 32 words (128 bytes) of the DDR with a predefined pattern:
--
-- 0x00: 0x01010101
-- 0x04: 0x02020202
-- ...
-- 0x7c: 0x20202020
--
--------------------------------------------------------------------------------
-- Copyright CERN 2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.wishbone_pkg.all;
entity spec_dma_test is
generic (
g_SIMULATION : boolean := FALSE
);
port (
-- Global ports
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
button1_n_i : in std_logic;
-- I2C to the FMC
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i : in std_logic;
-- DDR3
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic
);
end spec_dma_test;
architecture arch of spec_dma_test is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
signal wb_ddr_out : t_wishbone_master_out;
signal wb_ddr_in : t_wishbone_master_in;
type fsm_state_type is (S_IDLE, S_WRITE, S_DONE);
signal fsm_current_state : fsm_state_type;
begin
inst_spec_base : entity work.spec_base_wr
generic map (
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_DDR => TRUE,
g_DDR_DATA_SIZE => 32,
g_WITH_WR => FALSE,
g_SIMULATION => g_SIMULATION
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
pcbrev_i => pcbrev_i,
button1_n_i => button1_n_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_cyc_i => wb_ddr_out.cyc,
ddr_dma_wb_stb_i => wb_ddr_out.stb,
ddr_dma_wb_adr_i => wb_ddr_out.adr,
ddr_dma_wb_sel_i => wb_ddr_out.sel,
ddr_dma_wb_we_i => wb_ddr_out.we,
ddr_dma_wb_dat_i => wb_ddr_out.dat,
ddr_dma_wb_ack_o => wb_ddr_in.ack,
ddr_dma_wb_stall_o => wb_ddr_in.stall,
ddr_dma_wb_dat_o => wb_ddr_in.dat,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
spi_miso_i => '0',
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
p_fsm : process (clk_sys_62m5) is
variable pattern : unsigned(7 downto 0) := (others => '0');
begin -- process p_fsm
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
fsm_current_state <= S_IDLE;
pattern := (others => '0');
wb_ddr_out.adr <= (others => '0');
wb_ddr_out.dat <= (others => '0');
wb_ddr_out.cyc <= '0';
wb_ddr_out.stb <= '0';
else
wb_ddr_out.sel <= "1111";
wb_ddr_out.we <= '1';
case fsm_current_state is
when S_IDLE =>
wb_ddr_out.cyc <= '1';
fsm_current_state <= S_WRITE;
when S_WRITE =>
if wb_ddr_in.stall = '0' then
pattern := pattern + 1;
wb_ddr_out.cyc <= '1';
wb_ddr_out.stb <= '1';
wb_ddr_out.dat <= std_logic_vector(pattern & pattern & pattern & pattern);
wb_ddr_out.adr(7 downto 0) <= std_logic_vector(pattern - 1);
if pattern = 32 then
fsm_current_state <= S_DONE;
end if;
end if;
when S_DONE =>
if wb_ddr_in.stall = '0' then
wb_ddr_out.cyc <= '0';
wb_ddr_out.stb <= '0';
end if;
end case;
end if;
end if;
end process p_fsm;
end architecture arch;
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/full/ 0000775 0000000 0000000 00000000000 13707547500 0022532 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/full/Manifest.py 0000664 0000000 0000000 00000000075 13707547500 0024654 0 ustar 00root root 0000000 0000000 files = ["spec_full.vhd"]
modules = {'local': ["../../rtl"]}
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/full/spec_full.vhd 0000664 0000000 0000000 00000026164 13707547500 0025222 0 ustar 00root root 0000000 0000000 --------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_full
--
-- description: SPEC "full" design, with access to all peripherals and features
-- of the carrier board.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_full is
generic (
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Miscellanous SPEC pins
---------------------------------------------------------------------------
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_n_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
-- DDR3
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic
);
end entity spec_full;
architecture top of spec_full is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_spec_base: entity work.spec_base_wr
generic map (
g_with_vic => True,
g_with_onewire => False,
g_with_spi => False,
g_with_ddr => True,
g_dpram_initf => g_dpram_initf,
g_simulation => g_simulation
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end architecture top;
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/golden/ 0000775 0000000 0000000 00000000000 13707547500 0023040 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/golden/Manifest.py 0000664 0000000 0000000 00000000077 13707547500 0025164 0 ustar 00root root 0000000 0000000 files = ["spec_golden.vhd"]
modules = {'local': ["../../rtl"]}
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/golden/spec_golden.vhd 0000664 0000000 0000000 00000013521 13707547500 0026027 0 ustar 00root root 0000000 0000000 --------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_golden
--
-- description: SPEC golden design, without WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
entity spec_golden is
port (
-- Global ports
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
gn_RST_N_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
gn_GPIO_b : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
gn_P2L_RDY_o : out std_logic; -- Rx Buffer Full Flag
gn_P2L_CLK_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_P2L_CLK_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_P2L_DATA_i : in std_logic_vector(15 downto 0); -- Parallel receive data
gn_P2L_DFRAME_i : in std_logic; -- Receive Frame
gn_P2L_VALID_i : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
gn_P_WR_REQ_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_P_WR_RDY_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_RX_ERROR_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_L2P_DATA_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
gn_L2P_DFRAME_o : out std_logic; -- Transmit Data Frame
gn_L2P_VALID_o : out std_logic; -- Transmit Data Valid
gn_L2P_CLK_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_L2P_CLK_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_L2P_EDB_o : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
gn_L2P_RDY_i : in std_logic; -- Tx Buffer Full Flag
gn_L_WR_RDY_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_P_RD_D_RDY_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_TX_ERROR_i : in std_logic; -- Transmit Error
gn_VC_RDY_i : in std_logic_vector(1 downto 0); -- Channel ready
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Font panel LEDs
-- LED_RED : out std_logic;
-- LED_GREEN : out std_logic;
button1_n_i : in std_logic;
-- I2C to the FMC
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
onewire_b : inout std_logic;
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end spec_golden;
architecture rtl of spec_golden is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_spec_base: entity work.spec_base_wr
generic map (
g_WITH_VIC => True,
g_WITH_ONEWIRE => True,
g_WITH_SPI => True,
g_WITH_DDR => False,
g_WITH_WR => False,
g_simulation => False
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end rtl;
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/golden_wr/ 0000775 0000000 0000000 00000000000 13707547500 0023550 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/golden_wr/Manifest.py 0000664 0000000 0000000 00000000102 13707547500 0025661 0 ustar 00root root 0000000 0000000 files = ["spec_golden_wr.vhd"]
modules = {'local': ["../../rtl"]}
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/hdl/top/golden_wr/spec_golden_wr.vhd 0000664 0000000 0000000 00000023450 13707547500 0027251 0 ustar 00root root 0000000 0000000 --------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_golden_wr
--
-- description: SPEC golden design, with WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_golden_wr is
generic (
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Miscellanous SPEC pins
---------------------------------------------------------------------------
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_n_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic
);
end entity spec_golden_wr;
architecture top of spec_golden_wr is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_spec_base: entity work.spec_base_wr
generic map (
g_WITH_VIC => True,
g_WITH_ONEWIRE => False,
g_WITH_SPI => False,
g_WITH_DDR => False,
g_WITH_WR => True,
g_dpram_initf => g_dpram_initf,
g_simulation => g_simulation
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end architecture top;
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/pytest/ 0000775 0000000 0000000 00000000000 13707547500 0021547 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/pytest/conftest.py 0000664 0000000 0000000 00000001353 13707547500 0023750 0 ustar 00root root 0000000 0000000 """
SPDX-License-Identifier: GPL-3.0-or-later
SPDX-FileCopyrightText: 2020 CERN
"""
import pytest
from PySPEC import PySPEC
@pytest.fixture(scope="function")
def spec():
spec_dev = PySPEC(pytest.pci_id)
yield spec_dev
def pytest_addoption(parser):
parser.addoption("--pci-id",
required=True, help="SPEC PCI Identifier")
parser.addoption("--bitstream",
default=None, help="SPEC bitstream to be tested")
def pytest_configure(config):
pytest.pci_id = config.getoption("--pci-id")
pytest.cfg_bitstream = config.getoption("--bitstream")
if pytest.cfg_bitstream is not None:
spec = PySPEC(pytest.pci_id)
spec.program_fpga(pytest.cfg_bitstream)
del spec
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/pytest/pytest.ini 0000664 0000000 0000000 00000000172 13707547500 0023600 0 ustar 00root root 0000000 0000000 # SPDX-License-Identifier: GPL-3.0-or-later
# SPDX-FileCopyrightText: 2020 CERN
[pytest]
addopts = -v -p no:cacheprovider spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/pytest/test_dma.py 0000664 0000000 0000000 00000030251 13707547500 0023722 0 ustar 00root root 0000000 0000000 """
SPDX-License-Identifier: GPL-3.0-or-later
SPDX-FileCopyrightText: 2020 CERN
"""
import pytest
import random
import math
import os
import re
from PySPEC import PySPEC
random_repetitions = 0
class TestDma(object):
def test_acquisition_release(self, spec):
"""
Users can open and close the DMA channel
"""
with spec.dma() as dma:
pass
def test_acquisition_release_contention(self, spec):
"""
Refuse simultaneous DMA transfers
"""
with spec.dma() as dma:
spec_c = PySPEC(spec.pci_id)
with pytest.raises(OSError) as error:
with spec_c.dma() as dma2:
pass
def test_dma_no_buffer(self, spec):
"""
The read/write will return immediatelly if asked to perform
0-length transfer.
"""
with spec.dma() as dma:
data = dma.read(0, 0)
assert len(data) == 0
with spec.dma() as dma:
count = dma.write(0, b"")
assert count == 0
@pytest.mark.parametrize("buffer_size",
[2**i for i in range(3, 22)])
def test_dma_read(self, spec, buffer_size):
"""
We just want to see if the DMA engine reports errors. Test the
engine with different sizes, but same offset (default:
0x0). On the engine side we will get several transfers
(scatterlist) depending on the size.
"""
with spec.dma() as dma:
data1 = dma.read(0, buffer_size)
data2 = dma.read(0, buffer_size)
assert len(data1) == buffer_size
assert len(data2) == buffer_size
assert data1 == data2
@pytest.mark.parametrize("buffer_size",
[2**i for i in range(3, 22)])
def test_dma_write(self, spec, buffer_size):
"""
We just want to see if the DMA engine reports errors. Test the
engine with different sizes, but same offset (default:
0x0). On the engine side we will get several transfers
(scatterlist) depending on the size.
"""
with spec.dma() as dma:
count = dma.write(0, b"\x00" * buffer_size)
assert count == buffer_size
@pytest.mark.parametrize("ddr_offset",
[2**i for i in range(2, int(math.log2(PySPEC.DDR_SIZE)))])
@pytest.mark.parametrize("unaligned", range(1, PySPEC.DDR_ALIGN))
def test_dma_unaligned_offset_read(self, spec, ddr_offset, unaligned):
"""
The DDR access is 4byte aligned.
"""
with spec.dma() as dma:
with pytest.raises(OSError) as error:
dma.read(ddr_offset + unaligned, 16)
@pytest.mark.parametrize("ddr_offset",
[2**i for i in range(2, int(math.log2(PySPEC.DDR_SIZE)))])
@pytest.mark.parametrize("unaligned", range(1, PySPEC.DDR_ALIGN))
def test_dma_unaligned_offset_write(self, spec, ddr_offset, unaligned):
"""
The DDR access is 4byte aligned.
"""
with spec.dma() as dma:
with pytest.raises(OSError) as error:
dma.write(ddr_offset + unaligned, b"\x00" * 16)
@pytest.mark.parametrize("ddr_offset",
[2**i for i in range(2, int(math.log2(PySPEC.DDR_SIZE)))])
@pytest.mark.parametrize("unaligned", range(1, PySPEC.DDR_ALIGN))
def test_dma_unaligned_size_read(self, spec, ddr_offset, unaligned):
"""
The DDR access is 4byte aligned.
"""
with spec.dma() as dma:
with pytest.raises(OSError) as error:
dma.read(ddr_offset, (16 + unaligned))
@pytest.mark.parametrize("ddr_offset",
[2**i for i in range(2, int(math.log2(PySPEC.DDR_SIZE)))])
@pytest.mark.parametrize("unaligned", range(1, PySPEC.DDR_ALIGN))
def test_dma_unaligned_size_write(self, spec, ddr_offset, unaligned):
"""
The DDR access is 4byte aligned.
"""
with spec.dma() as dma:
with pytest.raises(OSError) as error:
dma.write(ddr_offset, b"\x00" * (16 + unaligned))
@pytest.mark.parametrize("split", [2**i for i in range(3, 14)])
@pytest.mark.parametrize("ddr_offset", [0x0, ])
@pytest.mark.parametrize("buffer_size", [2**14, ])
def test_dma_split_read(self, spec, buffer_size, ddr_offset, split, capsys):
"""
Write and read back buffers using DMA. We test different combinations
of offset and size. Here we atrificially split the **read** in small
pieces.
In the past we had problems with transfers greater than 4KiB. Be sure
that we can perform transfers (read) of "any" size.
"""
data = bytes([random.randrange(0, 0xFF, 1) for i in range(buffer_size)])
with spec.dma() as dma:
dma.write(ddr_offset, data)
data_rb = b""
for offset in range(0, buffer_size, split):
data_rb += dma.read(ddr_offset + offset, split)
assert data == data_rb
@pytest.mark.parametrize("split", [2**i for i in range(3, 14)])
@pytest.mark.parametrize("ddr_offset", [0x0, ])
@pytest.mark.parametrize("buffer_size", [2**14, ])
def test_dma_split_write(self, spec, buffer_size, ddr_offset, split):
"""
Write and read back buffers using DMA. We test different combinations
of offset and size. Here we atrificially split the **write** in small
pieces.
In the past we had problems with transfers greater than 4KiB. Be sure
that we can perform transfers (write) of "any" size.
"""
data = bytes([random.randrange(0, 0xFF, 1) for i in range(buffer_size)])
with spec.dma() as dma:
for offset in range(0, buffer_size, split):
dma.write(offset, data[offset:min(offset+split, buffer_size)])
data_rb = dma.read(0x0, buffer_size)
assert data == data_rb
@pytest.mark.parametrize("split", [2**i for i in range(3, 14)])
@pytest.mark.parametrize("buffer_size", [2**14, ])
def test_dma_split(self, spec, buffer_size, split):
"""
Write and read back buffers using DMA. We test different combinations
of offset and size. Here we atrificially split transfers in small
pieces.
In the past we had problems with transfers greater than 4KiB. Be sure
that we can perform transfers of "any" size.
"""
data = bytes([random.randrange(0, 0xFF, 1) for i in range(buffer_size)])
with spec.dma() as dma:
for offset in range(0, buffer_size, split):
dma.write(offset, data[offset:min(offset+split, buffer_size)])
for offset in range(0, buffer_size, split):
data_rb = dma.read(offset, split)
assert data[offset:min(offset+split, buffer_size)] == data_rb
@pytest.mark.parametrize("segment_size", [2**i for i in range(3, 20)])
def test_dma_scatterlist_read(self, spec, segment_size):
"""
Enforce a scatterlist on known size to read 1MiB.
"""
buffer_size = 2**20
data = bytes([random.randrange(0, 0xFF, 1) for i in range(buffer_size)])
with spec.dma() as dma:
dma.write(0, data)
assert data == dma.read(0, len(data), segment_size)
@pytest.mark.parametrize("segment_size", [2**i for i in range(3, 12)])
def test_dma_scatterlist_write(self, spec, segment_size):
"""
Enforce a scatterlist on known size to write 1MiB.
Remember: on write the scatterlist is enforced by the driver
on buffers bigger than 4KiB
"""
buffer_size = 2**20
data = bytes([random.randrange(0, 0xFF, 1) for i in range(buffer_size)])
with spec.dma() as dma:
dma.write(0, data, segment_size)
assert data == dma.read(0, len(data))
@pytest.mark.parametrize("ddr_offset",
[0x0] + \
[2**i for i in range(int(math.log2(PySPEC.DDR_ALIGN)), int(math.log2(PySPEC.DDR_SIZE)))] + \
[random.randrange(0, PySPEC.DDR_SIZE, PySPEC.DDR_ALIGN) for x in range(random_repetitions)])
@pytest.mark.parametrize("buffer_size",
[2**i for i in range(int(math.log2(PySPEC.DDR_ALIGN)) + 1, 22)] + \
[random.randrange(PySPEC.DDR_ALIGN * 2, 4096, PySPEC.DDR_ALIGN) for x in range(random_repetitions)])
def test_dma(self, spec, ddr_offset, buffer_size):
"""
Write and read back buffers using DMA. We test different combinations
of offset and size. Here we try to perform transfers as large as
possible.
"""
if ddr_offset + buffer_size >= PySPEC.DDR_SIZE:
pytest.skip("DDR Overflow!")
data = bytes([random.randrange(0, 0xFF, 1) for i in range(buffer_size)])
with spec.dma() as dma:
dma.write(ddr_offset, data)
data_rb = dma.read(ddr_offset, buffer_size)
assert data == data_rb
def test_dma_reg_zero(self, spec):
"""
Regression test.
It happend that after 256Bytes the received data is just
0x00. Other times it happend at different sizes but always
among the first power of two values
"""
data = bytes([random.randrange(0, 0xFF, 1) for i in range(1024)])
with spec.dma() as dma:
dma.write(0, data)
for i in range(1000000):
assert data == dma.read(0, len(data))
@pytest.mark.skipif(pytest.cfg_bitstream is None,
reason="We need a bitstream to reflash")
def test_dma_reg_word(self, spec):
"""
Regression test.
It happend that a 4Bytes transfer was triggering a DMA error
and in some cases it was irremediably corrupting the gennum chip.
This is most likely to happen once after programming the FPGA, and
it may take a long time before it happens again.
"""
spec.program_fpga(pytest.cfg_bitstream)
with spec.dma() as dma:
data = b"0123456789abcdefghilmnopqrstuvwx"
dma.write(0, data)
for i in range(10000000):
try:
assert data[0:4] == dma.read(0, 4)
except OSError as error:
assert False, "Failed after {:d} transfers".format(i)
@pytest.mark.parametrize("dma_alloc_size",
[2**20 * x for x in range(1, 5)])
def test_dma_throughput_read(self, spec, dma_alloc_size):
"""
It roughly measure read throughput by using the kernel
tracer. It does a simple avarage of 100 acquisitions.
A safe expectation today is 230MBps
"""
tracing_path = "/sys/kernel/debug/tracing"
with open(os.path.join(tracing_path, "current_tracer"), "w") as f:
f.write("function")
with open(os.path.join(tracing_path, "set_ftrace_filter"), "w") as f:
f.write("gn412x_dma_irq_handler\ngn412x_dma_start_task")
with open(os.path.join(tracing_path, "trace"), "w") as f:
f.write("")
diff = []
for i in range(100):
with open(os.path.join(tracing_path, "trace"), "w") as f:
f.write("")
with spec.dma(dma_alloc_size) as dma:
data = dma.read(0, dma_alloc_size)
assert len(data) == dma_alloc_size
with open(os.path.join(tracing_path, "trace"), "r") as f:
trace = f.read()
start = re.search(r"([0-9]+\.[0-9]{6}): gn412x_dma_start_task", trace, re.MULTILINE)
assert start is not None, trace
assert len(start.groups()) == 1
end = re.search(r"([0-9]+\.[0-9]{6}): gn412x_dma_irq_handler", trace, re.MULTILINE)
assert end is not None, trace
assert len(end.groups()) == 1
diff.append(float(end.group(1)) - float(start.group(1)))
assert diff[-1] > 0
throughput_m = int((dma_alloc_size / (round(math.fsum(diff) / 100, 6))) / 1024 / 1024)
assert throughput_m > 230, \
"Expected mora than {:d} MBps, got {:d} MBps".format(500,
throughput_m)
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/ 0000775 0000000 0000000 00000000000 13707547500 0022051 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/Makefile 0000664 0000000 0000000 00000000644 13707547500 0023515 0 ustar 00root root 0000000 0000000 -include Makefile.specific
-include $(REPO_PARENT)/parent_common.mk
DIRS = kernel
.PHONY: all clean modules install modules_install coccicheck $(DIRS)
all clean : $(DIRS)
install modules_install coccicheck modules: kernel
clean: TARGET = clean
modules: TARGET = modules
coccicheck: TARGET = coccicheck
install: TARGET = install
modules_install: TARGET = modules_install
$(DIRS):
$(MAKE) -C $@ $(ENV_VAR) $(TARGET)
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/PySPEC/ 0000775 0000000 0000000 00000000000 13707547500 0023114 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/PySPEC/.gitignore 0000664 0000000 0000000 00000000131 13707547500 0025077 0 ustar 00root root 0000000 0000000 # SPDX-License-Identifier: CC0-1.0
#
# SPDX-FileCopyrightText: 2020 CERN
*.pyc
MANIFEST
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/PySPEC/Makefile 0000664 0000000 0000000 00000000257 13707547500 0024560 0 ustar 00root root 0000000 0000000 # SPDX-License-Identifier: CC0-1.0
#
# SPDX-FileCopyrightText: 2020 CERN
-include Makefile.specific
all:
clean:
install:
python setup.py install
.PHONY: all clean install
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/PySPEC/PySPEC/ 0000775 0000000 0000000 00000000000 13707547500 0024157 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/PySPEC/PySPEC/PySPEC.py 0000664 0000000 0000000 00000013523 13707547500 0025600 0 ustar 00root root 0000000 0000000 """
@package docstring
@author: Federico Vaga
SPDX-License-Identifier: LGPL-3.0-or-later
SPDX-FileCopyrightText: 2020 CERN (home.cern)
"""
import os
from contextlib import contextmanager
class PySPEC:
"""
This class gives access to SPEC features.
"""
#: SPEC DDR size
DDR_SIZE = 256 * 1024 * 1024
#: SPEC DDR access alignment
DDR_ALIGN = 4
def __init__(self, pci_id):
self.pci_id = pci_id
self.debugfs = "/sys/kernel/debug/0000:{:s}".format(self.pci_id)
self.debugfs_fpga = os.path.join(self.debugfs, "spec-0000:{:s}".format(self.pci_id))
def program_fpga(self, bitstream):
"""
Program the FPGA with the given bitstream
:var path: path to bitstream
:raise OSError: on failure
"""
with open("/sys/module/firmware_class/parameters/path", "r") as f:
prev = f.read()
with open("/sys/module/firmware_class/parameters/path", "w") as f:
f.write(os.path.dirname(bitstream))
with open(os.path.join(self.debugfs, "fpga_firmware"), "w") as f:
f.write(os.path.basename(bitstream))
with open("/sys/module/firmware_class/parameters/path", "w") as f:
f.write(os.path.dirname(prev))
@contextmanager
def dma(self, dma_coherent_size=None):
"""
Create a DMA context from which users can do DMA
transfers. Within this context the user can use
PySPECDMA.read() and PySPECDMA.write(). Here an example.
>>> from PySPEC import PySPEC
>>> spec = PySPEC("06:00.0")
>>> with spec.dma() as dma:
>>> cnt = dma.write(0, b"\x00" * 16)
>>> buffer = dma.read(0, 16)
Which is equivalent to:
>>> from PySPEC import PySPEC
>>> spec = PySPEC("06:00.0")
>>> spec_dma = PySPEC.PySPECDMA(spec)
>>> spec_dma.open()
>>> cnt = spec_dma.write(0, b"\x00" * 16)
>>> buffer = spec_dma.read(0, 16)
>>> spec_dma.close()
"""
spec_dma = self.PySPECDMA(self)
spec_dma.request(dma_coherent_size)
try:
yield spec_dma
finally:
spec_dma.release()
class PySPECDMA:
"""
This class wraps DMA features in a single object.
The SPEC has
only one DMA channel. On request() the user will get exclusive
access. The user must release() the DMA channel as soon as
possible to let other users or drivers to access it. For this reason,
avoid to use this class directly. Instead, use the DMA context
from the PySPEC class which is less error prone.
>>> from PySPEC import PySPEC
>>> spec = PySPEC("06:00.0")
>>> with spec.dma() as dma:
>>> cnt = dma.write(0, b"\x00" * 16)
>>> buffer = dma.read(0, 16)
>>> print(buffer)
"""
def __init__(self, spec):
"""
Create a new instance
:var spec: a valid PySPEC instance
"""
self.spec = spec
def request(self, dma_coherent_size=None):
"""
Open a DMA file descriptor
:var dma_coherent_size: DMA coherent allocation size (in-kernel).
:raise OSError: if the open(2) or the driver fails
"""
if dma_coherent_size is not None:
with open("/sys/module/spec_fmc_carrier/parameters/user_dma_coherent_size", "w") as f:
f.write(str(dma_coherent_size))
self.dma_file = open(os.path.join(self.spec.debugfs_fpga, "dma"),
"rb+", buffering=0)
def release(self):
"""
Close the DMA file descriptor
:raise OSError: if the close(2) or the driver fails
"""
if hasattr(self, "dma_file"):
self.dma_file.close()
def read(self, offset, size, max_segment=0):
"""
Trigger a *device to memory* DMA transfer
:var offset: offset within the DDR
:var size: number of bytes to be transferred
:var max_segment: maximum size of a single transfer in a
scatterlist. Default is 0, it means to use
the DMA engine's default.
:return: the data transfered as bytes() array
:raise OSError: if the read(2) or the driver fails
"""
with open("/sys/module/spec_fmc_carrier/parameters/user_dma_max_segment", "w") as f:
f.write(str(max_segment))
self.__seek(offset)
data = []
while size - len(data) > 0:
data += self.dma_file.read(size - len(data))
return bytes(data)
def write(self, offset, data, max_segment=0):
"""
Trigger a *memory to device* DMA transfer
:var offset: offset within the DDR
:var size: number of bytes to be transferred
:var max_segment: maximum size of a single transfer in a
scatterlist. Default is 0, it means to use
the DMA engine's default.
:return: the number of transfered bytes
:raise OSError: if the write(2) or the driver fails
"""
with open("/sys/module/spec_fmc_carrier/parameters/user_dma_max_segment", "w") as f:
f.write(str(max_segment))
self.__seek(offset)
start = 0
while len(data) - start > 0:
start += self.dma_file.write(bytes(data[start:]))
return start
def __seek(self, offset):
"""
Change DDR offset
:var offset: offset within the DDR
:raise OSError: if lseek(2) fails or the driver
"""
self.dma_file.seek(offset)
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/PySPEC/PySPEC/__init__.py 0000664 0000000 0000000 00000000336 13707547500 0026272 0 ustar 00root root 0000000 0000000 """
@package docstring
@author: Federico Vaga
SPDX-License-Identifier: LGPL-3.0-or-later
SPDX-FileCopyrightText: 2020 CERN (home.cern)
"""
from .PySPEC import PySPEC
__all__ = (
"PySPEC",
)
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/PySPEC/setup.py 0000664 0000000 0000000 00000000772 13707547500 0024634 0 ustar 00root root 0000000 0000000 #!/usr/bin/env python
"""
SPDX-License-Identifier: CC0-1.0
SPDX-FileCopyrightText: 2020 CERN
"""
from distutils.core import setup
setup(name='PySPEC',
version='1.4.14',
description='Python Module to handle SPEC cards',
author='Federico Vaga',
author_email='federico.vaga@cern.ch',
maintainer="Federico Vaga",
maintainer_email="federico.vaga@cern.ch",
url='https://www.ohwr.org/project/spec',
packages=['PySPEC'],
license='LGPL-3.0-or-later',
)
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/ 0000775 0000000 0000000 00000000000 13707547500 0023331 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/.clang-format 0000664 0000000 0000000 00000035726 13707547500 0025721 0 ustar 00root root 0000000 0000000 # SPDX-License-Identifier: GPL-2.0
#
# clang-format configuration file. Intended for clang-format >= 4.
#
# For more information, see:
#
# Documentation/process/clang-format.rst
# https://clang.llvm.org/docs/ClangFormat.html
# https://clang.llvm.org/docs/ClangFormatStyleOptions.html
#
---
AccessModifierOffset: -4
AlignAfterOpenBracket: Align
AlignConsecutiveAssignments: false
AlignConsecutiveDeclarations: false
#AlignEscapedNewlines: Left # Unknown to clang-format-4.0
AlignOperands: true
AlignTrailingComments: false
AllowAllParametersOfDeclarationOnNextLine: false
AllowShortBlocksOnASingleLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: None
AllowShortIfStatementsOnASingleLine: false
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: false
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterClass: false
AfterControlStatement: false
AfterEnum: false
AfterFunction: true
AfterNamespace: true
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
#AfterExternBlock: false # Unknown to clang-format-5.0
BeforeCatch: false
BeforeElse: false
IndentBraces: false
#SplitEmptyFunction: true # Unknown to clang-format-4.0
#SplitEmptyRecord: true # Unknown to clang-format-4.0
#SplitEmptyNamespace: true # Unknown to clang-format-4.0
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Custom
#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0
BreakBeforeTernaryOperators: false
BreakConstructorInitializersBeforeComma: false
#BreakConstructorInitializers: BeforeComma # Unknown to clang-format-4.0
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: false
ColumnLimit: 80
CommentPragmas: '^ IWYU pragma:'
#CompactNamespaces: false # Unknown to clang-format-4.0
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 8
ContinuationIndentWidth: 8
Cpp11BracedListStyle: false
DerivePointerAlignment: false
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
#FixNamespaceComments: false # Unknown to clang-format-4.0
# Taken from:
# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ \
# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \
# | sort | uniq
ForEachMacros:
- 'apei_estatus_for_each_section'
- 'ata_for_each_dev'
- 'ata_for_each_link'
- '__ata_qc_for_each'
- 'ata_qc_for_each'
- 'ata_qc_for_each_raw'
- 'ata_qc_for_each_with_internal'
- 'ax25_for_each'
- 'ax25_uid_for_each'
- '__bio_for_each_bvec'
- 'bio_for_each_bvec'
- 'bio_for_each_integrity_vec'
- '__bio_for_each_segment'
- 'bio_for_each_segment'
- 'bio_for_each_segment_all'
- 'bio_list_for_each'
- 'bip_for_each_vec'
- 'blkg_for_each_descendant_post'
- 'blkg_for_each_descendant_pre'
- 'blk_queue_for_each_rl'
- 'bond_for_each_slave'
- 'bond_for_each_slave_rcu'
- 'bpf_for_each_spilled_reg'
- 'btree_for_each_safe128'
- 'btree_for_each_safe32'
- 'btree_for_each_safe64'
- 'btree_for_each_safel'
- 'card_for_each_dev'
- 'cgroup_taskset_for_each'
- 'cgroup_taskset_for_each_leader'
- 'cpufreq_for_each_entry'
- 'cpufreq_for_each_entry_idx'
- 'cpufreq_for_each_valid_entry'
- 'cpufreq_for_each_valid_entry_idx'
- 'css_for_each_child'
- 'css_for_each_descendant_post'
- 'css_for_each_descendant_pre'
- 'device_for_each_child_node'
- 'dma_fence_chain_for_each'
- 'drm_atomic_crtc_for_each_plane'
- 'drm_atomic_crtc_state_for_each_plane'
- 'drm_atomic_crtc_state_for_each_plane_state'
- 'drm_atomic_for_each_plane_damage'
- 'drm_client_for_each_connector_iter'
- 'drm_client_for_each_modeset'
- 'drm_connector_for_each_possible_encoder'
- 'drm_for_each_connector_iter'
- 'drm_for_each_crtc'
- 'drm_for_each_encoder'
- 'drm_for_each_encoder_mask'
- 'drm_for_each_fb'
- 'drm_for_each_legacy_plane'
- 'drm_for_each_plane'
- 'drm_for_each_plane_mask'
- 'drm_for_each_privobj'
- 'drm_mm_for_each_hole'
- 'drm_mm_for_each_node'
- 'drm_mm_for_each_node_in_range'
- 'drm_mm_for_each_node_safe'
- 'flow_action_for_each'
- 'for_each_active_dev_scope'
- 'for_each_active_drhd_unit'
- 'for_each_active_iommu'
- 'for_each_available_child_of_node'
- 'for_each_bio'
- 'for_each_board_func_rsrc'
- 'for_each_bvec'
- 'for_each_card_components'
- 'for_each_card_links'
- 'for_each_card_links_safe'
- 'for_each_card_prelinks'
- 'for_each_card_rtds'
- 'for_each_card_rtds_safe'
- 'for_each_cgroup_storage_type'
- 'for_each_child_of_node'
- 'for_each_clear_bit'
- 'for_each_clear_bit_from'
- 'for_each_cmsghdr'
- 'for_each_compatible_node'
- 'for_each_component_dais'
- 'for_each_component_dais_safe'
- 'for_each_comp_order'
- 'for_each_console'
- 'for_each_cpu'
- 'for_each_cpu_and'
- 'for_each_cpu_not'
- 'for_each_cpu_wrap'
- 'for_each_dev_addr'
- 'for_each_dev_scope'
- 'for_each_displayid_db'
- 'for_each_dma_cap_mask'
- 'for_each_dpcm_be'
- 'for_each_dpcm_be_rollback'
- 'for_each_dpcm_be_safe'
- 'for_each_dpcm_fe'
- 'for_each_drhd_unit'
- 'for_each_dss_dev'
- 'for_each_efi_memory_desc'
- 'for_each_efi_memory_desc_in_map'
- 'for_each_element'
- 'for_each_element_extid'
- 'for_each_element_id'
- 'for_each_endpoint_of_node'
- 'for_each_evictable_lru'
- 'for_each_fib6_node_rt_rcu'
- 'for_each_fib6_walker_rt'
- 'for_each_free_mem_pfn_range_in_zone'
- 'for_each_free_mem_pfn_range_in_zone_from'
- 'for_each_free_mem_range'
- 'for_each_free_mem_range_reverse'
- 'for_each_func_rsrc'
- 'for_each_hstate'
- 'for_each_if'
- 'for_each_iommu'
- 'for_each_ip_tunnel_rcu'
- 'for_each_irq_nr'
- 'for_each_link_codecs'
- 'for_each_link_platforms'
- 'for_each_lru'
- 'for_each_matching_node'
- 'for_each_matching_node_and_match'
- 'for_each_memblock'
- 'for_each_memblock_type'
- 'for_each_memcg_cache_index'
- 'for_each_mem_pfn_range'
- 'for_each_mem_range'
- 'for_each_mem_range_rev'
- 'for_each_migratetype_order'
- 'for_each_msi_entry'
- 'for_each_msi_entry_safe'
- 'for_each_net'
- 'for_each_netdev'
- 'for_each_netdev_continue'
- 'for_each_netdev_continue_rcu'
- 'for_each_netdev_feature'
- 'for_each_netdev_in_bond_rcu'
- 'for_each_netdev_rcu'
- 'for_each_netdev_reverse'
- 'for_each_netdev_safe'
- 'for_each_net_rcu'
- 'for_each_new_connector_in_state'
- 'for_each_new_crtc_in_state'
- 'for_each_new_mst_mgr_in_state'
- 'for_each_new_plane_in_state'
- 'for_each_new_private_obj_in_state'
- 'for_each_node'
- 'for_each_node_by_name'
- 'for_each_node_by_type'
- 'for_each_node_mask'
- 'for_each_node_state'
- 'for_each_node_with_cpus'
- 'for_each_node_with_property'
- 'for_each_of_allnodes'
- 'for_each_of_allnodes_from'
- 'for_each_of_cpu_node'
- 'for_each_of_pci_range'
- 'for_each_old_connector_in_state'
- 'for_each_old_crtc_in_state'
- 'for_each_old_mst_mgr_in_state'
- 'for_each_oldnew_connector_in_state'
- 'for_each_oldnew_crtc_in_state'
- 'for_each_oldnew_mst_mgr_in_state'
- 'for_each_oldnew_plane_in_state'
- 'for_each_oldnew_plane_in_state_reverse'
- 'for_each_oldnew_private_obj_in_state'
- 'for_each_old_plane_in_state'
- 'for_each_old_private_obj_in_state'
- 'for_each_online_cpu'
- 'for_each_online_node'
- 'for_each_online_pgdat'
- 'for_each_pci_bridge'
- 'for_each_pci_dev'
- 'for_each_pci_msi_entry'
- 'for_each_populated_zone'
- 'for_each_possible_cpu'
- 'for_each_present_cpu'
- 'for_each_prime_number'
- 'for_each_prime_number_from'
- 'for_each_process'
- 'for_each_process_thread'
- 'for_each_property_of_node'
- 'for_each_registered_fb'
- 'for_each_reserved_mem_region'
- 'for_each_rtd_codec_dai'
- 'for_each_rtd_codec_dai_rollback'
- 'for_each_rtdcom'
- 'for_each_rtdcom_safe'
- 'for_each_set_bit'
- 'for_each_set_bit_from'
- 'for_each_sg'
- 'for_each_sg_dma_page'
- 'for_each_sg_page'
- 'for_each_sibling_event'
- 'for_each_subelement'
- 'for_each_subelement_extid'
- 'for_each_subelement_id'
- '__for_each_thread'
- 'for_each_thread'
- 'for_each_zone'
- 'for_each_zone_zonelist'
- 'for_each_zone_zonelist_nodemask'
- 'fwnode_for_each_available_child_node'
- 'fwnode_for_each_child_node'
- 'fwnode_graph_for_each_endpoint'
- 'gadget_for_each_ep'
- 'genradix_for_each'
- 'genradix_for_each_from'
- 'hash_for_each'
- 'hash_for_each_possible'
- 'hash_for_each_possible_rcu'
- 'hash_for_each_possible_rcu_notrace'
- 'hash_for_each_possible_safe'
- 'hash_for_each_rcu'
- 'hash_for_each_safe'
- 'hctx_for_each_ctx'
- 'hlist_bl_for_each_entry'
- 'hlist_bl_for_each_entry_rcu'
- 'hlist_bl_for_each_entry_safe'
- 'hlist_for_each'
- 'hlist_for_each_entry'
- 'hlist_for_each_entry_continue'
- 'hlist_for_each_entry_continue_rcu'
- 'hlist_for_each_entry_continue_rcu_bh'
- 'hlist_for_each_entry_from'
- 'hlist_for_each_entry_from_rcu'
- 'hlist_for_each_entry_rcu'
- 'hlist_for_each_entry_rcu_bh'
- 'hlist_for_each_entry_rcu_notrace'
- 'hlist_for_each_entry_safe'
- '__hlist_for_each_rcu'
- 'hlist_for_each_safe'
- 'hlist_nulls_for_each_entry'
- 'hlist_nulls_for_each_entry_from'
- 'hlist_nulls_for_each_entry_rcu'
- 'hlist_nulls_for_each_entry_safe'
- 'i3c_bus_for_each_i2cdev'
- 'i3c_bus_for_each_i3cdev'
- 'ide_host_for_each_port'
- 'ide_port_for_each_dev'
- 'ide_port_for_each_present_dev'
- 'idr_for_each_entry'
- 'idr_for_each_entry_continue'
- 'idr_for_each_entry_continue_ul'
- 'idr_for_each_entry_ul'
- 'in_dev_for_each_ifa_rcu'
- 'in_dev_for_each_ifa_rtnl'
- 'inet_bind_bucket_for_each'
- 'inet_lhash2_for_each_icsk_rcu'
- 'key_for_each'
- 'key_for_each_safe'
- 'klp_for_each_func'
- 'klp_for_each_func_safe'
- 'klp_for_each_func_static'
- 'klp_for_each_object'
- 'klp_for_each_object_safe'
- 'klp_for_each_object_static'
- 'kvm_for_each_memslot'
- 'kvm_for_each_vcpu'
- 'list_for_each'
- 'list_for_each_codec'
- 'list_for_each_codec_safe'
- 'list_for_each_entry'
- 'list_for_each_entry_continue'
- 'list_for_each_entry_continue_rcu'
- 'list_for_each_entry_continue_reverse'
- 'list_for_each_entry_from'
- 'list_for_each_entry_from_rcu'
- 'list_for_each_entry_from_reverse'
- 'list_for_each_entry_lockless'
- 'list_for_each_entry_rcu'
- 'list_for_each_entry_reverse'
- 'list_for_each_entry_safe'
- 'list_for_each_entry_safe_continue'
- 'list_for_each_entry_safe_from'
- 'list_for_each_entry_safe_reverse'
- 'list_for_each_prev'
- 'list_for_each_prev_safe'
- 'list_for_each_safe'
- 'llist_for_each'
- 'llist_for_each_entry'
- 'llist_for_each_entry_safe'
- 'llist_for_each_safe'
- 'media_device_for_each_entity'
- 'media_device_for_each_intf'
- 'media_device_for_each_link'
- 'media_device_for_each_pad'
- 'nanddev_io_for_each_page'
- 'netdev_for_each_lower_dev'
- 'netdev_for_each_lower_private'
- 'netdev_for_each_lower_private_rcu'
- 'netdev_for_each_mc_addr'
- 'netdev_for_each_uc_addr'
- 'netdev_for_each_upper_dev_rcu'
- 'netdev_hw_addr_list_for_each'
- 'nft_rule_for_each_expr'
- 'nla_for_each_attr'
- 'nla_for_each_nested'
- 'nlmsg_for_each_attr'
- 'nlmsg_for_each_msg'
- 'nr_neigh_for_each'
- 'nr_neigh_for_each_safe'
- 'nr_node_for_each'
- 'nr_node_for_each_safe'
- 'of_for_each_phandle'
- 'of_property_for_each_string'
- 'of_property_for_each_u32'
- 'pci_bus_for_each_resource'
- 'ping_portaddr_for_each_entry'
- 'plist_for_each'
- 'plist_for_each_continue'
- 'plist_for_each_entry'
- 'plist_for_each_entry_continue'
- 'plist_for_each_entry_safe'
- 'plist_for_each_safe'
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- 'radix_tree_for_each_slot'
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- 'resource_list_for_each_entry'
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- 'rhl_for_each_entry_rcu'
- 'rhl_for_each_rcu'
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- '__rq_for_each_bio'
- 'rq_for_each_bvec'
- 'rq_for_each_segment'
- 'scsi_for_each_prot_sg'
- 'scsi_for_each_sg'
- 'sctp_for_each_hentry'
- 'sctp_skb_for_each'
- 'shdma_for_each_chan'
- '__shost_for_each_device'
- 'shost_for_each_device'
- 'sk_for_each'
- 'sk_for_each_bound'
- 'sk_for_each_entry_offset_rcu'
- 'sk_for_each_from'
- 'sk_for_each_rcu'
- 'sk_for_each_safe'
- 'sk_nulls_for_each'
- 'sk_nulls_for_each_from'
- 'sk_nulls_for_each_rcu'
- 'snd_array_for_each'
- 'snd_pcm_group_for_each_entry'
- 'snd_soc_dapm_widget_for_each_path'
- 'snd_soc_dapm_widget_for_each_path_safe'
- 'snd_soc_dapm_widget_for_each_sink_path'
- 'snd_soc_dapm_widget_for_each_source_path'
- 'tb_property_for_each'
- 'tcf_exts_for_each_action'
- 'udp_portaddr_for_each_entry'
- 'udp_portaddr_for_each_entry_rcu'
- 'usb_hub_for_each_child'
- 'v4l2_device_for_each_subdev'
- 'v4l2_m2m_for_each_dst_buf'
- 'v4l2_m2m_for_each_dst_buf_safe'
- 'v4l2_m2m_for_each_src_buf'
- 'v4l2_m2m_for_each_src_buf_safe'
- 'virtio_device_for_each_vq'
- 'xa_for_each'
- 'xa_for_each_marked'
- 'xa_for_each_start'
- 'xas_for_each'
- 'xas_for_each_conflict'
- 'xas_for_each_marked'
- 'zorro_for_each_dev'
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...
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/.gitignore 0000664 0000000 0000000 00000000020 13707547500 0025311 0 ustar 00root root 0000000 0000000 spec-core-fpga.h spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/Kbuild 0000664 0000000 0000000 00000002522 13707547500 0024467 0 ustar 00root root 0000000 0000000 # add versions of supermodule. It is useful when spec is included as sub-module
# of a bigger project that we want to track
ifdef CONFIG_SUPER_REPO
ifdef CONFIG_SUPER_REPO_VERSION
SUBMODULE_VERSIONS += MODULE_INFO(version_$(CONFIG_SUPER_REPO),\"$(CONFIG_SUPER_REPO_VERSION)\");
endif
endif
# add versions of used submodules
ccflags-y += -DADDITIONAL_VERSIONS="$(SUBMODULE_VERSIONS)"
ccflags-y += -DVERSION=\"$(VERSION)\"
ccflags-y += -Wall -Werror
ccflags-y += -I$(FPGA_MGR_ABS)/include
ccflags-$(CONFIG_FPGA_MGR_BACKPORT) += -DCONFIG_FPGA_MGR_BACKPORT
ccflags-y += -I$(FMC_ABS)/include
ccflags-y += -I$(SPI_ABS)/include
# priority to I2C, FMC headers from our sources
LINUXINCLUDE := -I$(FMC_ABS)/include -I$(FMC_ABS)/include/linux -I$(I2C_ABS)/include -I$(I2C_ABS)/include/linux $(LINUXINCLUDE)
ifneq ($(FPGA_MGR_ABS), "")
FPGA_MGR_BACKPORT_INCLUDE := -I$(FPGA_MGR_ABS)/include
FPGA_MGR_BACKPORT_INCLUDE += -I$(FPGA_MGR_ABS)/include/linux
LINUXINCLUDE := $(FPGA_MGR_BACKPORT_INCLUDE) $(LINUXINCLUDE)
KBUILD_EXTRA_SYMBOLS += $(FPGA_MGR_ABS)/drivers/fpga/Module.symvers
endif
KBUILD_EXTRA_SYMBOLS += $(FMC_ABS)/drivers/fmc/Module.symvers
obj-m := spec-fmc-carrier.o
obj-m += gn412x-gpio.o
obj-m += gn412x-fcl.o
obj-m += spec-gn412x-dma.o
spec-fmc-carrier-objs := spec-core.o
spec-fmc-carrier-objs += spec-core-fpga.o
spec-fmc-carrier-objs += spec-compat.o
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/Makefile 0000664 0000000 0000000 00000004573 13707547500 0025002 0 ustar 00root root 0000000 0000000 -include Makefile.specific
-include $(REPO_PARENT)/parent_common.mk
KVERSION ?= $(shell uname -r)
LINUX ?= /lib/modules/$(KVERSION)/build
TOP_DIR ?= $(shell pwd)/../..
HDL_DIR ?= $(TOP_DIR)/hdl
DKMS ?= 0
ifndef (CONFIG_FPGA_MGR_BACKPORT)
ifeq ($(shell test $(shell uname -p) \> "4.4"), 0)
CONFIG_FPGA_MGR_BACKPORT := n
else
CONFIG_FPGA_MGR_BACKPORT := y
endif
endif
ifeq ($(DKMS), 1)
FPGA_MGR_VERSION ?= $(shell basename $(shell ls -d $(DKMSTREE)/fpga_mgr/* | grep -E "\/[0-9]+\.[0-9]+\.[0-9]+" | sort -V | tail -n 1))
FMC_VERSION ?= $(shell basename $(shell ls -d $(DKMSTREE)/fmc/* | grep -E "\/[0-9]+\.[0-9]+\.[0-9]+" | sort -V | tail -n 1))
I2C_VERSION ?= $(shell basename $(shell ls -d $(DKMSTREE)/i2c-ocores/* | grep -E "\/[0-9]+\.[0-9]+\.[0-9]+" | sort -V | tail -n 1))
SPI_VERSION ?= $(shell basename $(shell ls -d $(DKMSTREE)/spi-ocores/* | grep -E "\/[0-9]+\.[0-9]+\.[0-9]+" | sort -V | tail -n 1))
FPGA_MGR ?= $(DKMSTREE)/fpga_mgr/$(FPGA_MGR_VERSION)/source
FMC ?= $(DKMSTREE)/fmc/$(FMC_VERSION)/source
I2C ?= $(DKMSTREE)/i2c-ocores/$(I2C_VERSION)/source
SPI ?= $(DKMSTREE)/spi-ocores/$(SPI_VERSION)/source
endif
ifdef REPO_PARENT
FPGA_MGR ?= $(REPO_PARENT)/fpga-mgr-backport/
FMC ?= $(REPO_PARENT)/fmc-sw/
I2C ?= $(REPO_PARENT)/general-cores/software/i2c-ocores/
SPI ?= $(REPO_PARENT)/general-cores/software/spi-ocores/
endif
ifndef FPGA_MGR
$(error "Missing FPGA_MGR environment variable")
endif
ifndef FMC
$(error "Missing FMC environment variable")
endif
ifndef I2C
$(error "Missing I2C environment variable")
endif
ifndef SPI
$(error "Missing SPI environment variable")
endif
FPGA_MGR_ABS ?= $(abspath $(FPGA_MGR))
FMC_ABS ?= $(abspath $(FMC))
I2C_ABS ?= $(abspath $(I2C))
SPI_ABS ?= $(abspath $(SPI))
VERSION = $(shell git describe --dirty --long --tags)
CHEBY ?= /usr/bin/cheby
all: modules
.PHONY: all modules clean help install modules_install coccicheck spec-core-fpga.h
spec-core-fpga.h:
ifeq ($(DKMS), 0)
$(CHEBY) --gen-c -i $(HDL_DIR)/rtl/spec_base_regs.cheby > $@
endif
clean-spec-core-fpga.h:
ifeq ($(DKMS), 0)
rm -f spec-core-fpga.h
endif
install: modules_install
clean: clean-spec-core-fpga.h
modules help coccicheck modules_install clean: spec-core-fpga.h
$(MAKE) -C $(LINUX) M=$(shell pwd) \
VERSION=$(VERSION) \
FPGA_MGR_ABS=$(FPGA_MGR_ABS) \
CONFIG_FPGA_MGR_BACKPORT=$(CONFIG_FPGA_MGR_BACKPORT) \
FMC_ABS=$(FMC_ABS) \
I2C_ABS=$(I2C_ABS) \
SPI_ABS=$(SPI_ABS) \
$@
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/gn412x-fcl.c 0000664 0000000 0000000 00000034011 13707547500 0025261 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#include
#include
#include
#include
#include
#include "spec.h"
#include "spec-compat.h"
#include "gn412x.h"
#define FCL_CTRL_START_FSM BIT(0)
#define FCL_CTRL_SPRI_EN BIT(1)
#define FCL_CTRL_FSM_EN BIT(2)
#define FCL_CTRL_SEND_CFG_DATA BIT(3)
#define FCL_CTRL_LAST_BYTE_CNT_1 (0x3 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_2 (0x2 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_3 (0x1 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_4 (0x0 << 4)
#define FCL_CTRL_RESET BIT(6)
#define FCL_CTRL_DATA_PUSH_COMP BIT(7)
#define FCL_CTRL_SPRI_CLK_STOP_EN BIT(8)
#define FCL_SPRI_CLKOUT BIT(0)
#define FCL_SPRI_DATAOUT BIT(1)
#define FCL_SPRI_CONFIG BIT(2)
#define FCL_SPRI_DONE BIT(3)
#define FCL_SPRI_XI_SWAP BIT(4)
#define FCL_SPRI_STATUS BIT(5)
#define FCL_IRQ_SPRI_STATUS BIT(0)
#define FCL_IRQ_TIMER BIT(1)
#define FCL_IRQ_CONFIG_ERROR BIT(2)
#define FCL_IRQ_CONFIG_DONE BIT(3)
#define FCL_IRQ_FIFO_UNDRFL BIT(4)
#define FCL_IRQ_FIFO_HALFFULL BIT(5)
/* Compatibility layer */
static int gn412x_fcl_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count);
static int gn412x_fcl_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info);
static int compat_get_fpga_last_word_size(struct fpga_image_info *info,
size_t count)
{
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
return count;
#else
return info ? info->count : count;
#endif
}
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
static int compat_gn412x_fcl_write_init(struct fpga_manager *mgr,
u32 flags,
const char *buf, size_t count)
{
return gn412x_fcl_write_init(mgr, NULL, buf, count);
}
static int compat_gn412x_fcl_write_complete(struct fpga_manager *mgr,
u32 flags)
{
return gn412x_fcl_write_complete(mgr, NULL);
}
#else
static int compat_gn412x_fcl_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count)
{
return gn412x_fcl_write_init(mgr, info, buf, count);
}
static int compat_gn412x_fcl_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info)
{
return gn412x_fcl_write_complete(mgr, info);
}
#endif
#if KERNEL_VERSION(4, 18, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
static struct fpga_manager *compat_fpga_mgr_create(struct device *dev,
const char *name,
const struct fpga_manager_ops *mops,
void *priv)
{
int err;
err = fpga_mgr_register(dev, name, mops, priv);
if (err)
return NULL;
return (struct fpga_manager *)dev;
}
static void compat_fpga_mgr_free(struct fpga_manager *mgr)
{
fpga_mgr_unregister((struct device *)mgr);
}
static int compat_fpga_mgr_register(struct fpga_manager *mgr)
{
return mgr ? 0 : 1;
}
static void compat_fpga_mgr_unregister(struct fpga_manager *mgr)
{
return mgr ? 0 : 1;
}
#else
static struct fpga_manager *compat_fpga_mgr_create(struct device *dev,
const char *name,
const struct fpga_manager_ops *mops,
void *priv)
{
return fpga_mgr_create(dev, name, mops, priv);
}
static void compat_fpga_mgr_free(struct fpga_manager *mgr)
{
fpga_mgr_free(mgr);
}
static int compat_fpga_mgr_register(struct fpga_manager *mgr)
{
return fpga_mgr_register(mgr);
}
static void compat_fpga_mgr_unregister(struct fpga_manager *mgr)
{
fpga_mgr_unregister(mgr);
}
#endif
/* The real code */
/**
* struct gn412x_dev GN412X device descriptor
* @compl: for IRQ testing
* @int_cfg_gpio: INT_CFG used for GPIO interrupts
*/
struct gn412x_fcl_dev {
void __iomem *mem;
struct fpga_manager *mgr;
struct dentry *dbg_dir;
#define GN412X_DBG_REG_NAME "regs"
struct dentry *dbg_reg;
struct debugfs_regset32 dbg_reg32;
};
#define REG32(_name, _offset) {.name = _name, .offset = _offset}
static const struct debugfs_reg32 gn412x_debugfs_reg32[] = {
REG32("FCL_CTRL", FCL_CTRL),
REG32("FCL_STATUS", FCL_STATUS),
REG32("FCL_IODATA_IN", FCL_IODATA_IN),
REG32("FCL_IODATA_OUT", FCL_IODATA_OUT),
REG32("FCL_EN", FCL_EN),
REG32("FCL_TIMER0", FCL_TIMER_0),
REG32("FCL_TIMER1", FCL_TIMER_1),
REG32("FCL_CLK_DIV", FCL_CLK_DIV),
REG32("FCL_IRQ", FCL_IRQ),
REG32("FCL_TIMER_CTRL", FCL_TIMER_CTRL),
REG32("FCL_IM", FCL_IM),
REG32("FCL_TIMER2_0", FCL_TIMER2_0),
REG32("FCL_TIMER2_1", FCL_TIMER2_1),
REG32("FCL_DBG_STS", FCL_DBG_STS),
};
static int gn4124_dbg_init(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x = platform_get_drvdata(pdev);
struct dentry *dir, *file;
int err;
dir = debugfs_create_dir(dev_name(&pdev->dev), NULL);
if (IS_ERR_OR_NULL(dir)) {
err = PTR_ERR(dir);
dev_warn(&pdev->dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(&pdev->dev), err);
goto err_dir;
}
gn412x->dbg_reg32.regs = gn412x_debugfs_reg32;
gn412x->dbg_reg32.nregs = ARRAY_SIZE(gn412x_debugfs_reg32);
gn412x->dbg_reg32.base = gn412x->mem;
file = debugfs_create_regset32(GN412X_DBG_REG_NAME, 0200,
dir, &gn412x->dbg_reg32);
if (IS_ERR_OR_NULL(file)) {
err = PTR_ERR(file);
dev_warn(&pdev->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
GN412X_DBG_REG_NAME, err);
goto err_reg32;
}
gn412x->dbg_dir = dir;
gn412x->dbg_reg = file;
return 0;
err_reg32:
debugfs_remove_recursive(dir);
err_dir:
return err;
}
static void gn4124_dbg_exit(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x = platform_get_drvdata(pdev);
debugfs_remove_recursive(gn412x->dbg_dir);
}
static uint32_t gn412x_ioread32(struct gn412x_fcl_dev *gn412x,
int reg)
{
return ioread32(gn412x->mem + reg);
}
static void gn412x_iowrite32(struct gn412x_fcl_dev *gn412x,
uint32_t val, int reg)
{
return iowrite32(val, gn412x->mem + reg);
}
static inline uint8_t reverse_bits8(uint8_t x)
{
x = ((x >> 1) & 0x55) | ((x & 0x55) << 1);
x = ((x >> 2) & 0x33) | ((x & 0x33) << 2);
x = ((x >> 4) & 0x0f) | ((x & 0x0f) << 4);
return x;
}
static uint32_t unaligned_bitswap_le32(const uint32_t *ptr32)
{
static uint32_t tmp32;
static uint8_t *tmp8 = (uint8_t *) &tmp32;
static uint8_t *ptr8;
ptr8 = (uint8_t *) ptr32;
*(tmp8 + 0) = reverse_bits8(*(ptr8 + 0));
*(tmp8 + 1) = reverse_bits8(*(ptr8 + 1));
*(tmp8 + 2) = reverse_bits8(*(ptr8 + 2));
*(tmp8 + 3) = reverse_bits8(*(ptr8 + 3));
return tmp32;
}
/**
* it resets the FPGA
*/
static void gn4124_fpga_reset(struct gn412x_fcl_dev *gn412x)
{
uint32_t reg;
/* After reprogramming, reset the FPGA using the gennum register */
reg = gn412x_ioread32(gn412x, GNPCI_SYS_CFG_SYSTEM);
/*
* This _fucking_ register must be written with extreme care,
* becase some fields are "protected" and some are not. *hate*
*/
gn412x_iowrite32(gn412x, (reg & ~0xffff) | 0x3fff,
GNPCI_SYS_CFG_SYSTEM);
gn412x_iowrite32(gn412x, (reg & ~0xffff) | 0x7fff,
GNPCI_SYS_CFG_SYSTEM);
}
/**
* Initialize the gennum
* @gn412x: gn412x device instance
* @last_word_size: last word size in the FPGA bitstream
*
* Return: 0 on success, otherwise a negative error code
*/
static int gn4124_fpga_fcl_init(struct gn412x_fcl_dev *gn412x,
int last_word_size)
{
uint32_t ctrl, en;
int i;
gn412x_iowrite32(gn412x, 0x00, FCL_CLK_DIV);
gn412x_iowrite32(gn412x, FCL_CTRL_RESET, FCL_CTRL);
i = gn412x_ioread32(gn412x, FCL_CTRL);
if (i != FCL_CTRL_RESET) {
pr_err("%s: %i: error\n", __func__, __LINE__);
return -EIO;
}
gn412x_iowrite32(gn412x, 0x00, FCL_CTRL);
gn412x_iowrite32(gn412x, 0x00, FCL_IRQ); /* clear pending irq */
ctrl = 0;
ctrl |= FCL_CTRL_SPRI_EN;
ctrl |= FCL_CTRL_FSM_EN;
ctrl |= FCL_CTRL_SPRI_CLK_STOP_EN;
switch (last_word_size) {
case 3:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_3;
break;
case 2:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_2;
break;
case 1:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_1;
break;
case 0:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_4;
break;
default: return -EINVAL;
}
gn412x_iowrite32(gn412x, ctrl, FCL_CTRL);
gn412x_iowrite32(gn412x, 0x00, FCL_CLK_DIV);
gn412x_iowrite32(gn412x, 0x00, FCL_TIMER_CTRL);
gn412x_iowrite32(gn412x, 0x10, FCL_TIMER_0);
gn412x_iowrite32(gn412x, 0x00, FCL_TIMER_1);
/*
* Set delay before data and clock is applied by FCL
* after SPRI_STATUS is detected being assert.
*/
gn412x_iowrite32(gn412x, 0x08, FCL_TIMER2_0);
gn412x_iowrite32(gn412x, 0x00, FCL_TIMER2_1);
en = 0;
en |= FCL_SPRI_CLKOUT;
en |= FCL_SPRI_DATAOUT;
en |= FCL_SPRI_CONFIG;
en |= FCL_SPRI_XI_SWAP;
gn412x_iowrite32(gn412x, en, FCL_EN);
ctrl |= FCL_CTRL_START_FSM;
gn412x_iowrite32(gn412x, ctrl, FCL_CTRL);
return 0;
}
/**
* Wait for the FPGA to be configured and ready
* @gn412x: device instance
*
* Return: 0 on success,-ETIMEDOUT on failure
*/
static int gn4124_fpga_fcl_waitdone(struct gn412x_fcl_dev *gn412x)
{
unsigned long j;
j = jiffies + 2 * HZ;
while (1) {
uint32_t val = gn412x_ioread32(gn412x, FCL_IRQ);
/* Done */
if (val & 0x8)
return 0;
/* Fail */
if (val & 0x4)
return -EIO;
/* Timeout */
if (time_after(jiffies, j))
return -ETIMEDOUT;
udelay(100);
}
}
/**
* It configures the FPGA with the given image
* @gn412x: gn412x instance
* @data: FPGA configuration code
* @len: image length in bytes
*
* Return: 0 on success, otherwise a negative error code
*/
static int gn4124_fpga_load(struct gn412x_fcl_dev *gn412x,
const void *data, int len)
{
int size32 = (len + 3) >> 2;
int done = 0, wrote = 0;
const uint32_t *data32 = data;
while (size32 > 0) {
/* Check to see if FPGA configuation has error */
int i = gn412x_ioread32(gn412x, FCL_IRQ);
if ((i & FCL_IRQ_CONFIG_DONE) && wrote) {
done = 1;
pr_err("%s: %i: done after %i%i\n",
__func__, __LINE__,
wrote, ((len + 3) >> 2));
} else if ((i & FCL_IRQ_CONFIG_ERROR) && !done) {
pr_err("%s: %i: error after %i/%i\n",
__func__, __LINE__,
wrote, ((len + 3) >> 2));
return -EIO;
}
/* Wait until at least 1/2 of the fifo is empty */
while (gn412x_ioread32(gn412x, FCL_IRQ) & FCL_IRQ_FIFO_HALFFULL)
;
/* Write a few dwords into FIFO at a time. */
for (i = 0; size32 && i < 32; i++) {
gn412x_iowrite32(gn412x, unaligned_bitswap_le32(data32),
FCL_FIFO);
data32++; size32--; wrote++;
}
}
return 0;
}
/**
* It notifies the gennum that the configuration is over
* @gn412x: gn412x device instance
*/
static void gn4124_fpga_fcl_complete(struct gn412x_fcl_dev *gn412x)
{
uint32_t ctrl = 0;
ctrl |= FCL_CTRL_SPRI_EN;
ctrl |= FCL_CTRL_FSM_EN;
ctrl |= FCL_CTRL_DATA_PUSH_COMP;
ctrl |= FCL_CTRL_SPRI_CLK_STOP_EN;
gn412x_iowrite32(gn412x, ctrl, FCL_CTRL);
}
static enum fpga_mgr_states gn412x_fcl_state(struct fpga_manager *mgr)
{
return mgr->state;
}
static int gn412x_fcl_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count)
{
struct gn412x_fcl_dev *gn412x = mgr->priv;
int err = 0, last_word_size;
last_word_size = compat_get_fpga_last_word_size(info, count) & 0x3;
err = gn4124_fpga_fcl_init(gn412x, last_word_size);
if (err < 0)
goto err;
return 0;
err:
return err;
}
static int gn412x_fcl_write(struct fpga_manager *mgr,
const char *buf, size_t count)
{
struct gn412x_fcl_dev *gn412x = mgr->priv;
return gn4124_fpga_load(gn412x, buf, count);
}
static void gn4124_fcl_reset(struct gn412x_fcl_dev *gn412x)
{
gn412x_iowrite32(gn412x, 0x00, FCL_CTRL);
gn412x_iowrite32(gn412x, 0x00, FCL_EN);
}
static int gn412x_fcl_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info)
{
struct gn412x_fcl_dev *gn412x = mgr->priv;
int err;
gn4124_fpga_fcl_complete(gn412x);
err = gn4124_fpga_fcl_waitdone(gn412x);
if (err < 0)
return err;
gn4124_fcl_reset(gn412x);
gn4124_fpga_reset(gn412x);
return 0;
}
static void gn412x_fcl_fpga_remove(struct fpga_manager *mgr)
{
/* do nothing */
}
static const struct fpga_manager_ops gn412x_fcl_ops = {
compat_fpga_ops_initial_header_size
compat_fpga_ops_groups
.state = gn412x_fcl_state,
.write_init = compat_gn412x_fcl_write_init,
.write = gn412x_fcl_write,
.write_complete = compat_gn412x_fcl_write_complete,
.fpga_remove = gn412x_fcl_fpga_remove,
};
static int gn412x_fcl_probe(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x;
struct resource *r;
int err;
gn412x = kzalloc(sizeof(*gn412x), GFP_KERNEL);
if (!gn412x)
return -ENOMEM;
platform_set_drvdata(pdev, gn412x);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(&pdev->dev, "Missing memory resource\n");
err = -EINVAL;
goto err_res_mem;
}
gn412x->mem = ioremap(r->start, resource_size(r));
if (!gn412x->mem) {
err = -EADDRNOTAVAIL;
goto err_map;
}
gn4124_fcl_reset(gn412x);
gn4124_dbg_init(pdev);
gn412x->mgr = compat_fpga_mgr_create(&pdev->dev,
dev_name(&pdev->dev),
&gn412x_fcl_ops, gn412x);
if (!gn412x->mgr) {
err = -EPERM;
goto err_fpga_create;
}
err = compat_fpga_mgr_register(gn412x->mgr);
if (err)
goto err_fpga_reg;
return 0;
err_fpga_reg:
compat_fpga_mgr_free(gn412x->mgr);
err_fpga_create:
gn4124_dbg_exit(pdev);
iounmap(gn412x->mem);
err_map:
err_res_mem:
kfree(gn412x);
platform_set_drvdata(pdev, NULL);
return err;
}
static int gn412x_fcl_remove(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x = platform_get_drvdata(pdev);
if (!gn412x->mgr)
return -ENODEV;
compat_fpga_mgr_unregister(gn412x->mgr);
compat_fpga_mgr_free(gn412x->mgr);
gn4124_dbg_exit(pdev);
iounmap(gn412x->mem);
kfree(gn412x);
platform_set_drvdata(pdev, NULL);
dev_dbg(&pdev->dev, "%s\n", __func__);
return 0;
}
static const struct platform_device_id gn412x_fcl_id[] = {
{
.name = "gn412x-fcl",
},
{}, /* last */
};
static struct platform_driver gn412x_fcl_platform_driver = {
.driver = {
.name = KBUILD_MODNAME,
},
.probe = gn412x_fcl_probe,
.remove = gn412x_fcl_remove,
.id_table = gn412x_fcl_id,
};
module_platform_driver(gn412x_fcl_platform_driver);
MODULE_AUTHOR("Federico Vaga ");
MODULE_DESCRIPTION("GN412X FCL driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(VERSION);
MODULE_DEVICE_TABLE(platform, gn412x_fcl_id);
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/gn412x-gpio.c 0000664 0000000 0000000 00000042412 13707547500 0025457 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#include
#include
#include
#include "spec.h"
#include "gn412x.h"
#include "platform_data/gn412x-gpio.h"
/**
* struct gn412x_gpio_dev GN412X device descriptor
* @compl: for IRQ testing
* @int_cfg_gpio: INT_CFG used for GPIO interrupts
*/
struct gn412x_gpio_dev {
void __iomem *mem;
struct gpio_chip gpiochip;
struct irq_chip irqchip;
struct completion compl;
struct gn412x_platform_data *pdata;
struct dentry *dbg_dir;
#define GN412X_DBG_REG_NAME "regs"
struct dentry *dbg_reg;
struct debugfs_regset32 dbg_reg32;
};
static struct gn412x_platform_data gn412x_gpio_pdata_default = {
.int_cfg = 0,
};
static inline struct gn412x_gpio_dev *to_gn412x_gpio_dev_gpio(struct gpio_chip *chip)
{
return container_of(chip, struct gn412x_gpio_dev, gpiochip);
}
enum gn412x_gpio_versions {
GN412X_VER = 0,
};
enum htvic_mem_resources {
GN412X_MEM_BASE = 0,
};
#define REG32(_name, _offset) {.name = _name, .offset = _offset}
static const struct debugfs_reg32 gn412x_debugfs_reg32[] = {
REG32("INT_CTRL", GNINT_CTRL),
REG32("INT_STAT", GNINT_STAT),
REG32("INT_CFG0", GNINT_CFG_0),
REG32("INT_CFG1", GNINT_CFG_1),
REG32("INT_CFG2", GNINT_CFG_2),
REG32("INT_CFG3", GNINT_CFG_3),
REG32("INT_CFG4", GNINT_CFG_4),
REG32("INT_CFG5", GNINT_CFG_5),
REG32("INT_CFG6", GNINT_CFG_6),
REG32("INT_CFG7", GNINT_CFG_7),
REG32("GPIO_BYPASS_MODE", GNGPIO_BYPASS_MODE),
REG32("GPIO_DIRECTION_MODE", GNGPIO_DIRECTION_MODE),
REG32("GPIO_OUTPUT_ENABLE", GNGPIO_OUTPUT_ENABLE),
REG32("GPIO_OUTPUT_VALUE", GNGPIO_OUTPUT_VALUE),
REG32("GPIO_INPUT_VALUE", GNGPIO_INPUT_VALUE),
REG32("GPIO_INT_MASK", GNGPIO_INT_MASK),
REG32("GPIO_INT_MASK_CLR", GNGPIO_INT_MASK_CLR),
REG32("GPIO_INT_MASK_SET", GNGPIO_INT_MASK_SET),
REG32("GPIO_INT_STATUS", GNGPIO_INT_STATUS),
REG32("GPIO_INT_TYPE", GNGPIO_INT_TYPE),
REG32("GPIO_INT_VALUE", GNGPIO_INT_VALUE),
REG32("GPIO_INT_ON_ANY", GNGPIO_INT_ON_ANY),
};
static int gn412x_dbg_init(struct gn412x_gpio_dev *gn412x)
{
struct dentry *dir, *file;
int err;
#if KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE
struct device *dev = gn412x->gpiochip.dev;
#else
struct device *dev = gn412x->gpiochip.parent;
#endif
dir = debugfs_create_dir(dev_name(dev), NULL);
if (IS_ERR_OR_NULL(dir)) {
err = PTR_ERR(dir);
dev_warn(dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(dev), err);
goto err_dir;
}
gn412x->dbg_reg32.regs = gn412x_debugfs_reg32;
gn412x->dbg_reg32.nregs = ARRAY_SIZE(gn412x_debugfs_reg32);
gn412x->dbg_reg32.base = gn412x->mem;
file = debugfs_create_regset32(GN412X_DBG_REG_NAME, 0200,
dir, &gn412x->dbg_reg32);
if (IS_ERR_OR_NULL(file)) {
err = PTR_ERR(file);
dev_warn(dev,
"Cannot create debugfs file \"%s\" (%d)\n",
GN412X_DBG_REG_NAME, err);
goto err_reg32;
}
gn412x->dbg_dir = dir;
gn412x->dbg_reg = file;
return 0;
err_reg32:
debugfs_remove_recursive(dir);
err_dir:
return err;
}
static void gn412x_dbg_exit(struct gn412x_gpio_dev *gn412x)
{
debugfs_remove_recursive(gn412x->dbg_dir);
}
static uint32_t gn412x_ioread32(struct gn412x_gpio_dev *gn412x,
int reg)
{
return ioread32(gn412x->mem + reg);
}
static void gn412x_iowrite32(struct gn412x_gpio_dev *gn412x,
uint32_t val, int reg)
{
return iowrite32(val, gn412x->mem + reg);
}
static int gn412x_gpio_reg_read(struct gpio_chip *chip,
int reg, unsigned int offset)
{
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(chip);
return gn412x_ioread32(gn412x, reg) & BIT(offset);
}
static void gn412x_gpio_reg_write(struct gpio_chip *chip,
int reg, unsigned int offset, int value)
{
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(chip);
uint32_t regval;
regval = gn412x_ioread32(gn412x, reg);
if (value)
regval |= BIT(offset);
else
regval &= ~BIT(offset);
gn412x_iowrite32(gn412x, regval, reg);
}
/**
* Enable GPIO interrupts
* @gn412x gn412x device
*
* Return: 0 on success, otherwise a negative error number
*/
static void gn412x_gpio_int_cfg_enable(struct gn412x_gpio_dev *gn412x)
{
uint32_t int_cfg;
int_cfg = gn412x_ioread32(gn412x, GNINT_CFG(gn412x->pdata->int_cfg));
int_cfg |= GNINT_STAT_GPIO;
gn412x_iowrite32(gn412x, int_cfg, GNINT_CFG(gn412x->pdata->int_cfg));
}
/**
* Disable GPIO interrupts from a single configuration space
* @gn412x gn412x device
*/
static void gn412x_gpio_int_cfg_disable(struct gn412x_gpio_dev *gn412x)
{
uint32_t int_cfg;
int_cfg = gn412x_ioread32(gn412x, GNINT_CFG(gn412x->pdata->int_cfg));
int_cfg &= ~GNINT_STAT_GPIO;
gn412x_iowrite32(gn412x, int_cfg, GNINT_CFG(gn412x->pdata->int_cfg));
}
static int gn412x_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
int val;
#if KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE
struct device *dev = chip->dev;
#else
struct device *dev = chip->parent;
#endif
val = gn412x_gpio_reg_read(chip, GNGPIO_BYPASS_MODE, offset);
if (val) {
dev_err(dev, "%s GPIO %d is in BYPASS mode\n",
chip->label, offset);
return -EBUSY;
}
return 0;
}
static void gn412x_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
/* set it as input to avoid to drive anything */
gn412x_gpio_reg_write(chip, GNGPIO_DIRECTION_MODE, offset, 1);
}
static int gn412x_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
return !!gn412x_gpio_reg_read(chip, GNGPIO_DIRECTION_MODE, offset);
}
static int gn412x_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
gn412x_gpio_reg_write(chip, GNGPIO_DIRECTION_MODE, offset, 1);
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_ENABLE, offset, 0);
return 0;
}
static int gn412x_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
gn412x_gpio_reg_write(chip, GNGPIO_DIRECTION_MODE, offset, 0);
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_ENABLE, offset, 1);
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_VALUE, offset, value);
return 0;
}
static int gn412x_gpio_get(struct gpio_chip *chip,
unsigned int offset)
{
return gn412x_gpio_reg_read(chip, GNGPIO_INPUT_VALUE, offset);
}
static void gn412x_gpio_set(struct gpio_chip *chip,
unsigned int offset, int value)
{
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_VALUE, offset, value);
}
/**
* (disable)
*/
static void gn412x_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(gc);
gn412x_iowrite32(gn412x, BIT(d->hwirq), GNGPIO_INT_MASK_SET);
}
/**
* (enable)
*/
static void gn412x_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(gc);
gn412x_iowrite32(gn412x, BIT(d->hwirq), GNGPIO_INT_MASK_CLR);
}
static int gn412x_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
#if KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE
struct device *dev = gc->dev;
#else
struct device *dev = gc->parent;
#endif
/*
* detect errors:
* - level and edge together cannot work
*/
if ((flow_type & IRQ_TYPE_LEVEL_MASK) &&
(flow_type & IRQ_TYPE_EDGE_BOTH)) {
dev_err(dev,
"Impossible to set GPIO IRQ %ld to both LEVEL and EDGE (0x%x)\n",
d->hwirq, flow_type);
return -EINVAL;
}
/* Configure: level or edge (default)? */
if (flow_type & IRQ_TYPE_LEVEL_MASK) {
gn412x_gpio_reg_write(gc, GNGPIO_INT_TYPE, d->hwirq, 1);
} else {
gn412x_gpio_reg_write(gc, GNGPIO_INT_TYPE, d->hwirq, 0);
/* if we want to trigger on any edge */
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
gn412x_gpio_reg_write(gc, GNGPIO_INT_ON_ANY,
d->hwirq, 1);
}
/* Configure: level-low or falling-edge, level-high or raising-edge */
if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
gn412x_gpio_reg_write(gc, GNGPIO_INT_VALUE, d->hwirq, 0);
else
gn412x_gpio_reg_write(gc, GNGPIO_INT_VALUE, d->hwirq, 1);
return IRQ_SET_MASK_OK;
}
/**
* A new IRQ interrupt has been requested
* @d IRQ related data
*
* We need to set the GPIO line to be input and disable completely any
* kind of output. We do not want any alternative function (bypass mode).
*/
static unsigned int gn412x_gpio_irq_startup(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
gn412x_gpio_reg_write(gc, GNGPIO_BYPASS_MODE, d->hwirq, 0);
gn412x_gpio_reg_write(gc, GNGPIO_DIRECTION_MODE, d->hwirq, 1);
gn412x_gpio_reg_write(gc, GNGPIO_OUTPUT_ENABLE, d->hwirq, 0);
gn412x_gpio_direction_input(gc, d->hwirq);
/* FIXME in the original code we had this? What is it? */
/* !!(gennum_readl(spec, GNGPIO_INPUT_VALUE) & bit); */
gn412x_gpio_irq_unmask(d);
return 0;
}
/**
* It disables the GPIO interrupt by masking it
*/
static void gn412x_gpio_irq_disable(struct irq_data *d)
{
gn412x_gpio_irq_mask(d);
}
static void gn412x_gpio_irq_ack(struct irq_data *d)
{
/*
* based on HW design,there is no need to ack HW
* before handle current irq. But this routine is
* necessary for handle_edge_irq
*/
}
/**
* This will run in hard-IRQ context since we do not have much to do
*/
static irqreturn_t spec_irq_sw_handler(int irq, void *arg)
{
struct gn412x_gpio_dev *gn412x = arg;
/* Ack the interrupts */
gn412x_ioread32(gn412x, GNINT_STAT);
gn412x_iowrite32(gn412x, 0x0000, GNINT_STAT);
complete(&gn412x->compl);
return IRQ_HANDLED;
}
/**
* Handle IRQ from the GPIO block
*/
static irqreturn_t gn412x_gpio_irq_handler_t(int irq, void *arg)
{
struct gn412x_gpio_dev *gn412x = arg;
struct gpio_chip *gc = &gn412x->gpiochip;
unsigned int cascade_irq;
uint32_t gpio_int_status, gpio_int_type;
unsigned long loop;
irqreturn_t ret = IRQ_NONE;
int i;
#if KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE
struct device *dev = gc->dev;
#else
struct device *dev = gc->parent;
#endif
gpio_int_status = gn412x_ioread32(gn412x, GNGPIO_INT_STATUS);
gpio_int_status &= ~gn412x_ioread32(gn412x, GNGPIO_INT_MASK);
if (!gpio_int_status)
goto out_enable_irq;
loop = gpio_int_status;
for_each_set_bit(i, &loop, GN4124_GPIO_MAX) {
#if KERNEL_VERSION(4, 14, 0) > LINUX_VERSION_CODE
cascade_irq = irq_find_mapping(gc->irqdomain, i);
#else
cascade_irq = irq_find_mapping(gc->irq.domain, i);
#endif
dev_dbg(dev, "GPIO: %d, IRQ: %d\n", i, cascade_irq);
/*
* Ok, now we execute the handler for the given IRQ. Please
* note that this is not the action requested by the device
* driver but it is the handler defined during the IRQ mapping
*/
handle_nested_irq(cascade_irq);
}
/*
* Level interrupts are cleared only when they are processed. This
* means that at this point (interrupts have been processed) the
* GPIO_INT_STATUS is still set because it is a sticky bit that got
* set again after our first read because we did not handle yet
* the IRQ. For this reason we have to clear it (defentivelly) by
* reading again the register ...
*/
gpio_int_status = gn412x_ioread32(gn412x, GNGPIO_INT_STATUS);
/*
* ... but like this edge interrupts are lost. So write back
* in the register the status of all pending edge interrupts.
* (NOTE: not yet prooven that it works)
*/
gpio_int_type = gn412x_ioread32(gn412x, GNGPIO_INT_TYPE);
gn412x_iowrite32(gn412x, (gpio_int_status & (~gpio_int_type)),
GNGPIO_INT_STATUS);
ret = IRQ_HANDLED;
out_enable_irq:
/* Re-enable the GPIO interrupts, we are done here */
gn412x_gpio_int_cfg_enable(gn412x);
return ret;
}
static irqreturn_t gn412x_gpio_irq_handler_h(int irq, void *arg)
{
struct gn412x_gpio_dev *gn412x = arg;
uint32_t int_stat, int_cfg;
int_cfg = gn412x_ioread32(gn412x, GNINT_CFG(gn412x->pdata->int_cfg));
int_stat = gn412x_ioread32(gn412x, GNINT_STAT);
if (unlikely(!(int_stat & int_cfg)))
return IRQ_NONE;
if (unlikely(int_stat & GNINT_STAT_SW_ALL)) /* only for testing */
return spec_irq_sw_handler(irq, gn412x);
/*
* Do not listen to new interrupts while handling the current GPIOs.
* This may take a while since the chain behind each GPIO can be long.
* If the IRQ behind is level, we do not want this IRQ handeler to be
* called continuously. But on the other hand we do not want other
* devices sharing the same IRQ to wait for us; just to play safe,
* let's disable interrupts. Within the thread we will re-enable them
* when we are ready (like IRQF_ONESHOT).
*/
gn412x_gpio_int_cfg_disable(gn412x);
return IRQ_WAKE_THREAD;
}
static void gn412x_gpio_irq_set_nested_thread(struct gn412x_gpio_dev *gn412x,
unsigned int gpio, bool nest)
{
int irq;
#if KERNEL_VERSION(4, 14, 0) > LINUX_VERSION_CODE
irq = irq_find_mapping(gn412x->gpiochip.irqdomain, gpio);
#else
irq = irq_find_mapping(gn412x->gpiochip.irq.domain, gpio);
#endif
irq_set_nested_thread(irq, nest);
}
static void gn412x_gpio_irq_set_nested_thread_all(struct gn412x_gpio_dev *gn412x,
bool nest)
{
int i;
for (i = 0; i < GN4124_GPIO_MAX; ++i)
gn412x_gpio_irq_set_nested_thread(gn412x, i, nest);
}
static int gn412x_gpio_probe(struct platform_device *pdev)
{
struct gn412x_gpio_dev *gn412x;
struct resource *r;
int err;
gn412x = kzalloc(sizeof(*gn412x), GFP_KERNEL);
if (!gn412x)
return -ENOMEM;
platform_set_drvdata(pdev, gn412x);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(&pdev->dev, "Missing memory resource\n");
err = -EINVAL;
goto err_res_mem;
}
gn412x->mem = ioremap(r->start, resource_size(r));
if (!gn412x->mem) {
err = -EADDRNOTAVAIL;
goto err_map;
}
gn412x->pdata = dev_get_platdata(&pdev->dev);
if (!gn412x->pdata) {
dev_warn(&pdev->dev, "Missing platform data, use default\n");
gn412x->pdata = &gn412x_gpio_pdata_default;
}
gn412x_iowrite32(gn412x, 0, GNGPIO_BYPASS_MODE);
gn412x_gpio_int_cfg_disable(gn412x);
gn412x_iowrite32(gn412x, 0xFFFF, GNGPIO_INT_MASK_SET);
gn412x->irqchip.name = "GN412X-GPIO",
gn412x->irqchip.irq_startup = gn412x_gpio_irq_startup,
gn412x->irqchip.irq_disable = gn412x_gpio_irq_disable,
gn412x->irqchip.irq_mask = gn412x_gpio_irq_mask,
gn412x->irqchip.irq_unmask = gn412x_gpio_irq_unmask,
gn412x->irqchip.irq_set_type = gn412x_gpio_irq_set_type,
gn412x->irqchip.irq_ack = gn412x_gpio_irq_ack,
#if KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE
gn412x->gpiochip.dev = &pdev->dev;
#else
gn412x->gpiochip.parent = &pdev->dev;
#endif
gn412x->gpiochip.label = "gn412x-gpio";
gn412x->gpiochip.owner = THIS_MODULE;
gn412x->gpiochip.request = gn412x_gpio_request;
gn412x->gpiochip.free = gn412x_gpio_free;
gn412x->gpiochip.get_direction = gn412x_gpio_get_direction;
gn412x->gpiochip.direction_input = gn412x_gpio_direction_input;
gn412x->gpiochip.direction_output = gn412x_gpio_direction_output;
gn412x->gpiochip.get = gn412x_gpio_get;
gn412x->gpiochip.set = gn412x_gpio_set;
gn412x->gpiochip.base = -1;
gn412x->gpiochip.ngpio = GN4124_GPIO_MAX;
gn412x->gpiochip.can_sleep = 0;
#if KERNEL_VERSION(4, 15, 0) <= LINUX_VERSION_CODE
gn412x->gpiochip.irq.chip = &gn412x->irqchip;
gn412x->gpiochip.irq.first = 0;
gn412x->gpiochip.irq.handler = handle_simple_irq;
gn412x->gpiochip.irq.default_type = IRQ_TYPE_NONE;
gn412x->gpiochip.irq.threaded = true;
#endif
err = gpiochip_add(&gn412x->gpiochip);
if (err)
goto err_add;
#if KERNEL_VERSION(4, 15, 0) > LINUX_VERSION_CODE
err = gpiochip_irqchip_add(&gn412x->gpiochip,
&gn412x->irqchip,
0, handle_simple_irq,
IRQ_TYPE_NONE);
if (err)
goto err_add_irq;
#endif
gn412x_gpio_irq_set_nested_thread_all(gn412x, true);
#if KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE
err = request_threaded_irq(platform_get_irq(pdev, 0),
gn412x_gpio_irq_handler_h,
gn412x_gpio_irq_handler_t,
IRQF_SHARED,
dev_name(gn412x->gpiochip.dev),
gn412x);
if (err) {
dev_err(gn412x->gpiochip.dev, "Can't request IRQ %d (%d)\n",
#else
err = request_threaded_irq(platform_get_irq(pdev, 0),
gn412x_gpio_irq_handler_h,
gn412x_gpio_irq_handler_t,
IRQF_SHARED,
dev_name(gn412x->gpiochip.parent),
gn412x);
if (err) {
dev_err(gn412x->gpiochip.parent, "Can't request IRQ %d (%d)\n",
#endif
platform_get_irq(pdev, 0), err);
goto err_req;
}
gn412x_gpio_int_cfg_enable(gn412x);
gn412x_dbg_init(gn412x);
return 0;
err_req:
gn412x_gpio_irq_set_nested_thread_all(gn412x, false);
#if KERNEL_VERSION(4, 15, 0) > LINUX_VERSION_CODE
err_add_irq:
gpiochip_remove(&gn412x->gpiochip);
#endif
err_add:
iounmap(gn412x->mem);
err_map:
err_res_mem:
kfree(gn412x);
return err;
}
static int gn412x_gpio_remove(struct platform_device *pdev)
{
struct gn412x_gpio_dev *gn412x = platform_get_drvdata(pdev);
gn412x_dbg_exit(gn412x);
gn412x_gpio_int_cfg_disable(gn412x);
free_irq(platform_get_irq(pdev, 0), gn412x);
gn412x_gpio_irq_set_nested_thread_all(gn412x, false);
gpiochip_remove(&gn412x->gpiochip);
iounmap(gn412x->mem);
kfree(gn412x);
dev_dbg(&pdev->dev, "%s\n", __func__);
return 0;
}
static const struct platform_device_id gn412x_gpio_id[] = {
{
.name = "gn412x-gpio",
},
{}, /* last */
};
static struct platform_driver gn412x_gpio_platform_driver = {
.driver = {
.name = KBUILD_MODNAME,
},
.probe = gn412x_gpio_probe,
.remove = gn412x_gpio_remove,
.id_table = gn412x_gpio_id,
};
module_platform_driver(gn412x_gpio_platform_driver);
MODULE_AUTHOR("Federico Vaga ");
MODULE_DESCRIPTION("GN412X GPIO driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(VERSION);
MODULE_DEVICE_TABLE(platform, gn412x_gpio_id);
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/gn412x.h 0000664 0000000 0000000 00000004056 13707547500 0024532 0 ustar 00root root 0000000 0000000 /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2010-2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#ifndef __GN412X_H__
#define __GN412X_H__
#define GNINT_STAT_GPIO BIT(15)
#define GNINT_STAT_SW0 BIT(2)
#define GNINT_STAT_SW1 BIT(3)
#define GNINT_STAT_SW_ALL (GNINT_STAT_SW0 | GNINT_STAT_SW1)
/* Registers for GN4124 access */
enum {
/* page 106 */
GNPPCI_MSI_CONTROL = 0x48, /* actually, 3 smaller regs */
GNPPCI_MSI_ADDRESS_LOW = 0x4c,
GNPPCI_MSI_ADDRESS_HIGH = 0x50,
GNPPCI_MSI_DATA = 0x54,
GNPCI_SYS_CFG_SYSTEM = 0x800,
/* page 130 ff */
GNINT_CTRL = 0x810,
GNINT_STAT = 0x814,
GNINT_CFG_0 = 0x820,
GNINT_CFG_1 = 0x824,
GNINT_CFG_2 = 0x828,
GNINT_CFG_3 = 0x82c,
GNINT_CFG_4 = 0x830,
GNINT_CFG_5 = 0x834,
GNINT_CFG_6 = 0x838,
GNINT_CFG_7 = 0x83c,
#define GNINT_CFG(x) (GNINT_CFG_0 + 4 * (x))
/* page 146 ff */
GNGPIO_BASE = 0xA00,
GNGPIO_BYPASS_MODE = GNGPIO_BASE,
GNGPIO_DIRECTION_MODE = GNGPIO_BASE + 0x04, /* 0 == output */
GNGPIO_OUTPUT_ENABLE = GNGPIO_BASE + 0x08,
GNGPIO_OUTPUT_VALUE = GNGPIO_BASE + 0x0C,
GNGPIO_INPUT_VALUE = GNGPIO_BASE + 0x10,
GNGPIO_INT_MASK = GNGPIO_BASE + 0x14, /* 1 == disabled */
GNGPIO_INT_MASK_CLR = GNGPIO_BASE + 0x18, /* irq enable */
GNGPIO_INT_MASK_SET = GNGPIO_BASE + 0x1C, /* irq disable */
GNGPIO_INT_STATUS = GNGPIO_BASE + 0x20,
GNGPIO_INT_TYPE = GNGPIO_BASE + 0x24, /* 1 == level */
GNGPIO_INT_VALUE = GNGPIO_BASE + 0x28, /* 1 == high/rise */
GNGPIO_INT_ON_ANY = GNGPIO_BASE + 0x2C, /* both edges */
/* page 158 ff */
FCL_BASE = 0xB00,
FCL_CTRL = FCL_BASE,
FCL_STATUS = FCL_BASE + 0x04,
FCL_IODATA_IN = FCL_BASE + 0x08,
FCL_IODATA_OUT = FCL_BASE + 0x0C,
FCL_EN = FCL_BASE + 0x10,
FCL_TIMER_0 = FCL_BASE + 0x14,
FCL_TIMER_1 = FCL_BASE + 0x18,
FCL_CLK_DIV = FCL_BASE + 0x1C,
FCL_IRQ = FCL_BASE + 0x20,
FCL_TIMER_CTRL = FCL_BASE + 0x24,
FCL_IM = FCL_BASE + 0x28,
FCL_TIMER2_0 = FCL_BASE + 0x2C,
FCL_TIMER2_1 = FCL_BASE + 0x30,
FCL_DBG_STS = FCL_BASE + 0x34,
FCL_FIFO = 0xE00,
PCI_SYS_CFG_SYSTEM = 0x800
};
#endif
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/platform_data/ 0000775 0000000 0000000 00000000000 13707547500 0026146 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/platform_data/gn412x-gpio.h 0000664 0000000 0000000 00000000407 13707547500 0030277 0 ustar 00root root 0000000 0000000 /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#ifndef __GN412X_GPIO_H__
#define __GN412X_GPIO_H__
struct gn412x_platform_data {
unsigned int int_cfg;
};
#endif
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/spec-compat.c 0000664 0000000 0000000 00000007765 13707547500 0025727 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#include
#include
#include
#include
#include
#include
#include "spec-compat.h"
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
struct fpga_manager *__fpga_mgr_get(struct device *dev)
{
struct fpga_manager *mgr;
int ret = -ENODEV;
mgr = to_fpga_manager(dev);
if (!mgr)
goto err_dev;
/* Get exclusive use of fpga manager */
if (!mutex_trylock(&mgr->ref_mutex)) {
ret = -EBUSY;
goto err_dev;
}
if (!try_module_get(dev->parent->driver->owner))
goto err_ll_mod;
return mgr;
err_ll_mod:
mutex_unlock(&mgr->ref_mutex);
err_dev:
put_device(dev);
return ERR_PTR(ret);
}
static int fpga_mgr_dev_match(struct device *dev, const void *data)
{
return dev->parent == data;
}
#define FPGA_CLASS "fpga_mgr_class"
/**
* fpga_mgr_get - get an exclusive reference to a fpga mgr
* @dev:parent device that fpga mgr was registered with
*
* Given a device, get an exclusive reference to a fpga mgr.
*
* Return: fpga manager struct or IS_ERR() condition containing error code.
*/
struct fpga_manager *fpga_mgr_get(struct device *dev)
{
struct class *fpga_mgr_class;
struct device *mgr_dev;
fpga_mgr_class = (struct class *) kallsyms_lookup_name(FPGA_CLASS);
mgr_dev = class_find_device(fpga_mgr_class, NULL, dev,
fpga_mgr_dev_match);
if (!mgr_dev)
return ERR_PTR(-ENODEV);
return __fpga_mgr_get(mgr_dev);
}
#endif
static int __compat_spec_fw_load(struct fpga_manager *mgr, const char *name)
{
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE
return fpga_mgr_firmware_load(mgr, 0, name);
#else
struct fpga_image_info image;
memset(&image, 0, sizeof(image));
return fpga_mgr_firmware_load(mgr, &image, name);
#endif
#else
struct fpga_image_info image;
memset(&image, 0, sizeof(image));
image.firmware_name = (char *)name;
image.dev = mgr->dev.parent;
return fpga_mgr_load(mgr, &image);
#endif
}
struct mfd_find_data {
const char *name;
int id;
};
static int mfd_find_device_match(struct device *dev, void *data)
{
struct mfd_find_data *d = data;
struct platform_device *pdev = to_platform_device(dev);
if (strncmp(d->name, mfd_get_cell(pdev)->name,
strnlen(d->name, 32)) != 0)
return 0;
if (d->id >= 0 && pdev->id != d->id)
return 0;
return 1;
}
static struct platform_device *mfd_find_device(struct device *parent,
const char *name,
int id)
{
struct mfd_find_data d = {name, id};
struct device *dev;
dev = device_find_child(parent, (void *)&d, mfd_find_device_match);
if (!dev)
return NULL;
return to_platform_device(dev);
}
int compat_spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name)
{
struct fpga_manager *mgr;
struct platform_device *fpga_pdev;
int err;
fpga_pdev = mfd_find_device(&spec_gn412x->pdev->dev, "gn412x-fcl", -1);
if (!fpga_pdev)
return -ENODEV;
mgr = fpga_mgr_get(&fpga_pdev->dev);
if (IS_ERR(mgr))
return -ENODEV;
err = fpga_mgr_lock(mgr);
if (err)
goto out;
err = __compat_spec_fw_load(mgr, name);
fpga_mgr_unlock(mgr);
out:
fpga_mgr_put(mgr);
return err;
}
int compat_gpiod_add_lookup_table(struct gpiod_lookup_table *table)
{
void (*gpiod_add_lookup_table_p)(struct gpiod_lookup_table *table);
gpiod_add_lookup_table_p = (void *) kallsyms_lookup_name("gpiod_add_lookup_table");
if (gpiod_add_lookup_table_p)
gpiod_add_lookup_table_p(table);
else
return WARN(1, "Cannot find 'gpiod_add_lookup_table'");
return 0;
}
#if KERNEL_VERSION(4, 3, 0) > LINUX_VERSION_CODE
void gpiod_remove_lookup_table(struct gpiod_lookup_table *table)
{
struct mutex *gpio_lookup_lock_p = (void *) kallsyms_lookup_name("gpio_lookup_lock");
mutex_lock(gpio_lookup_lock_p);
list_del(&table->list);
mutex_unlock(gpio_lookup_lock_p);
}
#endif
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/spec-compat.h 0000664 0000000 0000000 00000003667 13707547500 0025731 0 ustar 00root root 0000000 0000000 /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#ifndef __SPEC_COMPAT_H__
#define __SPEC_COMPAT_H__
#include
#include
#include
#include
#include "spec.h"
#if KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE
/* So that we select the buffer size because smaller */
#define compat_fpga_ops_initial_header_size .initial_header_size = 0xFFFFFFFF,
#else
#define compat_fpga_ops_initial_header_size .initial_header_size = 0,
#endif
#else
#define compat_fpga_ops_initial_header_size
#endif
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
#define compat_fpga_ops_groups
#else
#define compat_fpga_ops_groups .groups = NULL,
#endif
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
struct fpga_image_info;
#endif
int compat_spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name);
#if KERNEL_VERSION(3, 11, 0) > LINUX_VERSION_CODE
#define __ATTR_RW(_name) __ATTR(_name, (S_IWUSR | S_IRUGO), \
_name##_show, _name##_store)
#define __ATTR_WO(_name) { \
.attr = { .name = __stringify(_name), .mode = S_IWUSR }, \
.store = _name##_store, \
}
#define DEVICE_ATTR_RW(_name) \
struct device_attribute dev_attr_##_name = __ATTR_RW(_name)
#define DEVICE_ATTR_RO(_name) \
struct device_attribute dev_attr_##_name = __ATTR_RO(_name)
#define DEVICE_ATTR_WO(_name) \
struct device_attribute dev_attr_##_name = __ATTR_WO(_name)
#endif
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE
#define GPIO_PERSISTENT (0 << 3)
#endif
extern int compat_gpiod_add_lookup_table(struct gpiod_lookup_table *table);
#if KERNEL_VERSION(4, 3, 0) > LINUX_VERSION_CODE
extern void gpiod_remove_lookup_table(struct gpiod_lookup_table *table);
#endif
#endif /* __SPEC_COMPAT_H__ */
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/spec-core-fpga.c 0000664 0000000 0000000 00000076466 13707547500 0026313 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "linux/printk.h"
#include "spec.h"
#include "spec-compat.h"
static int user_dma_coherent_size = 4 * 1024 * 1024;
module_param(user_dma_coherent_size, int, 0644);
MODULE_PARM_DESC(user_dma_coherent_size,
"DMA coherent allocation's size in bytes (default 4MiB)");
static size_t user_dma_max_segment;
module_param(user_dma_max_segment, long, 0644);
MODULE_PARM_DESC(user_dma_max_segment,
"Maximum DMA segment size in bytes (default 0, meaning whatever supported by the DMA engine)");
enum spec_fpga_irq_lines {
SPEC_FPGA_IRQ_FMC_I2C = 0,
SPEC_FPGA_IRQ_SPI,
SPEC_FPGA_IRQ_DMA_DONE,
};
enum spec_fpga_csr_offsets {
SPEC_FPGA_CSR_APP_OFF = SPEC_BASE_REGS_CSR + 0x00,
SPEC_FPGA_CSR_RESETS = SPEC_BASE_REGS_CSR + 0x04,
SPEC_FPGA_CSR_FMC_PRESENT = SPEC_BASE_REGS_CSR + 0x08,
SPEC_FPGA_CSR_GN4124_STATUS = SPEC_BASE_REGS_CSR + 0x0C,
SPEC_FPGA_CSR_DDR_STATUS = SPEC_BASE_REGS_CSR + 0x10,
SPEC_FPGA_CSR_PCB_REV = SPEC_BASE_REGS_CSR + 0x14,
};
enum spec_fpga_csr_fields {
SPEC_FPGA_CSR_DDR_STATUS_DONE = 0x1,
};
enum spec_fpga_therm_offsets {
SPEC_FPGA_THERM_SERID_MSB = SPEC_BASE_REGS_THERM_ID + 0x0,
SPEC_FPGA_THERM_SERID_LSB = SPEC_BASE_REGS_THERM_ID + 0x4,
SPEC_FPGA_THERM_TEMP = SPEC_BASE_REGS_THERM_ID + 0x8,
};
enum spec_fpga_meta_cap_mask {
SPEC_META_CAP_VIC = BIT(0),
SPEC_META_CAP_THERM = BIT(1),
SPEC_META_CAP_SPI = BIT(2),
SPEC_META_CAP_WR = BIT(3),
SPEC_META_CAP_BLD = BIT(4),
SPEC_META_CAP_DMA = BIT(5),
};
static const struct debugfs_reg32 spec_fpga_debugfs_reg32[] = {
{
.name = "Application offset",
.offset = SPEC_FPGA_CSR_APP_OFF,
},
{
.name = "Resets",
.offset = SPEC_FPGA_CSR_RESETS,
},
{
.name = "FMC present",
.offset = SPEC_FPGA_CSR_FMC_PRESENT,
},
{
.name = "GN4124 Status",
.offset = SPEC_FPGA_CSR_GN4124_STATUS,
},
{
.name = "DDR Status",
.offset = SPEC_FPGA_CSR_DDR_STATUS,
},
{
.name = "PCB revision",
.offset = SPEC_FPGA_CSR_PCB_REV,
},
};
static int spec_fpga_dbg_bld_info(struct seq_file *s, void *offset)
{
struct spec_fpga *spec_fpga = s->private;
int off;
if (!(spec_fpga->meta->cap & SPEC_META_CAP_BLD)) {
seq_puts(s, "not available\n");
return 0;
}
for (off = SPEC_BASE_REGS_BUILDINFO;
off < SPEC_BASE_REGS_BUILDINFO + SPEC_BASE_REGS_BUILDINFO_SIZE - 1;
off++) {
char tmp = ioread8(spec_fpga->fpga + off);
if (!tmp)
return 0;
seq_putc(s, tmp);
}
return 0;
}
static int spec_fpga_dbg_bld_info_open(struct inode *inode,
struct file *file)
{
struct spec_gn412x *spec = inode->i_private;
return single_open(file, spec_fpga_dbg_bld_info, spec);
}
static const struct file_operations spec_fpga_dbg_bld_ops = {
.owner = THIS_MODULE,
.open = spec_fpga_dbg_bld_info_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
struct spec_fpga_dbg_dma {
struct spec_fpga *spec_fpga;
struct dma_chan *dchan;
size_t datalen;
void *data;
dma_addr_t datadma;
struct dmaengine_result dma_res;
struct completion compl;
};
struct spec_fmca_dbg_dma_tx_ctxt {
struct dmaengine_result dma_res;
};
static void spec_fmca_dbg_dma_tx_complete(void *arg,
const struct dmaengine_result *result)
{
struct spec_fpga_dbg_dma *dbgdma = arg;
memcpy(&dbgdma->dma_res, result, sizeof(*result));
complete(&dbgdma->compl);
}
static int spec_fpga_dbg_dma_transfer(struct spec_fpga_dbg_dma *dbgdma,
enum dma_transfer_direction dir,
size_t count, loff_t offset)
{
int err;
struct dma_slave_config sconfig;
struct dma_async_tx_descriptor *tx;
dma_cookie_t cookie;
size_t max_segment;
struct sg_table sgt;
struct scatterlist *sg;
int i;
dev_dbg(dbgdma->dchan->device->dev,
"arg: {dir: %d, size: %ld, offset: 0x%08llx}\n",
dir, count, offset);
/*
* The GN4124 chip has a 4KiB payload. For DMA_DEV_TO_MEM this is
* handled by the HDL core. For DMA_MEM_TO_DEV, the split is done here.
*/
if (dir == DMA_DEV_TO_MEM)
max_segment = dma_get_max_seg_size(dbgdma->dchan->device->dev);
else
max_segment = 4096;
if (user_dma_max_segment)
max_segment = min(user_dma_max_segment, max_segment);
err = sg_alloc_table(&sgt,
(count / max_segment) + !!(count % max_segment),
GFP_KERNEL);
if (err)
goto err_sgt;
for_each_sg(sgt.sgl, sg, sgt.nents, i) {
sg_dma_address(sg) = dbgdma->datadma + (i * max_segment);
sg_dma_len(sg) = max_segment;
if (sg_is_last(sg)) {
size_t len = count % max_segment;
if (len)
sg_dma_len(sg) = len;
}
}
memset(&sconfig, 0, sizeof(sconfig));
sconfig.direction = dir;
sconfig.src_addr = offset;
err = dmaengine_slave_config(dbgdma->dchan, &sconfig);
if (err)
goto err_cfg;
tx = dmaengine_prep_slave_sg(dbgdma->dchan, sgt.sgl, sgt.nents,
dir, 0);
if (!tx) {
err = -EINVAL;
goto err_prep;
}
/* Setup the DMA completion callback */
dbgdma->dma_res.result = DMA_TRANS_NOERROR;
dbgdma->dma_res.residue = 0;
tx->callback_result = spec_fmca_dbg_dma_tx_complete;
tx->callback_param = (void *)dbgdma;
cookie = dmaengine_submit(tx);
if (cookie < 0) {
err = cookie;
goto err_sub;
}
dma_async_issue_pending(dbgdma->dchan);
err = wait_for_completion_interruptible_timeout(
&dbgdma->compl, msecs_to_jiffies(60000));
if (err == 0)
err = -ETIMEDOUT;
if (err > 0) {
switch (dbgdma->dma_res.result) {
case DMA_TRANS_NOERROR:
err = 0;
break;
default:
err = -EIO;
break;
}
}
err_sub:
err_prep:
err_cfg:
sg_free_table(&sgt);
err_sgt:
return err;
}
static ssize_t spec_fpga_dbg_dma_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
struct spec_fpga_dbg_dma *dbgdma = file->private_data;
int err;
if (*ppos >= SPEC_DDR_SIZE)
return -EINVAL;
count = min(dbgdma->datalen, count);
err = spec_fpga_dbg_dma_transfer(file->private_data, DMA_DEV_TO_MEM,
count, *ppos);
if (err)
goto err_trans;
err = copy_to_user(buf, dbgdma->data, count);
if (err)
goto err_cpy;
*ppos += count;
return count;
err_cpy:
err_trans:
return err;
}
static ssize_t spec_fpga_dbg_dma_write(struct file *file,
const char __user *buf, size_t count,
loff_t *ppos)
{
struct spec_fpga_dbg_dma *dbgdma = file->private_data;
int err;
if (*ppos >= SPEC_DDR_SIZE)
return -EINVAL;
count = min(dbgdma->datalen, count);
err = copy_from_user(dbgdma->data, buf, count);
if (err)
goto err_cpy;
err = spec_fpga_dbg_dma_transfer(dbgdma, DMA_MEM_TO_DEV,
count, *ppos);
if (err)
goto err_trans;
*ppos += count;
return count;
err_trans:
err_cpy:
return err;
}
static bool spec_fpga_dbg_dma_filter(struct dma_chan *dchan, void *arg)
{
return dchan->device == arg;
}
static int spec_fpga_dbg_dma_open(struct inode *inode, struct file *file)
{
struct spec_fpga_dbg_dma *dbgdma;
struct spec_fpga *spec_fpga = inode->i_private;
dma_cap_mask_t dma_mask;
int err;
if (!spec_fpga->dma_pdev) {
dev_warn(&spec_fpga->dev,
"Not able to find DMA engine: platform_device missing\n");
return -ENODEV;
}
dbgdma = kzalloc(sizeof(*dbgdma), GFP_KERNEL);
if (!dbgdma)
return -ENOMEM;
init_completion(&dbgdma->compl);
dbgdma->spec_fpga = spec_fpga;
dbgdma->datalen = user_dma_coherent_size;
dbgdma->data = dma_alloc_coherent(dbgdma->spec_fpga->dev.parent,
dbgdma->datalen, &dbgdma->datadma,
GFP_KERNEL);
if (!dbgdma->data) {
err = -ENOMEM;
goto err_dma_alloc;
}
dma_cap_zero(dma_mask);
dma_cap_set(DMA_SLAVE, dma_mask);
dma_cap_set(DMA_PRIVATE, dma_mask);
dbgdma->dchan = dma_request_channel(dma_mask, spec_fpga_dbg_dma_filter,
platform_get_drvdata(spec_fpga->dma_pdev));
if (!dbgdma->dchan) {
dev_dbg(&spec_fpga->dev,
"DMA transfer Failed: can't request channel\n");
err = -EBUSY;
goto err_req;
}
file->private_data = dbgdma;
return 0;
err_req:
dma_free_coherent(dbgdma->spec_fpga->dev.parent,
dbgdma->datalen, dbgdma->data, dbgdma->datadma);
err_dma_alloc:
kfree(dbgdma);
return err;
}
static int spec_fpga_dbg_dma_flush(struct file *file, fl_owner_t id)
{
return 0;
}
static int spec_fpga_dbg_dma_release(struct inode *inode, struct file *file)
{
struct spec_fpga_dbg_dma *dbgdma = file->private_data;
dma_free_coherent(dbgdma->spec_fpga->dev.parent,
dbgdma->datalen, dbgdma->data, dbgdma->datadma);
dma_release_channel(dbgdma->dchan);
kfree(dbgdma);
return 0;
}
static const struct file_operations spec_fpga_dbg_dma_ops = {
.owner = THIS_MODULE,
.llseek = default_llseek,
.read = spec_fpga_dbg_dma_read,
.write = spec_fpga_dbg_dma_write,
.open = spec_fpga_dbg_dma_open,
.flush = spec_fpga_dbg_dma_flush,
.release = spec_fpga_dbg_dma_release,
};
static int spec_fpga_dbg_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pdev = to_pci_dev(spec_fpga->dev.parent);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
int err;
spec_fpga->dbg_dir_fpga = debugfs_create_dir(dev_name(&spec_fpga->dev),
spec_gn412x->dbg_dir);
if (IS_ERR_OR_NULL(spec_fpga->dbg_dir_fpga)) {
err = PTR_ERR(spec_fpga->dbg_dir_fpga);
dev_err(&spec_fpga->dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(&spec_fpga->dev), err);
return err;
}
spec_fpga->dbg_csr_reg.regs = spec_fpga_debugfs_reg32;
spec_fpga->dbg_csr_reg.nregs = ARRAY_SIZE(spec_fpga_debugfs_reg32);
spec_fpga->dbg_csr_reg.base = spec_fpga->fpga;
spec_fpga->dbg_csr = debugfs_create_regset32(SPEC_DBG_CSR_NAME, 0200,
spec_fpga->dbg_dir_fpga,
&spec_fpga->dbg_csr_reg);
if (IS_ERR_OR_NULL(spec_fpga->dbg_csr)) {
err = PTR_ERR(spec_fpga->dbg_csr);
dev_warn(&spec_fpga->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
SPEC_DBG_CSR_NAME, err);
goto err;
}
spec_fpga->dbg_bld = debugfs_create_file(SPEC_DBG_BLD_INFO_NAME,
0444,
spec_fpga->dbg_dir_fpga,
spec_fpga,
&spec_fpga_dbg_bld_ops);
if (IS_ERR_OR_NULL(spec_fpga->dbg_bld)) {
err = PTR_ERR(spec_fpga->dbg_bld);
dev_err(&spec_fpga->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
SPEC_DBG_BLD_INFO_NAME, err);
goto err;
}
spec_fpga->dbg_dma = debugfs_create_file(SPEC_DBG_DMA_NAME,
0444,
spec_fpga->dbg_dir_fpga,
spec_fpga,
&spec_fpga_dbg_dma_ops);
if (IS_ERR_OR_NULL(spec_fpga->dbg_dma)) {
err = PTR_ERR(spec_fpga->dbg_dma);
dev_err(&spec_fpga->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
SPEC_DBG_DMA_NAME, err);
goto err;
}
return 0;
err:
debugfs_remove_recursive(spec_fpga->dbg_dir_fpga);
return err;
}
static void spec_fpga_dbg_exit(struct spec_fpga *spec_fpga)
{
debugfs_remove_recursive(spec_fpga->dbg_dir_fpga);
}
static inline uint32_t spec_fpga_csr_app_offset(struct spec_fpga *spec_fpga)
{
return ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_APP_OFF);
}
static inline uint32_t spec_fpga_csr_pcb_rev(struct spec_fpga *spec_fpga)
{
return ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_PCB_REV);
}
static struct resource spec_fpga_vic_res[] = {
{
.name = "htvic-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_BASE_REGS_VIC,
.end = SPEC_BASE_REGS_VIC + SPEC_BASE_REGS_VIC_SIZE - 1,
}, {
.name = "htvic-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = 0,
.end = 0,
},
};
struct irq_domain *spec_fpga_irq_find_host(struct device *dev)
{
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
struct irq_fwspec fwspec = {
.fwnode = dev->fwnode,
.param_count = 2,
.param[0] = ((unsigned long)dev >> 32) & 0xffffffff,
.param[1] = ((unsigned long)dev) & 0xffffffff,
};
return irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY);
#else
return (irq_find_host((void *)dev));
#endif
}
/* Vector Interrupt Controller */
static int spec_fpga_vic_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pcidev);
unsigned long pci_start = pci_resource_start(pcidev, 0);
const unsigned int res_n = ARRAY_SIZE(spec_fpga_vic_res);
struct resource res[ARRAY_SIZE(spec_fpga_vic_res)];
struct platform_device *pdev;
if (!(spec_fpga->meta->cap & SPEC_META_CAP_VIC))
return 0;
memcpy(&res, spec_fpga_vic_res, sizeof(res));
res[0].start += pci_start;
res[0].end += pci_start;
res[1].start = gpiod_to_irq(spec_gn412x->gpiod[GN4124_GPIO_IRQ1]);
res[1].end = res[1].start;
pdev = platform_device_register_resndata(&spec_fpga->dev,
"htvic-spec",
PLATFORM_DEVID_AUTO,
res, res_n,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
spec_fpga->vic_pdev = pdev;
return 0;
}
static void spec_fpga_vic_exit(struct spec_fpga *spec_fpga)
{
if (spec_fpga->vic_pdev) {
platform_device_unregister(spec_fpga->vic_pdev);
spec_fpga->vic_pdev = NULL;
}
}
/* DMA engine */
static struct resource spec_fpga_dma_res[] = {
{
.name = "spec-gn412x-dma-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_BASE_REGS_DMA,
.end = SPEC_BASE_REGS_DMA + SPEC_BASE_REGS_DMA_SIZE - 1,
}, {
.name = "spec-gn412x-dma-irq-done",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = 0,
.end = 0,
},
};
static int spec_fpga_dma_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
unsigned long pci_start = pci_resource_start(pcidev, 0);
const unsigned int res_n = ARRAY_SIZE(spec_fpga_dma_res);
struct resource res[ARRAY_SIZE(spec_fpga_dma_res)];
struct platform_device *pdev;
struct irq_domain *vic_domain;
uint32_t ddr_status;
if (!(spec_fpga->meta->cap & SPEC_META_CAP_DMA))
return 0;
mdelay(1);
ddr_status = ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_DDR_STATUS);
if (!(ddr_status & SPEC_FPGA_CSR_DDR_STATUS_DONE)) {
dev_err(&spec_fpga->dev,
"Failed to load DMA engine: DDR controller not calibrated - 0x%x.\n",
ddr_status);
return -ENODEV;
}
vic_domain = spec_fpga_irq_find_host(&spec_fpga->vic_pdev->dev);
if (!vic_domain) {
dev_err(&spec_fpga->dev,
"Failed to load DMA engine: can't find VIC\n");
return -ENODEV;
}
memcpy(&res, spec_fpga_dma_res, sizeof(res));
res[0].start += pci_start;
res[0].end += pci_start;
res[1].start = irq_find_mapping(vic_domain, SPEC_FPGA_IRQ_DMA_DONE);
pdev = platform_device_register_resndata(&spec_fpga->dev,
"spec-gn412x-dma",
PLATFORM_DEVID_AUTO,
res, res_n,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
spec_fpga->dma_pdev = pdev;
return 0;
}
static void spec_fpga_dma_exit(struct spec_fpga *spec_fpga)
{
if (spec_fpga->dma_pdev) {
platform_device_unregister(spec_fpga->dma_pdev);
spec_fpga->dma_pdev = NULL;
}
}
/* MFD devices */
enum spec_fpga_mfd_devs_enum {
SPEC_FPGA_MFD_FMC_I2C = 0,
SPEC_FPGA_MFD_SPI,
};
static struct resource spec_fpga_fmc_i2c_res[] = {
{
.name = "i2c-ocores-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_BASE_REGS_FMC_I2C,
.end = SPEC_BASE_REGS_FMC_I2C +
SPEC_BASE_REGS_FMC_I2C_SIZE - 1,
}, {
.name = "i2c-ocores-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = SPEC_FPGA_IRQ_FMC_I2C,
.end = SPEC_FPGA_IRQ_FMC_I2C,
},
};
#define SPEC_FPGA_WB_CLK_HZ 62500000
#define SPEC_FPGA_WB_CLK_KHZ (SPEC_FPGA_WB_CLK_HZ / 1000)
static struct ocores_i2c_platform_data spec_fpga_fmc_i2c_pdata = {
.reg_shift = 2, /* 32bit aligned */
.reg_io_width = 4,
.clock_khz = SPEC_FPGA_WB_CLK_KHZ,
.big_endian = 0,
.num_devices = 0,
.devices = NULL,
};
static struct resource spec_fpga_spi_res[] = {
{
.name = "spi-ocores-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_BASE_REGS_FLASH_SPI,
.end = SPEC_BASE_REGS_FLASH_SPI +
SPEC_BASE_REGS_FLASH_SPI_SIZE - 1,
}, {
.name = "spi-ocores-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = SPEC_FPGA_IRQ_SPI,
.end = SPEC_FPGA_IRQ_SPI,
},
};
struct flash_platform_data spec_flash_pdata = {
.name = "spec-flash",
.parts = NULL,
.nr_parts = 0,
.type = "m25p32",
};
static struct spi_board_info spec_fpga_spi_devices_info[] = {
{
.modalias = "m25p32", /*
* just informative: sometimes we have
* other chips, but the m25p80 driver
* takes care of identifying the correct
* memory
*/
.max_speed_hz = SPEC_FPGA_WB_CLK_HZ / 128,
.chip_select = 0,
.platform_data = &spec_flash_pdata,
}
};
static struct spi_ocores_platform_data spec_fpga_spi_pdata = {
.big_endian = 0,
.clock_hz = SPEC_FPGA_WB_CLK_HZ,
.num_devices = ARRAY_SIZE(spec_fpga_spi_devices_info),
.devices = spec_fpga_spi_devices_info,
};
static const struct mfd_cell spec_fpga_mfd_devs[] = {
[SPEC_FPGA_MFD_FMC_I2C] = {
.name = "i2c-ohwr",
.platform_data = &spec_fpga_fmc_i2c_pdata,
.pdata_size = sizeof(spec_fpga_fmc_i2c_pdata),
.num_resources = ARRAY_SIZE(spec_fpga_fmc_i2c_res),
.resources = spec_fpga_fmc_i2c_res,
},
[SPEC_FPGA_MFD_SPI] = {
.name = "spi-ocores",
.platform_data = &spec_fpga_spi_pdata,
.pdata_size = sizeof(spec_fpga_spi_pdata),
.num_resources = ARRAY_SIZE(spec_fpga_spi_res),
.resources = spec_fpga_spi_res,
},
};
static inline size_t __fpga_mfd_devs_size(void)
{
#define SPEC_FPGA_MFD_DEVS_MAX 4
return (sizeof(struct mfd_cell) * SPEC_FPGA_MFD_DEVS_MAX);
}
static int spec_fpga_devices_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
struct mfd_cell *fpga_mfd_devs;
struct irq_domain *vic_domain;
unsigned int n_mfd = 0;
int err;
fpga_mfd_devs = devm_kzalloc(&spec_fpga->dev,
__fpga_mfd_devs_size(),
GFP_KERNEL);
if (!fpga_mfd_devs)
return -ENOMEM;
memcpy(&fpga_mfd_devs[n_mfd],
&spec_fpga_mfd_devs[SPEC_FPGA_MFD_FMC_I2C],
sizeof(fpga_mfd_devs[n_mfd]));
n_mfd++;
if (spec_fpga->meta->cap & SPEC_META_CAP_SPI) {
memcpy(&fpga_mfd_devs[n_mfd],
&spec_fpga_mfd_devs[SPEC_FPGA_MFD_SPI],
sizeof(fpga_mfd_devs[n_mfd]));
n_mfd++;
}
vic_domain = spec_fpga_irq_find_host(&spec_fpga->vic_pdev->dev);
if (!vic_domain) {
/* Remove IRQ resource from all devices */
fpga_mfd_devs[0].num_resources = 1; /* FMC I2C */
fpga_mfd_devs[1].num_resources = 1; /* SPI */
}
err = mfd_add_devices(&spec_fpga->dev,
PLATFORM_DEVID_AUTO,
fpga_mfd_devs, n_mfd,
&pcidev->resource[0],
0, vic_domain);
if (err)
goto err_mfd;
return 0;
err_mfd:
devm_kfree(&spec_fpga->dev, fpga_mfd_devs);
return err;
}
static void spec_fpga_devices_exit(struct spec_fpga *spec_fpga)
{
mfd_remove_devices(&spec_fpga->dev);
}
/* Thermometer */
static ssize_t temperature_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
if (spec_fpga->meta->cap & SPEC_META_CAP_THERM) {
uint32_t temp;
temp = ioread32(spec_fpga->fpga + SPEC_FPGA_THERM_TEMP);
return snprintf(buf, PAGE_SIZE, "%d.%d C\n",
temp / 16, (temp & 0xF) * 1000 / 16);
}
return snprintf(buf, PAGE_SIZE, "-.- C\n");
}
static DEVICE_ATTR_RO(temperature);
static ssize_t serial_number_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
if (spec_fpga->meta->cap & SPEC_META_CAP_THERM) {
uint32_t msb, lsb;
msb = ioread32(spec_fpga->fpga + SPEC_FPGA_THERM_SERID_MSB);
lsb = ioread32(spec_fpga->fpga + SPEC_FPGA_THERM_SERID_LSB);
return snprintf(buf, PAGE_SIZE, "0x%08x%08x\n", msb, lsb);
}
return snprintf(buf, PAGE_SIZE, "0x----------------\n");
}
static DEVICE_ATTR_RO(serial_number);
static struct attribute *spec_fpga_therm_attrs[] = {
&dev_attr_serial_number.attr,
&dev_attr_temperature.attr,
NULL,
};
static const struct attribute_group spec_fpga_therm_group = {
.name = "thermometer",
.attrs = spec_fpga_therm_attrs,
};
/* CSR attributes */
static ssize_t pcb_rev_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
return snprintf(buf, PAGE_SIZE, "0x%x\n",
spec_fpga_csr_pcb_rev(spec_fpga));
}
static DEVICE_ATTR_RO(pcb_rev);
static ssize_t application_offset_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
return snprintf(buf, PAGE_SIZE, "0x%x\n",
spec_fpga_csr_app_offset(spec_fpga));
}
static DEVICE_ATTR_RO(application_offset);
enum spec_fpga_csr_resets {
SPEC_FPGA_CSR_RESETS_ALL = BIT(0),
SPEC_FPGA_CSR_RESETS_APP = BIT(1),
};
static void spec_fpga_app_reset(struct spec_fpga *spec_fpga, bool val)
{
uint32_t resets;
resets = ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_RESETS);
if (val)
resets |= SPEC_FPGA_CSR_RESETS_APP;
else
resets &= ~SPEC_FPGA_CSR_RESETS_APP;
iowrite32(resets, spec_fpga->fpga + SPEC_FPGA_CSR_RESETS);
}
static void spec_fpga_app_restart(struct spec_fpga *spec_fpga)
{
spec_fpga_app_reset(spec_fpga, true);
udelay(1);
spec_fpga_app_reset(spec_fpga, false);
udelay(1);
}
static ssize_t reset_app_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
uint32_t resets;
resets = ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_RESETS);
return snprintf(buf, PAGE_SIZE, "%d\n",
!!(resets & SPEC_FPGA_CSR_RESETS_APP));
}
static ssize_t reset_app_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
spec_fpga_app_reset(to_spec_fpga(dev), val);
return count;
}
static DEVICE_ATTR_RW(reset_app);
static struct attribute *spec_fpga_csr_attrs[] = {
&dev_attr_pcb_rev.attr,
&dev_attr_application_offset.attr,
&dev_attr_reset_app.attr,
NULL,
};
static const struct attribute_group spec_fpga_csr_group = {
.attrs = spec_fpga_csr_attrs,
};
/* FMC */
#define SPEC_FMC_SLOTS 1
static inline u8 spec_fmc_presence(struct spec_fpga *spec_fpga)
{
return (ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_FMC_PRESENT) & 0x1);
}
static int spec_fmc_is_present(struct fmc_carrier *carrier,
struct fmc_slot *slot)
{
struct spec_fpga *spec_fpga = carrier->priv;
return spec_fmc_presence(spec_fpga);
}
static const struct fmc_carrier_operations spec_fmc_ops = {
.owner = THIS_MODULE,
.is_present = spec_fmc_is_present,
};
static int spec_i2c_find_adapter(struct device *dev, void *data)
{
struct spec_fpga *spec_fpga = data;
struct i2c_adapter *adap, *adap_parent;
if (dev->type != &i2c_adapter_type)
return 0;
adap = to_i2c_adapter(dev);
adap_parent = i2c_parent_is_i2c_adapter(adap);
if (!adap_parent)
return 0;
/* We have a muxed I2C master */
if (&spec_fpga->dev != adap_parent->dev.parent->parent)
return 0;
/* Found! Return the bus ID */
return i2c_adapter_id(adap);
}
/**
* Get the I2C adapter associated with an FMC slot
* @data: data used to find the correct I2C bus
* @slot_nr: FMC slot number
*
* Return: the I2C bus to be used
*/
static int spec_i2c_get_bus(struct spec_fpga *spec_fpga)
{
return i2c_for_each_dev(spec_fpga, spec_i2c_find_adapter);
}
/**
* Create an FMC interface
*/
static int spec_fmc_init(struct spec_fpga *spec_fpga)
{
int err;
spec_fpga->slot_info.i2c_bus_nr = spec_i2c_get_bus(spec_fpga);
if (spec_fpga->slot_info.i2c_bus_nr <= 0) {
dev_err(spec_fpga->dev.parent,
"Invalid I2C bus number %d\n",
spec_fpga->slot_info.i2c_bus_nr);
return -ENODEV;
}
spec_fpga->slot_info.ga = 0;
spec_fpga->slot_info.lun = 1;
err = fmc_carrier_register(&spec_fpga->dev, &spec_fmc_ops,
SPEC_FMC_SLOTS, &spec_fpga->slot_info,
spec_fpga);
if (err) {
dev_err(spec_fpga->dev.parent,
"Failed to register as FMC carrier\n");
goto err_fmc;
}
return 0;
err_fmc:
return err;
}
static int spec_fmc_exit(struct spec_fpga *spec_fpga)
{
return fmc_carrier_unregister(&spec_fpga->dev);
}
/* FPGA Application */
/**
* Build the platform_device_id->name from metadata
*
* The byte order on SPEC is little endian, but we want to convert it
* in string. Use big-endian read to swap word and get the string order
* from MSB to LSB
*/
static int spec_fpga_app_id_build(struct spec_fpga *spec_fpga,
unsigned long app_off,
char *id, unsigned int size)
{
uint32_t vendor, device;
vendor = ioread32be(spec_fpga->fpga + app_off + FPGA_META_VENDOR);
device = ioread32be(spec_fpga->fpga + app_off + FPGA_META_DEVICE);
memset(id, 0, size);
if (vendor == 0xFF000000) {
dev_warn(&spec_fpga->dev, "Vendor UUID not supported yet\n");
return -ENODEV;
}
snprintf(id, size, "id:%4phN%4phN", &vendor, &device);
return 0;
}
static int spec_fpga_app_init_res_mem(struct spec_fpga *spec_fpga,
unsigned int app_offset,
struct resource *res)
{
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
if (!app_offset)
return -ENODEV;
res->name = "app-mem";
res->flags = IORESOURCE_MEM;
res->start = pci_resource_start(pcidev, 0) + app_offset;
res->end = pci_resource_end(pcidev, 0);
return 0;
}
static void spec_fpga_app_init_res_irq(struct spec_fpga *spec_fpga,
unsigned int first_hwirq,
struct resource *res,
unsigned int res_n)
{
struct irq_domain *vic_domain;
int i, hwirq;
if (!spec_fpga->vic_pdev)
return;
vic_domain = spec_fpga_irq_find_host(&spec_fpga->vic_pdev->dev);
for (i = 0, hwirq = first_hwirq; i < res_n; ++i, ++hwirq) {
res[i].name = "app-irq";
res[i].flags = IORESOURCE_IRQ;
res[i].start = irq_find_mapping(vic_domain, hwirq);
}
}
static void spec_fpga_app_init_res_dma(struct spec_fpga *spec_fpga,
struct resource *res)
{
struct dma_device *dma;
if (!spec_fpga->dma_pdev) {
dev_warn(&spec_fpga->dev, "Not able to find DMA engine: platform_device missing\n");
return ;
}
dma = platform_get_drvdata(spec_fpga->dma_pdev);
if (dma) {
res->name = "app-dma";
res->flags = IORESOURCE_DMA;
res->start = 0;
res->start |= dma->dev_id << 16;
} else {
dev_warn(&spec_fpga->dev, "Not able to find DMA engine: drvdata missing\n");
}
}
#define SPEC_FPGA_APP_NAME_MAX 47
#define SPEC_FPGA_APP_IRQ_BASE 6
#define SPEC_FPGA_APP_RES_IRQ_START 2
#define SPEC_FPGA_APP_RES_IRQ_N (32 - SPEC_FPGA_APP_IRQ_BASE)
#define SPEC_FPGA_APP_RES_N (SPEC_FPGA_APP_RES_IRQ_N + 1 + 1) /* IRQs MEM DMA */
#define SPEC_FPGA_APP_RES_MEM 0
#define SPEC_FPGA_APP_RES_DMA 1
static int spec_fpga_app_init(struct spec_fpga *spec_fpga)
{
unsigned int res_n = SPEC_FPGA_APP_RES_N;
struct resource *res;
struct platform_device *pdev;
char app_name[SPEC_FPGA_APP_NAME_MAX];
unsigned int app_offset;
int err = 0;
app_offset = spec_fpga_csr_app_offset(spec_fpga);
res = kcalloc(SPEC_FPGA_APP_RES_N, sizeof(*res), GFP_KERNEL);
if (!res)
return -ENOMEM;
err = spec_fpga_app_init_res_mem(spec_fpga, app_offset,
&res[SPEC_FPGA_APP_RES_MEM]);
if (err) {
dev_warn(&spec_fpga->dev, "Application not found\n");
err = 0;
goto err_free;
}
spec_fpga_app_init_res_dma(spec_fpga, &res[SPEC_FPGA_APP_RES_DMA]);
spec_fpga_app_init_res_irq(spec_fpga,
SPEC_FPGA_APP_IRQ_BASE,
&res[SPEC_FPGA_APP_RES_IRQ_START],
SPEC_FPGA_APP_RES_IRQ_N);
err = spec_fpga_app_id_build(spec_fpga, app_offset,
app_name, SPEC_FPGA_APP_NAME_MAX);
if (err)
goto err_free;
spec_fpga_app_restart(spec_fpga);
pdev = platform_device_register_resndata(&spec_fpga->dev,
app_name, PLATFORM_DEVID_AUTO,
res, res_n,
NULL, 0);
err = IS_ERR(pdev);
if (err)
goto err_free;
spec_fpga->app_pdev = pdev;
err_free:
kfree(res);
return err;
}
static void spec_fpga_app_exit(struct spec_fpga *spec_fpga)
{
if (spec_fpga->app_pdev) {
platform_device_unregister(spec_fpga->app_pdev);
spec_fpga->app_pdev = NULL;
}
}
static bool spec_fpga_is_valid(struct spec_gn412x *spec_gn412x,
struct spec_meta_id *meta)
{
if ((meta->bom & SPEC_META_BOM_END_MASK) != SPEC_META_BOM_LE) {
dev_err(&spec_gn412x->pdev->dev,
"Expected Little Endian devices BOM: 0x%x\n",
meta->bom);
return false;
}
if ((meta->bom & SPEC_META_BOM_VER_MASK) != 0) {
dev_err(&spec_gn412x->pdev->dev,
"Unknow Metadata specification version BOM: 0x%x\n",
meta->bom);
return false;
}
if (meta->vendor != SPEC_META_VENDOR_ID ||
meta->device != SPEC_META_DEVICE_ID) {
dev_err(&spec_gn412x->pdev->dev,
"Unknow vendor/device ID: %08x:%08x\n",
meta->vendor, meta->device);
return false;
}
if ((meta->version & SPEC_META_VERSION_MASK) != SPEC_META_VERSION_1_4) {
dev_err(&spec_gn412x->pdev->dev,
"Unknow version: %08x\n", meta->version);
return false;
}
return true;
}
static void spec_release(struct device *dev)
{
}
static int spec_uevent(struct device *dev, struct kobj_uevent_env *env)
{
return 0;
}
static const struct attribute_group *spec_groups[] = {
&spec_fpga_therm_group,
&spec_fpga_csr_group,
NULL
};
static const struct device_type spec_fpga_type = {
.name = "spec",
.release = spec_release,
.uevent = spec_uevent,
.groups = spec_groups,
};
/**
* Initialize carrier devices on FPGA
*/
int spec_fpga_init(struct spec_gn412x *spec_gn412x)
{
struct spec_fpga *spec_fpga;
struct resource *r0 = &spec_gn412x->pdev->resource[0];
int err;
spec_fpga = kzalloc(sizeof(*spec_fpga), GFP_KERNEL);
if (!spec_fpga)
return -ENOMEM;
spec_gn412x->spec_fpga = spec_fpga;
spec_fpga->fpga = ioremap(r0->start, resource_size(r0));
if (!spec_fpga->fpga) {
err = -ENOMEM;
goto err_map;
}
spec_fpga->meta = spec_fpga->fpga + SPEC_META_BASE;
if (!spec_fpga_is_valid(spec_gn412x, spec_fpga->meta)) {
err = -EINVAL;
goto err_valid;
}
spec_fpga->dev.parent = &spec_gn412x->pdev->dev;
spec_fpga->dev.driver = spec_gn412x->pdev->dev.driver;
spec_fpga->dev.type = &spec_fpga_type;
err = dev_set_name(&spec_fpga->dev, "spec-%s",
dev_name(&spec_gn412x->pdev->dev));
if (err)
goto err_name;
err = device_register(&spec_fpga->dev);
if (err) {
dev_err(&spec_gn412x->pdev->dev, "Failed to register '%s'\n",
dev_name(&spec_gn412x->pdev->dev));
goto err_dev;
}
spec_fpga_dbg_init(spec_fpga);
err = spec_fpga_vic_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize VIC %d\n", err);
goto err_vic;
}
err = spec_fpga_dma_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize DMA %d\n", err);
goto err_dma;
}
err = spec_fpga_devices_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize Devices %d\n", err);
goto err_devs;
}
err = spec_fmc_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize FMC %d\n", err);
goto err_fmc;
}
err = spec_fpga_app_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize APP %d\n", err);
goto err_app;
}
return 0;
err_app:
spec_fmc_exit(spec_fpga);
err_fmc:
spec_fpga_devices_exit(spec_fpga);
err_devs:
spec_fpga_dma_exit(spec_fpga);
err_dma:
spec_fpga_vic_exit(spec_fpga);
err_vic:
return err;
err_dev:
err_name:
err_valid:
iounmap(spec_fpga->fpga);
err_map:
kfree(spec_fpga);
spec_gn412x->spec_fpga = NULL;
return err;
}
int spec_fpga_exit(struct spec_gn412x *spec_gn412x)
{
struct spec_fpga *spec_fpga = spec_gn412x->spec_fpga;
if (!spec_fpga)
return 0;
spec_fpga_app_exit(spec_fpga);
spec_fmc_exit(spec_fpga);
spec_fpga_devices_exit(spec_fpga);
spec_fpga_dma_exit(spec_fpga);
spec_fpga_vic_exit(spec_fpga);
spec_fpga_dbg_exit(spec_fpga);
device_unregister(&spec_fpga->dev);
iounmap(spec_fpga->fpga);
kfree(spec_fpga);
spec_gn412x->spec_fpga = NULL;
return 0;
}
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/spec-core.c 0000664 0000000 0000000 00000045123 13707547500 0025362 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*
* Driver for SPEC (Simple PCI FMC carrier) board.
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#if KERNEL_VERSION(3, 17, 0) <= LINUX_VERSION_CODE
#include
#endif
#include "platform_data/gn412x-gpio.h"
#include "spec.h"
#include "spec-compat.h"
static char *spec_fw_name_45t = "spec-golden-45T.bin";
static char *spec_fw_name_100t = "spec-golden-100T.bin";
static char *spec_fw_name_150t = "spec-golden-150T.bin";
char *spec_fw_name = "";
module_param_named(fw_name, spec_fw_name, charp, 0444);
static int spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name);
/* Debugging */
static int spec_irq_dbg_info(struct seq_file *s, void *offset)
{
struct spec_gn412x *spec_gn412x = s->private;
seq_printf(s, "'%s':\n", dev_name(&spec_gn412x->pdev->dev));
seq_printf(s, " redirect: %d\n",
to_pci_dev(&spec_gn412x->pdev->dev)->irq);
seq_puts(s, " irq-mapping:\n");
seq_puts(s, " - hardware: 8\n");
seq_printf(s, " linux: %d\n",
gpiod_to_irq(spec_gn412x->gpiod[GN4124_GPIO_IRQ1]));
seq_puts(s, " - hardware: 9\n");
seq_printf(s, " linux: %d\n",
gpiod_to_irq(spec_gn412x->gpiod[GN4124_GPIO_IRQ0]));
return 0;
}
static int spec_irq_dbg_info_open(struct inode *inode, struct file *file)
{
struct spec_gn412x *spec = inode->i_private;
return single_open(file, spec_irq_dbg_info, spec);
}
static const struct file_operations spec_irq_dbg_info_ops = {
.owner = THIS_MODULE,
.open = spec_irq_dbg_info_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
#define SPEC_DBG_FW_BUF_LEN 128
static ssize_t spec_dbg_fw_write(struct file *file,
const char __user *buf,
size_t count, loff_t *ppos)
{
struct spec_gn412x *spec_gn412x = file->private_data;
char buf_l[SPEC_DBG_FW_BUF_LEN];
int err;
if (SPEC_DBG_FW_BUF_LEN < count) {
dev_err(&spec_gn412x->pdev->dev,
"Firmware name too long max %u\n",
SPEC_DBG_FW_BUF_LEN);
return -EINVAL;
}
memset(buf_l, 0, SPEC_DBG_FW_BUF_LEN);
err = copy_from_user(buf_l, buf, count);
if (err)
return -EFAULT;
err = spec_fw_load(spec_gn412x, buf_l);
if (err)
return err;
return count;
}
static const struct file_operations spec_dbg_fw_ops = {
.owner = THIS_MODULE,
.open = simple_open,
.write = spec_dbg_fw_write,
};
static void seq_printf_meta(struct seq_file *s, const char *indent,
struct spec_meta_id *meta)
{
seq_printf(s, "%sMetadata:\n", indent);
seq_printf(s, "%s - Vendor: 0x%08x\n", indent, meta->vendor);
seq_printf(s, "%s - Device: 0x%08x\n", indent, meta->device);
seq_printf(s, "%s - Version: 0x%08x\n", indent, meta->version);
seq_printf(s, "%s - BOM: 0x%08x\n", indent, meta->bom);
seq_printf(s, "%s - SourceID: 0x%08x%08x%08x%08x\n",
indent,
meta->src[0],
meta->src[1],
meta->src[2],
meta->src[3]);
seq_printf(s, "%s - CapabilityMask: 0x%08x\n", indent, meta->cap);
seq_printf(s, "%s - VendorUUID: 0x%08x%08x%08x%08x\n",
indent,
meta->uuid[0],
meta->uuid[1],
meta->uuid[2],
meta->uuid[3]);
}
static int spec_dbg_meta(struct seq_file *s, void *offset)
{
struct spec_gn412x *spec_gn412x = s->private;
struct resource *r0 = &spec_gn412x->pdev->resource[0];
void *iomem;
uint32_t app_offset;
if (!spec_gn412x->spec_fpga) {
iomem = ioremap(r0->start, resource_size(r0));
} else {
iomem = spec_gn412x->spec_fpga->fpga;
}
if (!iomem) {
dev_warn(&spec_gn412x->pdev->dev, "%s: Mapping failed\n",
__func__);
return -ENOMEM;
}
app_offset = ioread32(iomem + 0x40);
seq_printf_meta(s, "", iomem + SPEC_META_BASE);
seq_puts(s, "Application:\n");
seq_printf_meta(s, " ", iomem + app_offset);
if (!spec_gn412x->spec_fpga)
iounmap(iomem);
return 0;
}
static int spec_dbg_meta_open(struct inode *inode, struct file *file)
{
struct spec_gn412x *spec = inode->i_private;
return single_open(file, spec_dbg_meta, spec);
}
static const struct file_operations spec_dbg_meta_ops = {
.owner = THIS_MODULE,
.open = spec_dbg_meta_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
/**
* It initializes the debugfs interface
* @spec: SPEC device instance
*
* Return: 0 on success, otherwise a negative error number
*/
static int spec_dbg_init(struct spec_gn412x *spec_gn412x)
{
struct device *dev = &spec_gn412x->pdev->dev;
spec_gn412x->dbg_dir = debugfs_create_dir(dev_name(dev),
NULL);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_dir)) {
dev_err(dev, "Cannot create debugfs directory (%ld)\n",
PTR_ERR(spec_gn412x->dbg_dir));
return PTR_ERR(spec_gn412x->dbg_dir);
}
spec_gn412x->dbg_info = debugfs_create_file(SPEC_DBG_INFO_NAME, 0444,
spec_gn412x->dbg_dir,
spec_gn412x,
&spec_irq_dbg_info_ops);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_info)) {
dev_err(dev, "Cannot create debugfs file \"%s\" (%ld)\n",
SPEC_DBG_INFO_NAME, PTR_ERR(spec_gn412x->dbg_info));
return PTR_ERR(spec_gn412x->dbg_info);
}
spec_gn412x->dbg_fw = debugfs_create_file(SPEC_DBG_FW_NAME, 0200,
spec_gn412x->dbg_dir,
spec_gn412x,
&spec_dbg_fw_ops);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_fw)) {
dev_err(dev, "Cannot create debugfs file \"%s\" (%ld)\n",
SPEC_DBG_FW_NAME, PTR_ERR(spec_gn412x->dbg_fw));
return PTR_ERR(spec_gn412x->dbg_fw);
}
spec_gn412x->dbg_meta = debugfs_create_file(SPEC_DBG_META_NAME, 0200,
spec_gn412x->dbg_dir,
spec_gn412x,
&spec_dbg_meta_ops);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_meta)) {
dev_err(dev, "Cannot create debugfs file \"%s\" (%ld)\n",
SPEC_DBG_META_NAME, PTR_ERR(spec_gn412x->dbg_meta));
return PTR_ERR(spec_gn412x->dbg_meta);
}
return 0;
}
/**
* It removes the debugfs interface
* @spec: SPEC device instance
*/
static void spec_dbg_exit(struct spec_gn412x *spec_gn412x)
{
debugfs_remove_recursive(spec_gn412x->dbg_dir);
}
/* SPEC GPIO configuration */
static void spec_bootsel_set(struct spec_gn412x *spec_gn412x,
enum spec_fpga_select sel)
{
switch (sel) {
case SPEC_FPGA_SELECT_FPGA_FLASH:
case SPEC_FPGA_SELECT_GN4124_FPGA:
case SPEC_FPGA_SELECT_GN4124_FLASH:
gpiod_set_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0],
!!(sel & 0x1));
gpiod_set_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1],
!!(sel & 0x2));
break;
default:
break;
}
}
static enum spec_fpga_select spec_bootsel_get(struct spec_gn412x *spec_gn412x)
{
enum spec_fpga_select sel = 0;
sel |= !!gpiod_get_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1]) << 1;
sel |= !!gpiod_get_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0]) << 0;
return sel;
}
static const struct gpiod_lookup_table spec_gpiod_table = {
.table = {
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_BOOTSEL0,
"bootsel", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_BOOTSEL1,
"bootsel", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SPRI_DIN,
"spi", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SPRI_FLASH_CS,
"spi", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_IRQ0,
"irq", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_IRQ1,
"irq", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SCL,
"i2c", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SDA,
"i2c", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
{},
}
};
static inline size_t spec_gpiod_table_size(void)
{
return sizeof(struct gpiod_lookup_table) +
(sizeof(struct gpiod_lookup) * 9);
}
static int spec_gpio_init_table(struct spec_gn412x *spec_gn412x)
{
struct gpiod_lookup_table *lookup;
int err = 0;
lookup = kmemdup(&spec_gpiod_table, spec_gpiod_table_size(),
GFP_KERNEL);
if (!lookup)
return -ENOMEM;
lookup->dev_id = kstrdup(dev_name(&spec_gn412x->pdev->dev),
GFP_KERNEL);
if (!lookup->dev_id)
goto err_dup;
spec_gn412x->gpiod_table = lookup;
err = compat_gpiod_add_lookup_table(spec_gn412x->gpiod_table);
if (err)
goto err_lookup;
return 0;
err_lookup:
kfree(lookup->dev_id);
err_dup:
kfree(lookup);
return err;
}
static void spec_gpio_exit_table(struct spec_gn412x *spec_gn412x)
{
struct gpiod_lookup_table *lookup = spec_gn412x->gpiod_table;
gpiod_remove_lookup_table(lookup);
kfree(lookup->dev_id);
kfree(lookup);
spec_gn412x->gpiod_table = NULL;
}
/**
* Configure bootsel GPIOs
*
* Note: Because of a BUG in RedHat kernel 3.10 we re-set direction
*/
static int spec_gpio_init_bootsel(struct spec_gn412x *spec_gn412x)
{
struct gpio_desc *gpiod;
int err;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "bootsel", 0,
GPIOD_OUT_HIGH);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel0;
}
err = gpiod_direction_output(gpiod, 1);
if (err) {
gpiod_put(gpiod);
goto err_out0;
}
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0] = gpiod;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "bootsel", 1,
GPIOD_OUT_HIGH);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel1;
}
err = gpiod_direction_output(gpiod, 1);
if (err) {
gpiod_put(gpiod);
goto err_out1;
}
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1] = gpiod;
return 0;
err_out1:
err_sel1:
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0]);
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0] = NULL;
err_out0:
err_sel0:
return err;
}
static void spec_gpio_exit_bootsel(struct spec_gn412x *spec_gn412x)
{
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1]);
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1] = NULL;
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0]);
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0] = NULL;
}
/**
* Configure IRQ GPIOs
*
* Note: Because of a BUG in RedHat kernel 3.10 we re-set direction
*/
static int spec_gpio_init_irq(struct spec_gn412x *spec_gn412x)
{
struct gpio_desc *gpiod;
int err;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "irq", 0, GPIOD_IN);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel0;
}
err = gpiod_direction_input(gpiod);
if (err) {
gpiod_put(gpiod);
goto err_out0;
}
spec_gn412x->gpiod[GN4124_GPIO_IRQ0] = gpiod;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "irq", 1, GPIOD_IN);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel1;
}
err = gpiod_direction_input(gpiod);
if (err) {
gpiod_put(gpiod);
goto err_out1;
}
spec_gn412x->gpiod[GN4124_GPIO_IRQ1] = gpiod;
return 0;
err_out1:
err_sel1:
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_IRQ0]);
spec_gn412x->gpiod[GN4124_GPIO_IRQ0] = NULL;
err_out0:
err_sel0:
return err;
}
static void spec_gpio_exit_irq(struct spec_gn412x *spec_gn412x)
{
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_IRQ1]);
spec_gn412x->gpiod[GN4124_GPIO_IRQ1] = NULL;
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_IRQ0]);
spec_gn412x->gpiod[GN4124_GPIO_IRQ0] = NULL;
}
static int spec_gpio_init(struct spec_gn412x *spec_gn412x)
{
int err;
err = spec_gpio_init_table(spec_gn412x);
if (err)
return err;
err = spec_gpio_init_bootsel(spec_gn412x);
if (err)
goto err_bootsel;
err = spec_gpio_init_irq(spec_gn412x);
if (err)
goto err_irq;
return 0;
err_irq:
spec_gpio_exit_bootsel(spec_gn412x);
err_bootsel:
spec_gpio_exit_table(spec_gn412x);
return err;
}
static void spec_gpio_exit(struct spec_gn412x *spec_gn412x)
{
spec_gpio_exit_irq(spec_gn412x);
spec_gpio_exit_bootsel(spec_gn412x);
spec_gpio_exit_table(spec_gn412x);
}
/* SPEC sub-devices */
static struct gn412x_platform_data gn412x_gpio_pdata = {
.int_cfg = 0,
};
static struct resource gn412x_gpio_res[] = {
{
.name = "gn412x-gpio-mem",
.flags = IORESOURCE_MEM,
.start = 0,
.end = 0x1000 - 1,
}, {
.name = "gn412x-gpio-irq",
.flags = IORESOURCE_IRQ,
.start = 0,
.end = 0,
}
};
static struct resource gn412x_fcl_res[] = {
{
.name = "gn412x-fcl-mem",
.flags = IORESOURCE_MEM,
.start = 0,
.end = 0x1000 - 1,
},
};
enum spec_mfd_enum {
SPEC_MFD_GN412X_GPIO = 0,
SPEC_MFD_GN412X_FCL,
};
static const struct mfd_cell spec_mfd_devs[] = {
[SPEC_MFD_GN412X_GPIO] = {
.name = "gn412x-gpio",
.platform_data = &gn412x_gpio_pdata,
.pdata_size = sizeof(gn412x_gpio_pdata),
.num_resources = ARRAY_SIZE(gn412x_gpio_res),
.resources = gn412x_gpio_res,
},
[SPEC_MFD_GN412X_FCL] = {
.name = "gn412x-fcl",
.platform_data = NULL,
.pdata_size = 0,
.num_resources = ARRAY_SIZE(gn412x_fcl_res),
.resources = gn412x_fcl_res,
},
};
/**
* Return the SPEC defult FPGA firmware name based on PCI ID
* @spec: SPEC device
*
* Return: FPGA firmware name
*/
static const char *spec_fw_name_init_get(struct spec_gn412x *spec_gn412x)
{
if (strlen(spec_fw_name) > 0)
return spec_fw_name;
switch (spec_gn412x->pdev->device) {
case PCI_DEVICE_ID_SPEC_45T:
return spec_fw_name_45t;
case PCI_DEVICE_ID_SPEC_100T:
return spec_fw_name_100t;
case PCI_DEVICE_ID_SPEC_150T:
return spec_fw_name_150t;
default:
return NULL;
}
}
/**
* Load FPGA code
* @spec: SPEC device
* @name: FPGA bitstream file name
*
* Return: 0 on success, otherwise a negative error number
*/
static int spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name)
{
enum spec_fpga_select sel;
int err;
dev_dbg(&spec_gn412x->pdev->dev, "Writing firmware '%s'\n", name);
err = spec_fpga_exit(spec_gn412x);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Cannot remove FPGA device instances. Try to remove them manually and to reload this device instance\n");
return err;
}
mutex_lock(&spec_gn412x->mtx);
sel = spec_bootsel_get(spec_gn412x);
spec_bootsel_set(spec_gn412x, SPEC_FPGA_SELECT_GN4124_FPGA);
err = compat_spec_fw_load(spec_gn412x, name);
if (err)
goto out;
err = spec_fpga_init(spec_gn412x);
if (err)
dev_warn(&spec_gn412x->pdev->dev,
"FPGA incorrectly programmed %d\n", err);
out:
spec_bootsel_set(spec_gn412x, sel);
mutex_unlock(&spec_gn412x->mtx);
return err;
}
static ssize_t bootselect_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
enum spec_fpga_select sel;
if (strncmp("fpga-flash", buf, 8) == 0) {
sel = SPEC_FPGA_SELECT_FPGA_FLASH;
} else if (strncmp("gn4124-fpga", buf, 8) == 0) {
sel = SPEC_FPGA_SELECT_GN4124_FPGA;
} else if (strncmp("gn4124-flash", buf, 8) == 0) {
sel = SPEC_FPGA_SELECT_GN4124_FLASH;
} else {
dev_err(dev, "Unknown bootselect option '%s'\n",
buf);
return -EINVAL;
}
mutex_lock(&spec_gn412x->mtx);
spec_bootsel_set(spec_gn412x, sel);
mutex_unlock(&spec_gn412x->mtx);
return count;
}
static ssize_t bootselect_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
enum spec_fpga_select sel;
sel = spec_bootsel_get(spec_gn412x);
switch (sel) {
case SPEC_FPGA_SELECT_FPGA_FLASH:
return snprintf(buf, PAGE_SIZE, "fpga-flash\n");
case SPEC_FPGA_SELECT_GN4124_FPGA:
return snprintf(buf, PAGE_SIZE, "gn4124-fpga\n");
case SPEC_FPGA_SELECT_GN4124_FLASH:
return snprintf(buf, PAGE_SIZE, "gn4124-flash\n");
default:
dev_err(dev, "Unknown bootselect option '%x'\n",
sel);
return -EINVAL;
}
}
static DEVICE_ATTR_RW(bootselect);
/**
* Load golden bitstream on FGPA
*/
static ssize_t load_golden_fpga_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
int err;
err = spec_fw_load(spec_gn412x, spec_fw_name_init_get(spec_gn412x));
return err < 0 ? err : count;
}
static DEVICE_ATTR_WO(load_golden_fpga);
static struct attribute *gn412x_fpga_attrs[] = {
&dev_attr_load_golden_fpga.attr,
&dev_attr_bootselect.attr,
NULL,
};
static const struct attribute_group gn412x_fpga_group = {
.name = "fpga-options",
.attrs = gn412x_fpga_attrs,
};
static int spec_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct spec_gn412x *spec_gn412x;
int err = 0;
spec_gn412x = kzalloc(sizeof(*spec_gn412x), GFP_KERNEL);
if (!spec_gn412x)
return -ENOMEM;
mutex_init(&spec_gn412x->mtx);
pci_set_drvdata(pdev, spec_gn412x);
spec_gn412x->pdev = pdev;
err = pci_enable_device(pdev);
if (err) {
dev_err(&pdev->dev, "Failed to enable PCI device (%d)\n",
err);
goto err_enable;
}
pci_set_master(pdev);
err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
spec_mfd_devs,
ARRAY_SIZE(spec_mfd_devs),
&pdev->resource[4], pdev->irq, NULL);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to add MFD devices (%d)\n",
err);
goto err_mfd;
}
err = spec_gpio_init(spec_gn412x);
if (err) {
dev_err(&pdev->dev, "Failed to get GPIOs (%d)\n", err);
goto err_sgpio;
}
err = sysfs_create_group(&pdev->dev.kobj, &gn412x_fpga_group);
if (err)
goto err_sysfs;
spec_dbg_init(spec_gn412x);
mutex_lock(&spec_gn412x->mtx);
err = spec_fpga_init(spec_gn412x);
if (err)
dev_warn(&pdev->dev,
"FPGA incorrectly programmed or empty (%d)\n", err);
mutex_unlock(&spec_gn412x->mtx);
return 0;
err_sysfs:
spec_gpio_exit(spec_gn412x);
err_sgpio:
mfd_remove_devices(&pdev->dev);
err_mfd:
pci_disable_device(pdev);
err_enable:
kfree(spec_gn412x);
return err;
}
static void spec_remove(struct pci_dev *pdev)
{
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
spec_fpga_exit(spec_gn412x);
spec_dbg_exit(spec_gn412x);
sysfs_remove_group(&pdev->dev.kobj, &gn412x_fpga_group);
spec_gpio_exit(spec_gn412x);
mfd_remove_devices(&pdev->dev);
pci_disable_device(pdev);
kfree(spec_gn412x);
}
static const struct pci_device_id spec_pci_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_45T)},
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_100T)},
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_150T)},
{0,},
};
static struct pci_driver spec_driver = {
.driver = {
.owner = THIS_MODULE,
},
.name = "spec-fmc-carrier",
.probe = spec_probe,
.remove = spec_remove,
.id_table = spec_pci_tbl,
};
module_pci_driver(spec_driver);
MODULE_AUTHOR("Federico Vaga ");
MODULE_LICENSE("GPL v2");
MODULE_VERSION(VERSION);
MODULE_DESCRIPTION("Driver for the 'Simple PCIe FMC Carrier' a.k.a. SPEC");
MODULE_DEVICE_TABLE(pci, spec_pci_tbl);
MODULE_SOFTDEP("pre: gn412x_gpio gn412x_fcl htvic spec_gn412x_dma i2c_mux i2c-ocores spi-ocores");
ADDITIONAL_VERSIONS;
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/spec-gn412x-dma.c 0000664 0000000 0000000 00000062454 13707547500 0026222 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/**
* Copyright (C) 2017 CERN (www.cern.ch)
* Author: Federico Vaga
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
/**
* dma_cookie_complete - complete a descriptor
* @tx: descriptor to complete
*
* Mark this descriptor complete by updating the channels completed
* cookie marker. Zero the descriptors cookie to prevent accidental
* repeated completions.
*
* Note: caller is expected to hold a lock to prevent concurrency.
*/
static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
{
BUG_ON(tx->cookie < DMA_MIN_COOKIE);
tx->chan->completed_cookie = tx->cookie;
tx->cookie = 0;
}
/**
* dma_cookie_init - initialize the cookies for a DMA channel
* @chan: dma channel to initialize
*/
static inline void dma_cookie_init(struct dma_chan *chan)
{
chan->cookie = DMA_MIN_COOKIE;
chan->completed_cookie = DMA_MIN_COOKIE;
}
/**
* dma_cookie_assign - assign a DMA engine cookie to the descriptor
* @tx: descriptor needing cookie
*
* Assign a unique non-zero per-channel cookie to the descriptor.
* Note: caller is expected to hold a lock to prevent concurrency.
*/
static inline dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx)
{
struct dma_chan *chan = tx->chan;
dma_cookie_t cookie;
cookie = chan->cookie + 1;
if (cookie < DMA_MIN_COOKIE)
cookie = DMA_MIN_COOKIE;
tx->cookie = chan->cookie = cookie;
return cookie;
}
/**
* dma_cookie_status - report cookie status
* @chan: dma channel
* @cookie: cookie we are interested in
* @state: dma_tx_state structure to return last/used cookies
*
* Report the status of the cookie, filling in the state structure if
* non-NULL. No locking is required.
*/
static inline enum dma_status dma_cookie_status(struct dma_chan *chan,
dma_cookie_t cookie, struct dma_tx_state *state)
{
dma_cookie_t used, complete;
used = chan->cookie;
complete = chan->completed_cookie;
if (state) {
state->last = complete;
state->used = used;
state->residue = 0;
}
return dma_async_is_complete(cookie, complete, used);
}
enum gn412x_dma_regs {
GN412X_DMA_CTRL = 0x00,
GN412X_DMA_STAT = 0x04,
GN412X_DMA_ADDR_MEM = 0x08,
GN412X_DMA_ADDR_L = 0x0C,
GN412X_DMA_ADDR_H = 0x10,
GN412X_DMA_LEN = 0x14,
GN412X_DMA_NEXT_L = 0x18,
GN412X_DMA_NEXT_H = 0x1C,
GN412X_DMA_ATTR = 0x20,
GN412X_DMA_CUR_ADDR_MEM = 0x24,
GN412X_DMA_CUR_ADDR_L = 0x28,
GN412X_DMA_CUR_ADDR_H = 0x2C,
GN412X_DMA_CUR_LEN = 0x30,
};
enum gn412x_dma_regs_ctrl {
GN412X_DMA_CTRL_START = BIT(0),
GN412X_DMA_CTRL_ABORT = BIT(1),
GN412X_DMA_CTRL_SWAPPING = 0xC,
};
enum gn412x_dma_ctrl_swapping {
GN412X_DMA_CTRL_SWAPPING_NONE = 0,
GN412X_DMA_CTRL_SWAPPING_16,
GN412X_DMA_CTRL_SWAPPING_16_WORD,
GN412X_DMA_CTRL_SWAPPING_32,
};
#define GN412X_DMA_ATTR_DIR_MEM_TO_DEV (1 << 0)
#define GN412X_DMA_ATTR_CHAIN (1 << 1)
struct gn412x_dma_tx;
/**
* List of device identifiers
*/
enum gn412x_dma_id_enum {
GN412X_DMA_GN4124_IPCORE = 0,
};
enum gn412x_dma_state {
GN412X_DMA_STAT_IDLE = 0,
GN412X_DMA_STAT_BUSY,
GN412X_DMA_STAT_ERROR,
GN412X_DMA_STAT_ABORTED,
};
#define GN412X_DMA_STAT_ACK BIT(2)
#define GN412X_DMA_DDR_ALIGN 4
#define GN412X_DMA_DDR_SIZE (256 * 1024 * 1024)
#define GN412X_DMA_MAX_SEG_R GN412X_DMA_DDR_SIZE
#define GN412X_DMA_MAX_SEG_W 0x1000
/**
* Transfer descriptor an hardware transfer
* @start_addr: pointer where start to retrieve data from device memory
* @dma_addr_l: low 32bit of the dma address on host memory
* @dma_addr_h: high 32bit of the dma address on host memory
* @dma_len: number of bytes to transfer from device to host
* @next_addr_l: low 32bit of the address of the next memory area to use
* @next_addr_h: high 32bit of the address of the next memory area to use
* @attribute: dma information about data transferm. At the moment it is used
* only to provide the "last item" bit, direction is fixed to
* device->host
*
* note: it must be a power of 2 in order to be used also as alignement
* within the DMA pool
*/
struct gn412x_dma_tx_hw {
uint32_t start_addr;
uint32_t dma_addr_l;
uint32_t dma_addr_h;
uint32_t dma_len;
uint32_t next_addr_l;
uint32_t next_addr_h;
uint32_t attribute;
uint32_t reserved; /* alignement */
};
/**
* DMA channel descriptor
* @chan: dmaengine channel
* @pending_list: list of pending transfers
* @tx_curr: current transfer
* @task: tasklet for DMA start
* @lock: protects: pending_list, tx_curr, sconfig
* @sconfig: channel configuration to be used
* @error: number of errors detected
*/
struct gn412x_dma_chan {
struct dma_chan chan;
struct list_head pending_list;
struct gn412x_dma_tx *tx_curr;
struct tasklet_struct task;
spinlock_t lock;
struct dma_slave_config sconfig;
unsigned int error;
};
static inline struct gn412x_dma_chan *to_gn412x_dma_chan(struct dma_chan *_ptr)
{
return container_of(_ptr, struct gn412x_dma_chan, chan);
}
static inline bool gn412x_dma_has_pending_tx(struct gn412x_dma_chan *gn412x_dma_chan)
{
return !list_empty(&gn412x_dma_chan->pending_list);
}
/**
* DMA device descriptor
* @pdev: platform device associated
* @addr: component base address
* @dma: dmaengine device
* @chan: list of DMA channels
* @pool: shared DMA pool for HW descriptors
* @pool_list: list of HW descriptor allocated
*/
struct gn412x_dma_device {
struct platform_device *pdev;
void __iomem *addr;
struct dma_device dma;
struct gn412x_dma_chan chan;
struct dma_pool *pool;
struct list_head *pool_list;
struct dentry *dbg_dir;
#define GN412X_DMA_DBG_REG_NAME "regs"
struct dentry *dbg_reg;
struct debugfs_regset32 dbg_reg32;
};
static inline struct gn412x_dma_device *to_gn412x_dma_device(struct dma_device *_ptr)
{
return container_of(_ptr, struct gn412x_dma_device, dma);
}
/**
* DMA transfer descriptor
* @tx: dmaengine descriptor
* @sgl_hw: scattelist HW descriptors
* @sg_len: number of entries in the scatterlist
* @list: token to indentify this transfer in the pending list
*/
struct gn412x_dma_tx {
struct dma_async_tx_descriptor tx;
struct gn412x_dma_tx_hw **sgl_hw;
unsigned int sg_len;
struct list_head list;
};
static inline struct gn412x_dma_tx *to_gn412x_dma_tx(struct dma_async_tx_descriptor *_ptr)
{
return container_of(_ptr, struct gn412x_dma_tx, tx);
}
#define REG32(_name, _offset) {.name = _name, .offset = _offset}
static const struct debugfs_reg32 gn412x_dma_debugfs_reg32[] = {
REG32("DMACTRLR", GN412X_DMA_CTRL),
REG32("DMASTATR", GN412X_DMA_STAT),
REG32("DMACSTARTR", GN412X_DMA_ADDR_MEM),
REG32("DMAHSTARTLR", GN412X_DMA_ADDR_L),
REG32("DMAHSTARTHR", GN412X_DMA_ADDR_H),
REG32("DMALENR", GN412X_DMA_LEN),
REG32("DMANEXTLR", GN412X_DMA_NEXT_L),
REG32("DMANEXTHR", GN412X_DMA_NEXT_H),
REG32("DMAATTRIBR", GN412X_DMA_ATTR),
REG32("DMACURCSTARTR", GN412X_DMA_CUR_ADDR_MEM),
REG32("DMACURHSTARTLR", GN412X_DMA_CUR_ADDR_L),
REG32("DMACURHSTARTHR", GN412X_DMA_CUR_ADDR_H),
REG32("DMACURLENR", GN412X_DMA_CUR_LEN),
};
/**
* Start DMA transfer
* @gn412x_dma: DMA device
*/
static void gn412x_dma_ctrl_start(struct gn412x_dma_device *gn412x_dma)
{
uint32_t ctrl;
ctrl = ioread32(gn412x_dma->addr + GN412X_DMA_CTRL);
ctrl |= GN412X_DMA_CTRL_START;
iowrite32(ctrl, gn412x_dma->addr + GN412X_DMA_CTRL);
dev_dbg(&gn412x_dma->pdev->dev, "%s: stat: 0x%x\n",
__func__, ioread32(gn412x_dma->addr + GN412X_DMA_STAT));
}
/**
* Abort on going DMA transfer
* @gn412x_dma: DMA device
*/
static void gn412x_dma_ctrl_abort(struct gn412x_dma_device *gn412x_dma)
{
uint32_t ctrl;
ctrl = ioread32(gn412x_dma->addr + GN412X_DMA_CTRL);
ctrl |= GN412X_DMA_CTRL_ABORT;
iowrite32(ctrl, gn412x_dma->addr + GN412X_DMA_CTRL);
}
/**
* Set swapping option
* @gn412x_dma: DMA device
* @swap: swapping option
*/
static void gn412x_dma_ctrl_swapping(struct gn412x_dma_device *gn412x_dma,
enum gn412x_dma_ctrl_swapping swap)
{
uint32_t ctrl = swap;
iowrite32(ctrl, gn412x_dma->addr + GN412X_DMA_CTRL);
}
static enum gn412x_dma_state gn412x_dma_state(struct gn412x_dma_device *gn412x_dma)
{
return ioread32(gn412x_dma->addr + GN412X_DMA_STAT);
}
static bool gn412x_dma_is_busy(struct gn412x_dma_device *gn412x_dma)
{
uint32_t status;
status = ioread32(gn412x_dma->addr + GN412X_DMA_STAT);
return status & GN412X_DMA_STAT_BUSY;
}
static bool gn412x_dma_is_abort(struct gn412x_dma_device *gn412x_dma)
{
uint32_t status;
status = ioread32(gn412x_dma->addr + GN412X_DMA_STAT);
return status & GN412X_DMA_STAT_ABORTED;
}
static void gn412x_dma_irq_ack(struct gn412x_dma_device *gn412x_dma)
{
iowrite32(GN412X_DMA_STAT_ACK, gn412x_dma->addr + GN412X_DMA_STAT);
}
static void gn412x_dma_config(struct gn412x_dma_device *gn412x_dma,
struct gn412x_dma_tx_hw *tx_hw)
{
iowrite32(tx_hw->start_addr, gn412x_dma->addr + GN412X_DMA_ADDR_MEM);
iowrite32(tx_hw->dma_addr_l, gn412x_dma->addr + GN412X_DMA_ADDR_L);
iowrite32(tx_hw->dma_addr_h, gn412x_dma->addr + GN412X_DMA_ADDR_H);
iowrite32(tx_hw->dma_len, gn412x_dma->addr + GN412X_DMA_LEN);
iowrite32(tx_hw->next_addr_l, gn412x_dma->addr + GN412X_DMA_NEXT_L);
iowrite32(tx_hw->next_addr_h, gn412x_dma->addr + GN412X_DMA_NEXT_H);
iowrite32(tx_hw->attribute, gn412x_dma->addr + GN412X_DMA_ATTR);
}
static int gn412x_dma_alloc_chan_resources(struct dma_chan *dchan)
{
struct gn412x_dma_chan *chan = to_gn412x_dma_chan(dchan);
memset(&chan->sconfig, 0, sizeof(struct dma_slave_config));
return 0;
}
static void gn412x_dma_free_chan_resources(struct dma_chan *dchan)
{
}
/**
* Add a descriptor to the pending DMA transfer queue.
* This will not trigger any DMA transfer: here we just collect DMA
* transfer descriptions.
*/
static dma_cookie_t gn412x_dma_tx_submit(struct dma_async_tx_descriptor *tx)
{
struct gn412x_dma_tx *gn412x_dma_tx = to_gn412x_dma_tx(tx);
struct gn412x_dma_chan *chan = to_gn412x_dma_chan(tx->chan);
dma_cookie_t cookie;
unsigned long flags;
dev_dbg(&tx->chan->dev->device, "%s submit %p\n", __func__, tx);
spin_lock_irqsave(&chan->lock, flags);
cookie = dma_cookie_assign(tx);
list_add_tail(&gn412x_dma_tx->list, &chan->pending_list);
spin_unlock_irqrestore(&chan->lock, flags);
return cookie;
}
static void gn412x_dma_prep_fixup(struct gn412x_dma_tx_hw *tx_hw,
dma_addr_t next_addr)
{
if (!tx_hw || !next_addr)
return;
tx_hw->next_addr_l = ((next_addr >> 0) & 0xFFFFFFFF);
tx_hw->next_addr_h = ((next_addr >> 32) & 0xFFFFFFFF);
}
static void gn412x_dma_prep(struct gn412x_dma_tx_hw *tx_hw,
struct scatterlist *sg, dma_addr_t start_addr,
enum dma_transfer_direction direction)
{
tx_hw->start_addr = start_addr & 0xFFFFFFFF;
tx_hw->dma_addr_l = sg_dma_address(sg);
tx_hw->dma_addr_l &= 0xFFFFFFFF;
tx_hw->dma_addr_h = ((uint64_t)sg_dma_address(sg) >> 32);
tx_hw->dma_addr_h &= 0xFFFFFFFF;
tx_hw->dma_len = sg_dma_len(sg);
tx_hw->next_addr_l = 0x00000000;
tx_hw->next_addr_h = 0x00000000;
tx_hw->attribute = 0x0;
if (direction == DMA_MEM_TO_DEV)
tx_hw->attribute |= GN412X_DMA_ATTR_DIR_MEM_TO_DEV;
if (!sg_is_last(sg))
tx_hw->attribute |= GN412X_DMA_ATTR_CHAIN;
}
static struct dma_async_tx_descriptor *gn412x_dma_prep_slave_sg(
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
enum dma_transfer_direction direction, unsigned long flags,
void *context)
{
struct gn412x_dma_device *gn412x_dma = to_gn412x_dma_device(chan->device);
struct dma_slave_config *sconfig = &to_gn412x_dma_chan(chan)->sconfig;
struct gn412x_dma_tx *gn412x_dma_tx;
struct scatterlist *sg;
dma_addr_t src_addr;
int i;
if (unlikely(sconfig->direction != direction)) {
dev_err(&chan->dev->device,
"Transfer and slave configuration disagree on DMA direction\n");
goto err;
}
if (unlikely(!sgl || !sg_len)) {
dev_err(&chan->dev->device,
"You must provide a DMA scatterlist\n");
goto err;
}
gn412x_dma_tx = kzalloc(sizeof(struct gn412x_dma_tx), GFP_NOWAIT);
if (!gn412x_dma_tx)
goto err;
dma_async_tx_descriptor_init(&gn412x_dma_tx->tx, chan);
gn412x_dma_tx->tx.tx_submit = gn412x_dma_tx_submit;
gn412x_dma_tx->sg_len = sg_len;
/* Configure the hardware for this transfer */
gn412x_dma_tx->sgl_hw = kcalloc(gn412x_dma_tx->sg_len,
sizeof(struct gn412x_dma_tx_hw *),
GFP_KERNEL);
if (!gn412x_dma_tx->sgl_hw)
goto err_alloc_sglhw;
src_addr = sconfig->src_addr;
for_each_sg(sgl, sg, sg_len, i) {
dma_addr_t phys;
if (direction == DMA_MEM_TO_DEV &&
sg_dma_len(sg) > GN412X_DMA_MAX_SEG_W) {
dev_err(&chan->dev->device,
"Maximum write transfer size %d, got %d on transfer %d\n",
GN412X_DMA_MAX_SEG_W, sg_dma_len(sg), i);
goto err_alloc_pool;
} else if (sg_dma_len(sg) > dma_get_max_seg_size(chan->device->dev)) {
dev_err(&chan->dev->device,
"Maximum read transfer size %d, got %d on transfer %d\n",
dma_get_max_seg_size(chan->device->dev),
sg_dma_len(sg), i);
goto err_alloc_pool;
}
if (sg_dma_len(sg) & (GN412X_DMA_DDR_ALIGN - 1)) {
dev_err(&chan->dev->device,
"Transfer size must be aligne to %d Bytes, got %d Bytes\n",
GN412X_DMA_DDR_ALIGN, sg_dma_len(sg));
goto err_alloc_pool;
}
gn412x_dma_tx->sgl_hw[i] = dma_pool_alloc(gn412x_dma->pool,
GFP_DMA,
&phys);
if (!gn412x_dma_tx->sgl_hw[i])
goto err_alloc_pool;
if (i > 0) {
/*
* To build the chained transfer the previous
* descriptor (sgl_hw[i - 1]) must point to
* the physical address of current one (phys)
*/
gn412x_dma_prep_fixup(gn412x_dma_tx->sgl_hw[i - 1],
phys);
} else {
gn412x_dma_tx->tx.phys = phys;
}
gn412x_dma_prep(gn412x_dma_tx->sgl_hw[i], sg, src_addr,
direction);
src_addr += sg_dma_len(sg);
}
for_each_sg(sgl, sg, sg_len, i) {
struct gn412x_dma_tx_hw *tx_hw = gn412x_dma_tx->sgl_hw[i];
dev_dbg(&chan->dev->device,
"%s\n"
"\tsegment: %d\n"
"\tstart_addr: 0x%x\n"
"\tdma_addr_l: 0x%x\n"
"\tdma_addr_h: 0x%x\n"
"\tdma_len: 0x%x\n"
"\tnext_addr_l: 0x%x\n"
"\tnext_addr_h: 0x%x\n"
"\tattribute: 0x%x\n",
__func__, i,
tx_hw->start_addr,
tx_hw->dma_addr_l,
tx_hw->dma_addr_h,
tx_hw->dma_len,
tx_hw->next_addr_l,
tx_hw->next_addr_h,
tx_hw->attribute);
}
dev_dbg(&chan->dev->device, "%s prepared %p\n", __func__,
&gn412x_dma_tx->tx);
return &gn412x_dma_tx->tx;
err_alloc_pool:
while (--i >= 0)
dma_pool_free(gn412x_dma->pool,
gn412x_dma_tx->sgl_hw[i],
gn412x_dma_tx->tx.phys);
kfree(gn412x_dma_tx->sgl_hw);
err_alloc_sglhw:
kfree(gn412x_dma_tx);
err:
return NULL;
}
static void gn412x_dma_schedule_next(struct gn412x_dma_chan *gn412x_dma_chan)
{
unsigned long flags;
bool pending;
spin_lock_irqsave(&gn412x_dma_chan->lock, flags);
pending = gn412x_dma_has_pending_tx(gn412x_dma_chan);
spin_unlock_irqrestore(&gn412x_dma_chan->lock, flags);
if (pending)
tasklet_schedule(&gn412x_dma_chan->task);
}
static void gn412x_dma_issue_pending(struct dma_chan *chan)
{
gn412x_dma_schedule_next(to_gn412x_dma_chan(chan));
}
static void gn412x_dma_start_task(unsigned long arg)
{
struct gn412x_dma_chan *chan = (struct gn412x_dma_chan *)arg;
struct gn412x_dma_device *gn412x_dma;
unsigned long flags;
gn412x_dma = to_gn412x_dma_device(chan->chan.device);
if (unlikely(gn412x_dma_is_busy(gn412x_dma))) {
dev_err(&gn412x_dma->pdev->dev,
"Failed to start DMA transfer: channel busy\n");
return;
}
spin_lock_irqsave(&chan->lock, flags);
if (gn412x_dma_has_pending_tx(chan)) {
struct gn412x_dma_tx *tx;
tx = list_first_entry(&chan->pending_list,
struct gn412x_dma_tx, list);
list_del(&tx->list);
gn412x_dma_config(gn412x_dma, tx->sgl_hw[0]);
gn412x_dma_ctrl_swapping(gn412x_dma,
GN412X_DMA_CTRL_SWAPPING_NONE);
gn412x_dma_ctrl_start(gn412x_dma);
chan->tx_curr = tx;
}
spin_unlock_irqrestore(&chan->lock, flags);
}
static enum dma_status gn412x_dma_tx_status(struct dma_chan *chan,
dma_cookie_t cookie,
struct dma_tx_state *state)
{
return DMA_ERROR;
}
static int gn412x_dma_slave_config(struct dma_chan *chan,
struct dma_slave_config *sconfig)
{
struct gn412x_dma_chan *gn412x_dma_chan = to_gn412x_dma_chan(chan);
unsigned long flags;
spin_lock_irqsave(&gn412x_dma_chan->lock, flags);
memcpy(&gn412x_dma_chan->sconfig, sconfig,
sizeof(struct dma_slave_config));
spin_unlock_irqrestore(&gn412x_dma_chan->lock, flags);
if (gn412x_dma_chan->sconfig.src_addr & (GN412X_DMA_DDR_ALIGN - 1))
return -EINVAL;
return 0;
}
static int gn412x_dma_terminate_all(struct dma_chan *chan)
{
struct gn412x_dma_device *gn412x_dma;
struct gn412x_dma_tx *tx;
gn412x_dma = to_gn412x_dma_device(chan->device);
gn412x_dma_ctrl_abort(gn412x_dma);
/* FIXME remove all pending */
if (!gn412x_dma_is_abort(gn412x_dma)) {
dev_err(&gn412x_dma->pdev->dev,
"Failed to abort DMA transfer\n");
return -EINVAL;
}
tx = to_gn412x_dma_chan(chan)->tx_curr;
if (tx && tx->tx.callback_result) {
const struct dmaengine_result result = {
.result = DMA_TRANS_ABORTED,
.residue = 0,
};
tx->tx.callback_result(tx->tx.callback_param, &result);
}
return 0;
}
#if KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE
static int gn412x_dma_device_control(struct dma_chan *chan,
enum dma_ctrl_cmd cmd,
unsigned long arg)
{
switch (cmd) {
case DMA_SLAVE_CONFIG:
return gn412x_dma_slave_config(chan,
(struct dma_slave_config *)arg);
case DMA_TERMINATE_ALL:
return gn412x_dma_terminate_all(chan);
case DMA_PAUSE:
break;
case DMA_RESUME:
break;
default:
break;
}
return -ENODEV;
}
#endif
static irqreturn_t gn412x_dma_irq_handler(int irq, void *arg)
{
struct gn412x_dma_device *gn412x_dma = arg;
struct gn412x_dma_chan *chan = &gn412x_dma->chan;
struct gn412x_dma_tx *tx;
unsigned long flags;
unsigned int i;
enum gn412x_dma_state state;
/* FIXME check for spurious - need HDL fix */
gn412x_dma_irq_ack(gn412x_dma);
if (unlikely(chan->sconfig.direction == DMA_MEM_TO_DEV)) {
/*
* There is a bug in the HDL core, write path.
* The IRQ line is asserted before the actual end of transfer.
* A delay of 5us is the best compromise (empirical tests)
*/
ndelay(5000);
}
spin_lock_irqsave(&chan->lock, flags);
tx = chan->tx_curr;
chan->tx_curr = NULL;
spin_unlock_irqrestore(&chan->lock, flags);
state = gn412x_dma_state(gn412x_dma);
switch (state) {
case GN412X_DMA_STAT_IDLE:
dma_cookie_complete(&tx->tx);
if (tx->tx.callback_result) {
const struct dmaengine_result result = {
.result = DMA_TRANS_NOERROR,
.residue = 0,
};
tx->tx.callback_result(tx->tx.callback_param, &result);
} else if (tx->tx.callback) {
tx->tx.callback(tx->tx.callback_param);
}
break;
case GN412X_DMA_STAT_ERROR:
if (tx->tx.callback_result) {
const struct dmaengine_result result = {
.result = DMA_TRANS_READ_FAILED,
.residue = 0,
};
tx->tx.callback_result(tx->tx.callback_param, &result);
}
dev_err(&gn412x_dma->pdev->dev, "DMA transfer failed: error\n");
break;
default:
dev_err(&gn412x_dma->pdev->dev,
"DMA transfer failed: inconsitent state %d\n",
state);
break;
}
/* Clean up memory */
for (i = 0; i < tx->sg_len; ++i)
dma_pool_free(gn412x_dma->pool, tx->sgl_hw[i], tx->tx.phys);
kfree(tx->sgl_hw);
kfree(tx);
gn412x_dma_schedule_next(chan);
return IRQ_HANDLED;
}
static int gn412x_dma_dbg_init(struct gn412x_dma_device *gn412x_dma)
{
struct dentry *dir, *file;
int err;
dir = debugfs_create_dir(dev_name(&gn412x_dma->pdev->dev), NULL);
if (IS_ERR_OR_NULL(dir)) {
err = PTR_ERR(dir);
dev_warn(&gn412x_dma->pdev->dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(&gn412x_dma->pdev->dev), err);
goto err_dir;
}
gn412x_dma->dbg_reg32.regs = gn412x_dma_debugfs_reg32;
gn412x_dma->dbg_reg32.nregs = ARRAY_SIZE(gn412x_dma_debugfs_reg32);
gn412x_dma->dbg_reg32.base = gn412x_dma->addr;
file = debugfs_create_regset32(GN412X_DMA_DBG_REG_NAME, 0200,
dir, &gn412x_dma->dbg_reg32);
if (IS_ERR_OR_NULL(file)) {
err = PTR_ERR(file);
dev_warn(&gn412x_dma->pdev->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
GN412X_DMA_DBG_REG_NAME, err);
goto err_reg32;
}
gn412x_dma->dbg_dir = dir;
gn412x_dma->dbg_reg = file;
return 0;
err_reg32:
debugfs_remove_recursive(dir);
err_dir:
return err;
}
static void gn412x_dma_dbg_exit(struct gn412x_dma_device *gn412x_dma)
{
debugfs_remove_recursive(gn412x_dma->dbg_dir);
}
/**
* Configure DMA Engine configuration
*/
static int gn412x_dma_engine_init(struct gn412x_dma_device *gn412x_dma,
struct device *parent)
{
struct dma_device *dma = &gn412x_dma->dma;
dma->dev = parent;
if (dma_set_mask(dma->dev, DMA_BIT_MASK(64))) {
/* Check if hardware supports 32-bit DMA */
if (dma_set_mask(dma->dev, DMA_BIT_MASK(32))) {
dev_err(dma->dev,
"32-bit DMA addressing not available\n");
return -EINVAL;
}
}
INIT_LIST_HEAD(&dma->channels);
dma_cap_zero(dma->cap_mask);
dma_cap_set(DMA_SLAVE, dma->cap_mask);
dma_cap_set(DMA_PRIVATE, dma->cap_mask);
dma->device_alloc_chan_resources = gn412x_dma_alloc_chan_resources;
dma->device_free_chan_resources = gn412x_dma_free_chan_resources;
dma->device_prep_slave_sg = gn412x_dma_prep_slave_sg;
#if KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE
dma->device_control = gn412x_dma_device_control;
#else
/* TODO: adjust/verify addr widths, direction and granularity. */
dma->src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma->dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma->directions =
1 << DMA_DEV_TO_MEM |
1 << DMA_MEM_TO_DEV;
dma->residue_granularity = 0;
dma->device_config = gn412x_dma_slave_config;
dma->device_terminate_all = gn412x_dma_terminate_all;
#endif
dma->device_tx_status = gn412x_dma_tx_status;
dma->device_issue_pending = gn412x_dma_issue_pending;
gn412x_dma->chan.chan.device = dma;
list_add_tail(&gn412x_dma->chan.chan.device_node, &dma->channels);
INIT_LIST_HEAD(&gn412x_dma->chan.pending_list);
spin_lock_init(&gn412x_dma->chan.lock);
tasklet_init(&gn412x_dma->chan.task, gn412x_dma_start_task,
(unsigned long)&gn412x_dma->chan);
dma_set_max_seg_size(dma->dev, GN412X_DMA_DDR_SIZE);
gn412x_dma->pool = dma_pool_create(dev_name(dma->dev), dma->dev,
sizeof(struct gn412x_dma_tx_hw),
sizeof(struct gn412x_dma_tx_hw),
0);
if (!gn412x_dma->pool)
return -ENOMEM;
return 0;
}
/**
* Release DMa engine configuration
*/
static void gn412x_dma_engine_exit(struct gn412x_dma_device *gn412x_dma)
{
dma_pool_destroy(gn412x_dma->pool);
}
/**
* It creates a new instance of the GN4124 DMA engine
* @pdev: platform device
*
* @return: 0 on success otherwise a negative error code
*/
static int gn412x_dma_probe(struct platform_device *pdev)
{
struct gn412x_dma_device *gn412x_dma;
const struct resource *r;
int err;
/* FIXME set DMA mask on pdev? */
gn412x_dma = kzalloc(sizeof(struct gn412x_dma_device), GFP_KERNEL);
if (!gn412x_dma)
return -ENOMEM;
gn412x_dma->pdev = pdev;
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(&pdev->dev, "Missing memory resource\n");
err = -EINVAL;
goto err_res_mem;
}
gn412x_dma->addr = ioremap(r->start, resource_size(r));
if (!gn412x_dma->addr) {
err = -EADDRNOTAVAIL;
goto err_map;
}
err = request_any_context_irq(platform_get_irq(pdev, 0),
gn412x_dma_irq_handler, 0,
dev_name(&pdev->dev), gn412x_dma);
if (err < 0)
goto err_irq;
/* Get the pci_dev device because it is the one configured for DMA */
err = gn412x_dma_engine_init(gn412x_dma, pdev->dev.parent->parent);
if (err) {
dev_err(&pdev->dev, "Can't allocate DMA pool\n");
goto err_dma_init;
}
err = dma_async_device_register(&gn412x_dma->dma);
if (err)
goto err_reg;
gn412x_dma_dbg_init(gn412x_dma);
platform_set_drvdata(pdev, &gn412x_dma->dma);
return 0;
err_reg:
gn412x_dma_engine_exit(gn412x_dma);
err_dma_init:
free_irq(platform_get_irq(pdev, 0), gn412x_dma);
err_irq:
iounmap(gn412x_dma->addr);
err_map:
err_res_mem:
kfree(gn412x_dma);
return err;
}
/**
* It removes an instance of the GN4124 DMA engine
* @pdev: platform device
*
* @return: 0 on success otherwise a negative error code
*/
static int gn412x_dma_remove(struct platform_device *pdev)
{
struct dma_device *dma = platform_get_drvdata(pdev);
struct gn412x_dma_device *gn412x_dma = to_gn412x_dma_device(dma);
gn412x_dma_dbg_exit(gn412x_dma);
dmaengine_terminate_all(&gn412x_dma->chan.chan);
dma_async_device_unregister(&gn412x_dma->dma);
gn412x_dma_engine_exit(gn412x_dma);
free_irq(platform_get_irq(pdev, 0), gn412x_dma);
iounmap(gn412x_dma->addr);
kfree(gn412x_dma);
return 0;
}
/**
* List of all the compatible devices
*/
static const struct platform_device_id gn412x_dma_id[] = {
{
.name = "spec-gn412x-dma",
.driver_data = GN412X_DMA_GN4124_IPCORE,
},
{}, /* last */
};
struct platform_driver gn412x_dma_driver = {
.driver = {
.name = KBUILD_MODNAME,
},
.probe = gn412x_dma_probe,
.remove = gn412x_dma_remove,
.id_table = gn412x_dma_id
};
module_platform_driver(gn412x_dma_driver);
MODULE_AUTHOR("Federico Vaga ");
MODULE_DESCRIPTION("SPEC GN4124 IP-Core DMA engine");
MODULE_LICENSE("GPL");
MODULE_VERSION(VERSION);
MODULE_DEVICE_TABLE(platform, gn412x_dma_id);
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/kernel/spec.h 0000664 0000000 0000000 00000010363 13707547500 0024437 0 ustar 00root root 0000000 0000000 /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2010-2019 CERN (www.cern.ch)
* Author: Federico Vaga
* Author: Alessandro Rubini
*/
#ifndef __SPEC_H__
#define __SPEC_H__
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "gn412x.h"
#include "spec-core-fpga.h"
#define SPEC_FMC_SLOTS 1
/* On FPGA components */
#define PCI_VENDOR_ID_CERN (0x10DC)
#define PCI_DEVICE_ID_SPEC_45T (0x018D)
#define PCI_DEVICE_ID_SPEC_100T (0x01A2)
#define PCI_DEVICE_ID_SPEC_150T (0x01A3)
#define PCI_VENDOR_ID_GENNUM (0x1A39)
#define PCI_DEVICE_ID_GN4124 (0x0004)
#define GN4124_GPIO_MAX 16
#define GN4124_GPIO_BOOTSEL0 15
#define GN4124_GPIO_BOOTSEL1 14
#define GN4124_GPIO_SPRI_DIN 13
#define GN4124_GPIO_SPRI_FLASH_CS 12
#define GN4124_GPIO_IRQ0 9
#define GN4124_GPIO_IRQ1 8
#define GN4124_GPIO_SCL 5
#define GN4124_GPIO_SDA 4
#define SPEC_DDR_SIZE (256 * 1024 * 1024)
/**
* @SPEC_FPGA_SELECT_FPGA_FLASH: (default) the FPGA is an SPI master that can
* access the flash (at boot it takes its
* configuration from flash)
* @SPEC_FPGA_SELECT_GN4124_FPGA: the GN4124 can configure the FPGA
* @SPEC_FPGA_SELECT_GN4124_FLASH: the GN4124 is an SPI master that can access
* the flash
*/
enum spec_fpga_select {
SPEC_FPGA_SELECT_FPGA_FLASH = 0x3,
SPEC_FPGA_SELECT_GN4124_FPGA = 0x1,
SPEC_FPGA_SELECT_GN4124_FLASH = 0x0,
};
enum {
/* Metadata */
FPGA_META_VENDOR = 0x00,
FPGA_META_DEVICE = 0x04,
FPGA_META_VERSION = 0x08,
FPGA_META_BOM = 0x0C,
FPGA_META_SRC = 0x10,
FPGA_META_CAP = 0x20,
FPGA_META_UUID = 0x30,
};
enum {
/* Metadata */
SPEC_META_BASE = SPEC_BASE_REGS_METADATA,
SPEC_META_VENDOR = SPEC_META_BASE + FPGA_META_VENDOR,
SPEC_META_DEVICE = SPEC_META_BASE + FPGA_META_DEVICE,
SPEC_META_VERSION = SPEC_META_BASE + FPGA_META_VERSION,
SPEC_META_BOM = SPEC_META_BASE + FPGA_META_BOM,
SPEC_META_SRC = SPEC_META_BASE + FPGA_META_SRC,
SPEC_META_CAP = SPEC_META_BASE + FPGA_META_CAP,
SPEC_META_UUID = SPEC_META_BASE + FPGA_META_UUID,
};
#define SPEC_META_VENDOR_ID PCI_VENDOR_ID_CERN
#define SPEC_META_DEVICE_ID 0x53504543
#define SPEC_META_BOM_LE 0xFFFE0000
#define SPEC_META_BOM_END_MASK 0xFFFF0000
#define SPEC_META_BOM_VER_MASK 0x0000FFFF
#define SPEC_META_VERSION_MASK 0xFFFF0000
#define SPEC_META_VERSION_1_4 0x01040000
/**
* struct spec_meta_id Metadata
*/
struct spec_meta_id {
uint32_t vendor;
uint32_t device;
uint32_t version;
uint32_t bom;
uint32_t src[4];
uint32_t cap;
uint32_t uuid[4];
};
/**
* struct spec_fpga - it contains data to handle the FPGA
*
* @pdev: pointer to the PCI device
* @fpga:
* @meta:
* @vic_pdev:
* @app_pdev:
* @slot_info:
* @dbg_dir_fpga:
* @dbg_csr:
* @dbg_csr_reg:
*/
struct spec_fpga {
struct device dev;
void __iomem *fpga;
struct spec_meta_id __iomem *meta;
struct platform_device *vic_pdev;
struct platform_device *dma_pdev;
struct platform_device *app_pdev;
struct fmc_slot_info slot_info;
struct dentry *dbg_dir_fpga;
#define SPEC_DBG_CSR_NAME "csr_regs"
struct dentry *dbg_csr;
struct debugfs_regset32 dbg_csr_reg;
#define SPEC_DBG_BLD_INFO_NAME "build_info"
struct dentry *dbg_bld;
#define SPEC_DBG_DMA_NAME "dma"
struct dentry *dbg_dma;
};
/**
* struct spec_gn412x - it contains data to handle the PCB
*
* @pdev: pointer to the PCI device
* @mtx: it protects FPGA device/configuration loading
*/
struct spec_gn412x {
struct pci_dev *pdev;
struct mutex mtx;
struct gpiod_lookup_table *gpiod_table;
struct gpio_desc *gpiod[GN4124_GPIO_MAX];
struct dentry *dbg_dir;
#define SPEC_DBG_INFO_NAME "info"
struct dentry *dbg_info;
#define SPEC_DBG_FW_NAME "fpga_firmware"
struct dentry *dbg_fw;
#define SPEC_DBG_META_NAME "fpga_device_metadata"
struct dentry *dbg_meta;
struct spec_fpga *spec_fpga;
};
static inline struct spec_fpga *to_spec_fpga(struct device *_dev)
{
return container_of(_dev, struct spec_fpga, dev);
}
extern int spec_fpga_init(struct spec_gn412x *spec_gn412x);
extern int spec_fpga_exit(struct spec_gn412x *spec_gn412x);
#endif /* __SPEC_H__ */
spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/tools/ 0000775 0000000 0000000 00000000000 13707547500 0023211 5 ustar 00root root 0000000 0000000 spec-f2dfe5defc4ff78d0321ccf4ff25f81e8eb64fb3/software/tools/spec_dma_throughput.py 0000775 0000000 0000000 00000004554 13707547500 0027642 0 ustar 00root root 0000000 0000000 #!/usr/bin/python3
import os
import re
import argparse
import math
from matplotlib import pyplot
from PySPEC import PySPEC
def dma_time_get(trace):
start = re.search(r"([0-9]+\.[0-9]{6}): gn412x_dma_start_task", trace, re.MULTILINE)
assert start is not None, trace
assert len(start.groups()) == 1
end = re.search(r"([0-9]+\.[0-9]{6}): gn412x_dma_irq_handler", trace, re.MULTILINE)
assert end is not None, trace
assert len(end.groups()) == 1
return round(float(end.group(1)) - float(start.group(1)), 6)
def main():
parser = argparse.ArgumentParser(description='DMA Throughput')
parser.add_argument('--pci-id', dest='pciid', required=True,
help='SPEC PCI ID to use')
parser.add_argument('--min', default=4 * 1024, type=int,
help='Minimum transfer size in Bytes (default: 4096 Bytes). It is rounded to the lower power of 2.')
parser.add_argument('--max', default=4 * 1024 * 1024, type=int,
help='Maximum transfer size in Bytes (default: 4194304 Bytes). It is rounded to the lower power of 2.')
parser.add_argument('--seg', default=0, type=int,
help='Overwrite scatterlist segment size.')
args = parser.parse_args()
tracing_path = "/sys/kernel/debug/tracing"
with open(os.path.join(tracing_path, "current_tracer"), "w") as f:
f.write("function")
with open(os.path.join(tracing_path, "set_ftrace_filter"), "w") as f:
f.write("gn412x_dma_irq_handler\ngn412x_dma_start_task")
with open(os.path.join(tracing_path, "trace"), "w") as f:
f.write("")
spec = PySPEC(args.pciid)
throughput = []
sizes = [2**x for x in range(int(math.log2(args.min)), int(math.log2(args.max)) + 1)]
for size in sizes:
with open(os.path.join(tracing_path, "trace"), "w") as f:
f.write("")
with spec.dma(size) as dma:
dma.read(0, size, args.seg)
with open(os.path.join(tracing_path, "trace"), "r") as f:
throughput.append((float(size) / 1024 / 1024) / dma_time_get(f.read()))
print("{:d} Bytes -> {:f} MBps".format(size, throughput[-1]))
pyplot.title("DMA throughput at different block sizes")
pyplot.xlabel("DMA Size in Bytes")
pyplot.ylabel("Throughput in MBps")
pyplot.plot(sizes,throughput)
pyplot.show()
if __name__ == "__main__":
main()