pax_global_header 0000666 0000000 0000000 00000000064 13533225622 0014515 g ustar 00root root 0000000 0000000 52 comment=e1a905645e6e6420c2d2d19e82040d20a2315103
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/ 0000775 0000000 0000000 00000000000 13533225622 0017032 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/.gitignore 0000664 0000000 0000000 00000000216 13533225622 0021021 0 ustar 00root root 0000000 0000000 *.o
*.ko
*.mod.c
.*.o.cmd
.*.ko.cmd
*.mod.d
*.o.d
*.tmp
.tmp_versions
modules.order
Module.symvers
\#*
*~
GTAGS
GPATH
GRTAGS
Makefile.specific spec-e1a905645e6e6420c2d2d19e82040d20a2315103/.gitmodules 0000664 0000000 0000000 00000000743 13533225622 0021213 0 ustar 00root root 0000000 0000000 [submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/CHANGELOG 0000664 0000000 0000000 00000000242 13533225622 0020242 0 ustar 00root root 0000000 0000000 # Changelog
## [x.x.x] 2012-12-14
### Changed
- HDL: GN412x-CORE upgrade
## [x.x.x] 2012-12-14
### Added
- HDL: golden bitstream
## [0.0.0]
Start the development
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/LICENSES/ 0000775 0000000 0000000 00000000000 13533225622 0020237 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/LICENSES/GPL-2.0.txt 0000664 0000000 0000000 00000043215 13533225622 0021724 0 ustar 00root root 0000000 0000000 GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
License is intended to guarantee your freedom to share and change free
software--to make sure the software is free for all its users. This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it. (Some other Free Software Foundation software is covered by
the GNU Lesser General Public License instead.) You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
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To protect your rights, we need to make restrictions that forbid
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We protect your rights with two steps: (1) copyright the software, and
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Finally, any free program is threatened constantly by software
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The precise terms and conditions for copying, distribution and
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GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
a notice placed by the copyright holder saying it may be distributed
under the terms of this General Public License. The "Program", below,
refers to any such program or work, and a "work based on the Program"
means either the Program or any derivative work under copyright law:
that is to say, a work containing the Program or a portion of it,
either verbatim or with modifications and/or translated into another
language. (Hereinafter, translation is included without limitation in
the term "modification".) Each licensee is addressed as "you".
Activities other than copying, distribution and modification are not
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running the Program is not restricted, and the output from the Program
is covered only if its contents constitute a work based on the
Program (independent of having been made by running the Program).
Whether that is true depends on what the Program does.
1. You may copy and distribute verbatim copies of the Program's
source code as you receive it, in any medium, provided that you
conspicuously and appropriately publish on each copy an appropriate
copyright notice and disclaimer of warranty; keep intact all the
notices that refer to this License and to the absence of any warranty;
and give any other recipients of the Program a copy of this License
along with the Program.
You may charge a fee for the physical act of transferring a copy, and
you may at your option offer warranty protection in exchange for a fee.
2. You may modify your copy or copies of the Program or any portion
of it, thus forming a work based on the Program, and copy and
distribute such modifications or work under the terms of Section 1
above, provided that you also meet all of these conditions:
a) You must cause the modified files to carry prominent notices
stating that you changed the files and the date of any change.
b) You must cause any work that you distribute or publish, that in
whole or in part contains or is derived from the Program or any
part thereof, to be licensed as a whole at no charge to all third
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c) If the modified program normally reads commands interactively
when run, you must cause it, when started running for such
interactive use in the most ordinary way, to print or display an
announcement including an appropriate copyright notice and a
notice that there is no warranty (or else, saying that you provide
a warranty) and that users may redistribute the program under
these conditions, and telling the user how to view a copy of this
License. (Exception: if the Program itself is interactive but
does not normally print such an announcement, your work based on
the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
and can be reasonably considered independent and separate works in
themselves, then this License, and its terms, do not apply to those
sections when you distribute them as separate works. But when you
distribute the same sections as part of a whole which is a work based
on the Program, the distribution of the whole must be on the terms of
this License, whose permissions for other licensees extend to the
entire whole, and thus to each and every part regardless of who wrote it.
Thus, it is not the intent of this section to claim rights or contest
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exercise the right to control the distribution of derivative or
collective works based on the Program.
In addition, mere aggregation of another work not based on the Program
with the Program (or with a work based on the Program) on a volume of
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3. You may copy and distribute the Program (or a work based on it,
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This section is intended to make thoroughly clear what is believed to
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PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
spec-fmc-carrier
Copyright (C) 2019 CERN (https://home.cern)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
{signature of Ty Coon}, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/Manifest.py 0000664 0000000 0000000 00000000157 13533225622 0021155 0 ustar 00root root 0000000 0000000 modules = { "local" : [ "hdl/rtl" ] }
if action == "synthesis":
modules["local"].append("hdl/syn/common")
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/README.rst 0000664 0000000 0000000 00000000332 13533225622 0020517 0 ustar 00root root 0000000 0000000 ==============================
Simple PCIe FMC Carrier - SPEC
==============================
This git repository contains the HDL code necessary to enable most of
the SPEC features and the correspondent Linux driver.
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/distribution/ 0000775 0000000 0000000 00000000000 13533225622 0021551 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/distribution/.gitignore 0000664 0000000 0000000 00000000007 13533225622 0023536 0 ustar 00root root 0000000 0000000 build
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/distribution/Makefile 0000664 0000000 0000000 00000002455 13533225622 0023217 0 ustar 00root root 0000000 0000000 TOP_DIR ?= ../
DRIVER_NAME := spec-fmc-carrier
VERSION := $(shell git describe --abbrev=0)
DIR_NAME := $(DRIVER_NAME)-$(VERSION)
KEEP_TEMP ?= n
BUILD ?= $(abspath build)
BUILD_DKMS := $(BUILD)/dkms
BUILD_DKMSSOURCE := $(BUILD_DKMS)/source
BUILD_DKMSTREE := $(BUILD_DKMS)/tree
DKMS_OPT := --dkmstree $(BUILD_DKMSTREE) -m $(DRIVER_NAME)/$(VERSION)
all: kernel
kernel: dkms-tar dkms-rpm
dkms-tree:
@mkdir -p $(BUILD_DKMSSOURCE)
@mkdir -p $(BUILD_DKMSTREE)
dkms-src: dkms-tree
$(eval $@_src := $(shell git ls-tree -r --name-only HEAD $(TOP_DIR) | grep "kernel" | tr '\n' ' '))
$(eval $@_dir := $(BUILD_DKMSSOURCE)/$(DRIVER_NAME)-$(VERSION))
@mkdir -p $($@_dir)/platform_data
@cp -a $($@_src) $(TOP_DIR)/distribution/dkms.conf $($@_dir)
@mv $($@_dir)/gn412x-gpio.h $($@_dir)/platform_data
@cp -a $(TOP_DIR)/LICENSES/GPL-2.0.txt $($@_dir)/LICENSE
@sed -r -i -e "s/^VERSION\s=\s.*/VERSION = $(VERSION)/" $($@_dir)/Makefile
@sed -r -i -e "s/@PKGNAME@/$(DRIVER_NAME)/" $($@_dir)/dkms.conf
@sed -r -i -e "s/@PKGVER@/$(VERSION)/" $($@_dir)/dkms.conf
dkms-add: dkms-src
@dkms add $(DKMS_OPT) --sourcetree $(BUILD_DKMSSOURCE)
dkms-tar: dkms-add
@dkms mktarball $(DKMS_OPT) --source-only
dkms-rpm: dkms-add
@dkms mkrpm $(DKMS_OPT) --source-only
clean:
@rm -rf $(BUILD)
.PHONY: dkmstree dkms-add kernel-dkms-tar
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/distribution/dkms.conf 0000664 0000000 0000000 00000000635 13533225622 0023362 0 ustar 00root root 0000000 0000000 PACKAGE_NAME="@PKGNAME@"
PACKAGE_VERSION="@PKGVER@"
CLEAN="make clean"
MAKE[0]="make KVERSION=$kernelver all"
MAKE[1]="make KVERSION=$kernelver all"
MAKE[2]="make KVERSION=$kernelver all"
BUILT_MODULE_NAME[0]="@PKGNAME@"
BUILT_MODULE_NAME[1]="gn412x-gpio"
BUILT_MODULE_NAME[2]="gn412x-fcl"
DEST_MODULE_LOCATION[0]="/updates"
DEST_MODULE_LOCATION[1]="/updates"
DEST_MODULE_LOCATION[2]="/updates"
AUTOINSTALL="yes"
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/ 0000775 0000000 0000000 00000000000 13533225622 0017601 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/rtl/ 0000775 0000000 0000000 00000000000 13533225622 0020402 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/rtl/Manifest.py 0000664 0000000 0000000 00000000073 13533225622 0022522 0 ustar 00root root 0000000 0000000 files = ["spec_template_regs.vhd", "spec_template_wr.vhd"]
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/rtl/spec_template_regs.cheby 0000664 0000000 0000000 00000005463 13533225622 0025273 0 ustar 00root root 0000000 0000000 memory-map:
name: spec_template_regs
bus: wb-32-be
size: 0x2000
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
size: 0x40
interface: sram
- block:
name: csr
description: carrier and fmc status and control
address: 0x40
children:
- reg:
name: app_offset
description: offset to the application metadata
access: ro
width: 32
- reg:
name: resets
description: global and application resets
access: rw
width: 32
children:
- field:
name: global
range: 0
- field:
name: appl
range: 1
- reg:
name: fmc_presence
description: presence lines for the fmcs
access: ro
width: 32
- reg:
name: gn4124_status
description: status of gennum
access: ro
width: 32
# field 0: pll locked.
- reg:
name: ddr_status
description: status of the ddr3 controller
access: ro
width: 32
children:
- field:
description: Set when calibration is done.
name: calib_done
range: 0
- reg:
name: pcb_rev
description: pcb revision
access: ro
width: 32
children:
- field:
name: rev
range: 3-0
- submap:
name: therm_id
description: Thermometer and unique id
address: 0x70
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: fmc_i2c
description: i2c controllers to the fmcs
address: 0x80
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: flash_spi
description: spi controller to the flash
address: 0xa0
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: dma
description: dma registers for the gennum core
address: 0xc0
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: vic
description: vector interrupt controller
address: 0x100
size: 0x100
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: buildinfo
description: a ROM containing build information
size: 0x100
interface: sram
- submap:
name: wrc_regs
address: 0x1000
description: white-rabbit core registers
size: 0x1000
interface: wb-32-be
x-hdl:
busgroup: True
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/rtl/spec_template_regs.vhd 0000664 0000000 0000000 00000047423 13533225622 0024764 0 ustar 00root root 0000000 0000000 -- Do not edit; this file was generated by Cheby using these options:
-- --gen-hdl=spec_template_regs.vhd -i spec_template_regs.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_template_regs is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_adr_i : in std_logic_vector(12 downto 2);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_dat_i : in std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(31 downto 0);
-- a ROM containing the carrier metadata
metadata_addr_o : out std_logic_vector(5 downto 2);
metadata_data_i : in std_logic_vector(31 downto 0);
metadata_data_o : out std_logic_vector(31 downto 0);
-- offset to the application metadata
csr_app_offset_i : in std_logic_vector(31 downto 0);
csr_resets_global_o : out std_logic;
csr_resets_appl_o : out std_logic;
-- presence lines for the fmcs
csr_fmc_presence_i : in std_logic_vector(31 downto 0);
-- status of gennum
csr_gn4124_status_i : in std_logic_vector(31 downto 0);
-- Set when calibration is done.
csr_ddr_status_calib_done_i : in std_logic;
csr_pcb_rev_rev_i : in std_logic_vector(3 downto 0);
-- Thermometer and unique id
therm_id_i : in t_wishbone_master_in;
therm_id_o : out t_wishbone_master_out;
-- i2c controllers to the fmcs
fmc_i2c_i : in t_wishbone_master_in;
fmc_i2c_o : out t_wishbone_master_out;
-- spi controller to the flash
flash_spi_i : in t_wishbone_master_in;
flash_spi_o : out t_wishbone_master_out;
-- dma registers for the gennum core
dma_i : in t_wishbone_master_in;
dma_o : out t_wishbone_master_out;
-- vector interrupt controller
vic_i : in t_wishbone_master_in;
vic_o : out t_wishbone_master_out;
-- a ROM containing build information
buildinfo_addr_o : out std_logic_vector(7 downto 2);
buildinfo_data_i : in std_logic_vector(31 downto 0);
buildinfo_data_o : out std_logic_vector(31 downto 0);
-- white-rabbit core registers
wrc_regs_i : in t_wishbone_master_in;
wrc_regs_o : out t_wishbone_master_out
);
end spec_template_regs;
architecture syn of spec_template_regs is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_rack : std_logic;
signal metadata_re : std_logic;
signal csr_resets_global_reg : std_logic;
signal csr_resets_appl_reg : std_logic;
signal therm_id_re : std_logic;
signal therm_id_wt : std_logic;
signal therm_id_rt : std_logic;
signal therm_id_tr : std_logic;
signal therm_id_wack : std_logic;
signal therm_id_rack : std_logic;
signal fmc_i2c_re : std_logic;
signal fmc_i2c_wt : std_logic;
signal fmc_i2c_rt : std_logic;
signal fmc_i2c_tr : std_logic;
signal fmc_i2c_wack : std_logic;
signal fmc_i2c_rack : std_logic;
signal flash_spi_re : std_logic;
signal flash_spi_wt : std_logic;
signal flash_spi_rt : std_logic;
signal flash_spi_tr : std_logic;
signal flash_spi_wack : std_logic;
signal flash_spi_rack : std_logic;
signal dma_re : std_logic;
signal dma_wt : std_logic;
signal dma_rt : std_logic;
signal dma_tr : std_logic;
signal dma_wack : std_logic;
signal dma_rack : std_logic;
signal vic_re : std_logic;
signal vic_wt : std_logic;
signal vic_rt : std_logic;
signal vic_tr : std_logic;
signal vic_wack : std_logic;
signal vic_rack : std_logic;
signal buildinfo_rack : std_logic;
signal buildinfo_re : std_logic;
signal wrc_regs_re : std_logic;
signal wrc_regs_wt : std_logic;
signal wrc_regs_rt : std_logic;
signal wrc_regs_tr : std_logic;
signal wrc_regs_wack : std_logic;
signal wrc_regs_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_cyc_i and wb_stb_i;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wb_rip <= '0';
elsif rising_edge(clk_i) then
wb_rip <= (wb_rip or (wb_en and not wb_we_i)) and not rd_ack_int;
end if;
end process;
rd_int <= (wb_en and not wb_we_i) and not wb_rip;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wb_wip <= '0';
elsif rising_edge(clk_i) then
wb_wip <= (wb_wip or (wb_en and wb_we_i)) and not wr_ack_int;
end if;
end process;
wr_int <= (wb_en and wb_we_i) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_ack_o <= ack_int;
wb_stall_o <= not ack_int and wb_en;
wb_rty_o <= '0';
wb_err_o <= '0';
-- Assign outputs
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
metadata_rack <= '0';
elsif rising_edge(clk_i) then
metadata_rack <= metadata_re and not metadata_rack;
end if;
end process;
metadata_data_o <= wb_dat_i;
metadata_addr_o <= wb_adr_i(5 downto 2);
csr_resets_global_o <= csr_resets_global_reg;
csr_resets_appl_o <= csr_resets_appl_reg;
-- Assignments for submap therm_id
therm_id_tr <= therm_id_wt or therm_id_rt;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
therm_id_rt <= '0';
elsif rising_edge(clk_i) then
therm_id_rt <= (therm_id_rt or therm_id_re) and not therm_id_rack;
end if;
end process;
therm_id_o.cyc <= therm_id_tr;
therm_id_o.stb <= therm_id_tr;
therm_id_wack <= therm_id_i.ack and therm_id_wt;
therm_id_rack <= therm_id_i.ack and therm_id_rt;
therm_id_o.adr <= ((27 downto 0 => '0') & wb_adr_i(3 downto 2)) & (1 downto 0 => '0');
therm_id_o.sel <= (others => '1');
therm_id_o.we <= therm_id_wt;
therm_id_o.dat <= wb_dat_i;
-- Assignments for submap fmc_i2c
fmc_i2c_tr <= fmc_i2c_wt or fmc_i2c_rt;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
fmc_i2c_rt <= '0';
elsif rising_edge(clk_i) then
fmc_i2c_rt <= (fmc_i2c_rt or fmc_i2c_re) and not fmc_i2c_rack;
end if;
end process;
fmc_i2c_o.cyc <= fmc_i2c_tr;
fmc_i2c_o.stb <= fmc_i2c_tr;
fmc_i2c_wack <= fmc_i2c_i.ack and fmc_i2c_wt;
fmc_i2c_rack <= fmc_i2c_i.ack and fmc_i2c_rt;
fmc_i2c_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
fmc_i2c_o.sel <= (others => '1');
fmc_i2c_o.we <= fmc_i2c_wt;
fmc_i2c_o.dat <= wb_dat_i;
-- Assignments for submap flash_spi
flash_spi_tr <= flash_spi_wt or flash_spi_rt;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
flash_spi_rt <= '0';
elsif rising_edge(clk_i) then
flash_spi_rt <= (flash_spi_rt or flash_spi_re) and not flash_spi_rack;
end if;
end process;
flash_spi_o.cyc <= flash_spi_tr;
flash_spi_o.stb <= flash_spi_tr;
flash_spi_wack <= flash_spi_i.ack and flash_spi_wt;
flash_spi_rack <= flash_spi_i.ack and flash_spi_rt;
flash_spi_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
flash_spi_o.sel <= (others => '1');
flash_spi_o.we <= flash_spi_wt;
flash_spi_o.dat <= wb_dat_i;
-- Assignments for submap dma
dma_tr <= dma_wt or dma_rt;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
dma_rt <= '0';
elsif rising_edge(clk_i) then
dma_rt <= (dma_rt or dma_re) and not dma_rack;
end if;
end process;
dma_o.cyc <= dma_tr;
dma_o.stb <= dma_tr;
dma_wack <= dma_i.ack and dma_wt;
dma_rack <= dma_i.ack and dma_rt;
dma_o.adr <= ((25 downto 0 => '0') & wb_adr_i(5 downto 2)) & (1 downto 0 => '0');
dma_o.sel <= (others => '1');
dma_o.we <= dma_wt;
dma_o.dat <= wb_dat_i;
-- Assignments for submap vic
vic_tr <= vic_wt or vic_rt;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
vic_rt <= '0';
elsif rising_edge(clk_i) then
vic_rt <= (vic_rt or vic_re) and not vic_rack;
end if;
end process;
vic_o.cyc <= vic_tr;
vic_o.stb <= vic_tr;
vic_wack <= vic_i.ack and vic_wt;
vic_rack <= vic_i.ack and vic_rt;
vic_o.adr <= ((23 downto 0 => '0') & wb_adr_i(7 downto 2)) & (1 downto 0 => '0');
vic_o.sel <= (others => '1');
vic_o.we <= vic_wt;
vic_o.dat <= wb_dat_i;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
buildinfo_rack <= '0';
elsif rising_edge(clk_i) then
buildinfo_rack <= buildinfo_re and not buildinfo_rack;
end if;
end process;
buildinfo_data_o <= wb_dat_i;
buildinfo_addr_o <= wb_adr_i(7 downto 2);
-- Assignments for submap wrc_regs
wrc_regs_tr <= wrc_regs_wt or wrc_regs_rt;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wrc_regs_rt <= '0';
elsif rising_edge(clk_i) then
wrc_regs_rt <= (wrc_regs_rt or wrc_regs_re) and not wrc_regs_rack;
end if;
end process;
wrc_regs_o.cyc <= wrc_regs_tr;
wrc_regs_o.stb <= wrc_regs_tr;
wrc_regs_wack <= wrc_regs_i.ack and wrc_regs_wt;
wrc_regs_rack <= wrc_regs_i.ack and wrc_regs_rt;
wrc_regs_o.adr <= ((19 downto 0 => '0') & wb_adr_i(11 downto 2)) & (1 downto 0 => '0');
wrc_regs_o.sel <= (others => '1');
wrc_regs_o.we <= wrc_regs_wt;
wrc_regs_o.dat <= wb_dat_i;
-- Process for write requests.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wr_ack_int <= '0';
csr_resets_global_reg <= '0';
csr_resets_appl_reg <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
dma_wt <= '0';
vic_wt <= '0';
wrc_regs_wt <= '0';
elsif rising_edge(clk_i) then
wr_ack_int <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
dma_wt <= '0';
vic_wt <= '0';
wrc_regs_wt <= '0';
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
-- Submap metadata
when "01" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- Register csr_app_offset
when "01" =>
-- Register csr_resets
if wr_int = '1' then
csr_resets_global_reg <= wb_dat_i(0);
csr_resets_appl_reg <= wb_dat_i(1);
end if;
wr_ack_int <= wr_int;
when "10" =>
-- Register csr_fmc_presence
when "11" =>
-- Register csr_gn4124_status
when others =>
wr_ack_int <= wr_int;
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- Register csr_ddr_status
when "01" =>
-- Register csr_pcb_rev
when others =>
wr_ack_int <= wr_int;
end case;
when "11" =>
-- Submap therm_id
therm_id_wt <= (therm_id_wt or wr_int) and not therm_id_wack;
wr_ack_int <= therm_id_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
-- Submap fmc_i2c
fmc_i2c_wt <= (fmc_i2c_wt or wr_int) and not fmc_i2c_wack;
wr_ack_int <= fmc_i2c_wack;
when "1" =>
-- Submap flash_spi
flash_spi_wt <= (flash_spi_wt or wr_int) and not flash_spi_wack;
wr_ack_int <= flash_spi_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "11" =>
-- Submap dma
dma_wt <= (dma_wt or wr_int) and not dma_wack;
wr_ack_int <= dma_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "0001" =>
-- Submap vic
vic_wt <= (vic_wt or wr_int) and not vic_wack;
wr_ack_int <= vic_wack;
when "0010" =>
-- Submap buildinfo
when others =>
wr_ack_int <= wr_int;
end case;
when "1" =>
-- Submap wrc_regs
wrc_regs_wt <= (wrc_regs_wt or wr_int) and not wrc_regs_wack;
wr_ack_int <= wrc_regs_wack;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end process;
-- Process for registers read.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
rd_ack1_int <= '0';
reg_rdat_int <= (others => 'X');
elsif rising_edge(clk_i) then
reg_rdat_int <= (others => '0');
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
when "01" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_app_offset
reg_rdat_int <= csr_app_offset_i;
rd_ack1_int <= rd_int;
when "01" =>
-- csr_resets
reg_rdat_int(0) <= csr_resets_global_reg;
reg_rdat_int(1) <= csr_resets_appl_reg;
rd_ack1_int <= rd_int;
when "10" =>
-- csr_fmc_presence
reg_rdat_int <= csr_fmc_presence_i;
rd_ack1_int <= rd_int;
when "11" =>
-- csr_gn4124_status
reg_rdat_int <= csr_gn4124_status_i;
rd_ack1_int <= rd_int;
when others =>
rd_ack1_int <= rd_int;
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_ddr_status
reg_rdat_int(0) <= csr_ddr_status_calib_done_i;
rd_ack1_int <= rd_int;
when "01" =>
-- csr_pcb_rev
reg_rdat_int(3 downto 0) <= csr_pcb_rev_rev_i;
rd_ack1_int <= rd_int;
when others =>
rd_ack1_int <= rd_int;
end case;
when "11" =>
when others =>
rd_ack1_int <= rd_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
when "1" =>
when others =>
rd_ack1_int <= rd_int;
end case;
when "11" =>
when others =>
rd_ack1_int <= rd_int;
end case;
when "0001" =>
when "0010" =>
when others =>
rd_ack1_int <= rd_int;
end case;
when "1" =>
when others =>
rd_ack1_int <= rd_int;
end case;
end if;
end process;
-- Process for read requests.
process (wb_adr_i, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_data_i, metadata_rack, rd_int, therm_id_i.dat, therm_id_rack, therm_id_rt, rd_int, fmc_i2c_i.dat, fmc_i2c_rack, fmc_i2c_rt, rd_int, flash_spi_i.dat, flash_spi_rack, flash_spi_rt, rd_int, dma_i.dat, dma_rack, dma_rt, rd_int, vic_i.dat, vic_rack, vic_rt, rd_int, buildinfo_data_i, buildinfo_rack, rd_int, wrc_regs_i.dat, wrc_regs_rack, wrc_regs_rt) begin
-- By default ack read requests
wb_dat_o <= (others => '0');
metadata_re <= '0';
therm_id_re <= '0';
fmc_i2c_re <= '0';
flash_spi_re <= '0';
dma_re <= '0';
vic_re <= '0';
buildinfo_re <= '0';
wrc_regs_re <= '0';
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
-- Submap metadata
wb_dat_o <= metadata_data_i;
rd_ack_int <= metadata_rack;
metadata_re <= rd_int;
when "01" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_app_offset
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- csr_resets
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "10" =>
-- csr_fmc_presence
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "11" =>
-- csr_gn4124_status
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_ddr_status
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- csr_pcb_rev
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "11" =>
-- Submap therm_id
therm_id_re <= rd_int;
wb_dat_o <= therm_id_i.dat;
rd_ack_int <= therm_id_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
-- Submap fmc_i2c
fmc_i2c_re <= rd_int;
wb_dat_o <= fmc_i2c_i.dat;
rd_ack_int <= fmc_i2c_rack;
when "1" =>
-- Submap flash_spi
flash_spi_re <= rd_int;
wb_dat_o <= flash_spi_i.dat;
rd_ack_int <= flash_spi_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "11" =>
-- Submap dma
dma_re <= rd_int;
wb_dat_o <= dma_i.dat;
rd_ack_int <= dma_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "0001" =>
-- Submap vic
vic_re <= rd_int;
wb_dat_o <= vic_i.dat;
rd_ack_int <= vic_rack;
when "0010" =>
-- Submap buildinfo
wb_dat_o <= buildinfo_data_i;
rd_ack_int <= buildinfo_rack;
buildinfo_re <= rd_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "1" =>
-- Submap wrc_regs
wrc_regs_re <= rd_int;
wb_dat_o <= wrc_regs_i.dat;
rd_ack_int <= wrc_regs_rack;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/rtl/spec_template_wr.vhd 0000664 0000000 0000000 00000115141 13533225622 0024445 0 ustar 00root root 0000000 0000000 --------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_template_wr
--
-- description: SPEC carrier template, with WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.ddr3_ctrl_pkg.all;
use work.gn4124_core_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
use work.buildinfo_pkg.all;
use work.wr_fabric_pkg.all;
use work.streamers_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity spec_template_wr is
generic (
-- If true, instantiate a VIC/ONEWIRE/SPI/WR/DDRAM+DMA.
g_WITH_VIC : boolean := True;
g_WITH_ONEWIRE : boolean := True;
g_WITH_SPI : boolean := True;
g_WITH_WR : boolean := True;
g_WITH_DDR : boolean := True;
-- Address of the application meta-data. 0 if none.
g_APP_OFFSET : std_logic_vector(31 downto 0) := x"0000_0000";
-- Number of user interrupts
g_NUM_USER_IRQ : natural := 1;
-- WR PTP firmware.
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Fabric interface selection for WR Core:
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_FABRIC_IFACE : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_STREAMERS_OP_MODE : t_streamers_op_mode := TX_AND_RX;
g_TX_STREAMER_PARAMS : t_tx_streamer_params := c_TX_STREAMER_PARAMS_DEFAUT;
g_RX_STREAMER_PARAMS : t_rx_streamer_params := c_RX_STREAMER_PARAMS_DEFAUT;
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : integer := 0;
-- Increase information messages during simulation
g_VERBOSE : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- 125 MHz PLL reference
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
-- 20MHz VCXO clock (for WR)
clk_20m_vcxo_i : in std_logic;
-- 125 MHz GTP reference
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- Presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Miscellanous SPEC pins
---------------------------------------------------------------------------
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
------------------------------------------
-- DDR (bank 3)
------------------------------------------
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic;
------------------------------------------
-- User part
------------------------------------------
-- Direct access to the DDR-3
-- Classic wishbone
ddr_dma_clk_i : in std_logic;
ddr_dma_rst_n_i : in std_logic;
ddr_dma_wb_i : in t_wishbone_slave_data64_in;
ddr_dma_wb_o : out t_wishbone_slave_data64_out;
-- DDR FIFO empty flag
ddr_wr_fifo_empty_o : out std_logic;
-- Clocks and reset.
clk_sys_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
-- Interrupts
irq_user_i : in std_logic_vector(g_NUM_USER_IRQ + 5 downto 6) := (others => '0');
-- WR fabric interface (when g_fabric_iface = "plain")
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_DUMMY_SRC_IN;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_DUMMY_SNK_IN;
-- WR streamers (when g_fabric_iface = "streamers")
wrs_tx_data_i : in std_logic_vector(g_TX_STREAMER_PARAMS.DATA_WIDTH-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_TX_STREAMER_CFG_DEFAULT;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_RX_STREAMER_CFG_DEFAULT;
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
-- Timecode I/F
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
-- PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic;
-- The wishbone bus from the gennum/host to the application
-- Addresses 0-0x1fff are not available (used by the carrier).
-- This is a pipelined wishbone with byte granularity.
app_wb_o : out t_wishbone_master_out;
app_wb_i : in t_wishbone_master_in
);
end entity spec_template_wr;
architecture top of spec_template_wr is
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
signal clk_sys_62m5 : std_logic; -- 62.5Mhz
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
-- DDR
signal clk_ddr_333m : std_logic;
signal rst_ddr_333m_n : std_logic := '0';
signal ddr_rst : std_logic := '1';
signal ddr_status : std_logic_vector(31 downto 0);
signal ddr_calib_done : std_logic;
-- GN4124 core DMA port to DDR wishbone bus
signal gn_wb_ddr_in : t_wishbone_master_in;
signal gn_wb_ddr_out : t_wishbone_master_out;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
-- The wishbone bus to the carrier part.
signal carrier_wb_out : t_wishbone_slave_out;
signal carrier_wb_in : t_wishbone_slave_in;
signal gennum_status : std_logic_vector(31 downto 0);
signal metadata_addr : std_logic_vector(5 downto 2);
signal metadata_data : std_logic_vector(31 downto 0);
signal buildinfo_addr : std_logic_vector(7 downto 2);
signal buildinfo_data : std_logic_vector(31 downto 0);
signal therm_id_in : t_wishbone_master_in;
signal therm_id_out : t_wishbone_master_out;
-- i2c controllers to the fmcs
signal fmc_i2c_in : t_wishbone_master_in;
signal fmc_i2c_out : t_wishbone_master_out;
-- dma registers for the gennum core
signal dma_in : t_wishbone_master_in;
signal dma_out : t_wishbone_master_out;
-- spi controller to the flash
signal flash_spi_in : t_wishbone_master_in;
signal flash_spi_out : t_wishbone_master_out;
-- vector interrupt controller
signal vic_in : t_wishbone_master_in;
signal vic_out : t_wishbone_master_out;
-- white-rabbit core
signal wrc_in : t_wishbone_master_in;
signal wrc_out : t_wishbone_master_out;
signal wrc_out_sh : t_wishbone_master_out;
signal csr_rst_gbl : std_logic;
signal csr_rst_app : std_logic;
signal rst_csr_app_n : std_logic;
signal rst_csr_app_sync_n : std_logic;
signal rst_gbl_n : std_logic;
signal fmc0_scl_out, fmc0_sda_out : std_logic;
signal fmc0_scl_oen, fmc0_sda_oen : std_logic;
signal fmc_presence : std_logic_vector(31 downto 0);
signal irq_master : std_logic;
constant num_interrupts : natural := 6 + g_NUM_USER_IRQ;
signal irqs : std_logic_vector(num_interrupts - 1 downto 0);
-- clock and reset
signal rst_sys_62m5_n : std_logic;
signal rst_ref_125m_n : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ext_10m : std_logic;
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
signal eeprom_sda_out : std_logic;
signal eeprom_scl_in : std_logic;
signal eeprom_scl_out : std_logic;
-- SFP
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- LEDs and GPIO
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
attribute keep : string;
attribute keep of clk_sys_62m5 : signal is "TRUE";
attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of clk_ddr_333m : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE";
begin -- architecture top
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
gn_gpio_b(1) <= 'Z';
cmp_gn4124_core : entity work.xwb_gn4124_core
generic map (
g_WITH_DMA => g_WITH_DDR,
g_WBM_TO_WB_FIFO_SIZE => 16,
g_WBM_TO_WB_FIFO_FULL_THRES => 12,
g_WBM_FROM_WB_FIFO_SIZE => 16,
g_WBM_FROM_WB_FIFO_FULL_THRES => 12,
g_P2L_FIFO_SIZE => 256,
g_P2L_FIFO_FULL_THRES => 175,
g_L2P_ADDR_FIFO_FULL_SIZE => 256,
g_L2P_ADDR_FIFO_FULL_THRES => 175,
g_L2P_DATA_FIFO_FULL_SIZE => 256,
g_L2P_DATA_FIFO_FULL_THRES => 175
)
port map (
---------------------------------------------------------
-- Control and status
rst_n_a_i => gn_rst_n_i,
status_o => gennum_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
-- P2L Control
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
vc_rdy_i => gn_vc_rdy_i,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => gn_l2p_clk_p_o,
l2p_clk_n_o => gn_l2p_clk_n_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
-- L2P Control
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
---------------------------------------------------------
-- Interrupt interface
-- Note: the dma_irq are synchronized with the wb_master_clk clock
-- inside the gn4124 core.
dma_irq_o => irqs(2),
-- Note: this is a simple assignment.
irq_p_i => irq_master,
irq_p_o => gn_gpio_b(0),
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
wb_dma_cfg_clk_i => clk_sys_62m5,
wb_dma_cfg_rst_n_i => rst_sys_62m5_n,
wb_dma_cfg_i => dma_out,
wb_dma_cfg_o => dma_in,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
wb_master_clk_i => clk_sys_62m5,
wb_master_rst_n_i => rst_sys_62m5_n,
wb_master_o => gn_wb_out,
wb_master_i => gn_wb_in,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
wb_dma_dat_clk_i => clk_sys_62m5,
wb_dma_dat_rst_n_i => rst_gbl_n,
wb_dma_dat_o => gn_wb_ddr_out,
wb_dma_dat_i => gn_wb_ddr_in
);
-- Mini-crossbar from gennum to carrier and application bus.
inst_split: entity work.xwb_split
generic map (
g_mask => x"ffff_e000"
)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => gn_wb_out,
slave_o => gn_wb_in,
master_i (0) => carrier_wb_out,
master_i (1) => app_wb_i,
master_o (0) => carrier_wb_in,
master_o (1) => app_wb_o
);
inst_devs: entity work.spec_template_regs
port map (
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_cyc_i => carrier_wb_in.cyc,
wb_stb_i => carrier_wb_in.stb,
wb_adr_i => carrier_wb_in.adr (12 downto 2), -- Bytes address from gennum
wb_sel_i => carrier_wb_in.sel,
wb_we_i => carrier_wb_in.we,
wb_dat_i => carrier_wb_in.dat,
wb_ack_o => carrier_wb_out.ack,
wb_err_o => carrier_wb_out.err,
wb_rty_o => carrier_wb_out.rty,
wb_stall_o => carrier_wb_out.stall,
wb_dat_o => carrier_wb_out.dat,
-- a ROM containing the carrier metadata
metadata_addr_o => metadata_addr,
metadata_data_i => metadata_data,
metadata_data_o => open,
-- offset to the application metadata
csr_app_offset_i => g_APP_OFFSET,
csr_resets_global_o => csr_rst_gbl,
csr_resets_appl_o => csr_rst_app,
-- presence lines for the fmcs
csr_fmc_presence_i => fmc_presence,
csr_gn4124_status_i => gennum_status,
csr_ddr_status_calib_done_i => ddr_calib_done,
csr_pcb_rev_rev_i => pcbrev_i,
-- Thermometer and unique id
therm_id_i => therm_id_in,
therm_id_o => therm_id_out,
-- i2c controllers to the fmcs
fmc_i2c_i => fmc_i2c_in,
fmc_i2c_o => fmc_i2c_out,
-- dma registers for the gennum core
dma_i => dma_in,
dma_o => dma_out,
-- spi controller to the flash
flash_spi_i => flash_spi_in,
flash_spi_o => flash_spi_out,
-- vector interrupt controller
vic_i => vic_in,
vic_o => vic_out,
-- a ROM containing build info
buildinfo_addr_o => buildinfo_addr,
buildinfo_data_i => buildinfo_data,
buildinfo_data_o => open,
-- white-rabbit core
wrc_regs_i => wrc_in,
wrc_regs_o => wrc_out
);
fmc_presence (0) <= not fmc0_prsnt_m2c_n_i;
fmc_presence (31 downto 1) <= (others => '0');
-- Metadata
p_metadata: process (clk_sys_62m5) is
begin
if rising_edge(clk_sys_62m5) then
case metadata_addr is
when x"0" =>
-- Vendor ID
metadata_data <= x"000010dc";
when x"1" =>
-- Device ID
metadata_data <= x"53504543";
when x"2" =>
-- Version
metadata_data <= x"01040000";
when x"3" =>
-- BOM
metadata_data <= x"fffe0000";
when x"4" | x"5" | x"6" | x"7" =>
-- source id
metadata_data <= x"00000000";
when x"8" =>
-- capability mask
metadata_data <= x"00000000";
if g_WITH_VIC then
metadata_data(0) <= '1';
end if;
if g_WITH_ONEWIRE and not g_WITH_WR then
metadata_data(1) <= '1';
end if;
if g_WITH_SPI and not g_WITH_WR then
metadata_data(2) <= '1';
end if;
if g_WITH_WR then
metadata_data(3) <= '1';
end if;
-- Buildinfo
metadata_data(4) <= '1';
if g_WITH_DDR then
metadata_data(5) <= '1';
end if;
when others =>
metadata_data <= x"00000000";
end case;
end if;
end process;
-- Build information
p_buildinfo: process (clk_sys_62m5) is
variable addr : natural;
variable b : std_logic_vector(7 downto 0);
begin
if rising_edge(clk_sys_62m5) then
addr := to_integer(unsigned(buildinfo_addr)) * 4;
for i in 0 to 3 loop
if addr + i < buildinfo'length then
b := std_logic_vector(to_unsigned(character'pos(
buildinfo(buildinfo'left + addr + i)), 8));
else
b := x"00";
end if;
buildinfo_data (7 + i * 8 downto i * 8) <= b;
end loop;
end if;
end process;
rst_gbl_n <= rst_sys_62m5_n and (not csr_rst_gbl);
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
ddr_rst <= not rst_ddr_333m_n or csr_rst_gbl;
rst_csr_app_n <= not (csr_rst_gbl or csr_rst_app);
rst_sys_62m5_n_o <= rst_sys_62m5_n and rst_csr_app_n;
clk_sys_62m5_o <= clk_sys_62m5;
inst_rst_csr_app_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => rst_csr_app_n,
synced_o => rst_csr_app_sync_n);
rst_ref_125m_n_o <= rst_ref_125m_n and rst_csr_app_sync_n;
clk_ref_125m_o <= clk_ref_125m;
inst_i2c: entity work.xwb_i2c_master
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_interfaces => 1)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_gbl_n,
slave_i => fmc_i2c_out,
slave_o => fmc_i2c_in,
desc_o => open,
int_o => irqs(0),
scl_pad_i (0) => fmc0_scl_b,
scl_pad_o (0) => fmc0_scl_out,
scl_padoen_o (0) => fmc0_scl_oen,
sda_pad_i (0) => fmc0_sda_b,
sda_pad_o (0) => fmc0_sda_out,
sda_padoen_o (0) => fmc0_sda_oen
);
fmc0_scl_b <= fmc0_scl_out when fmc0_scl_oen = '0' else 'Z';
fmc0_sda_b <= fmc0_sda_out when fmc0_sda_oen = '0' else 'Z';
gen_user_irq: if g_NUM_USER_IRQ > 0 generate
irqs(irq_user_i'range) <= irq_user_i;
end generate gen_user_irq;
gen_vic: if g_with_vic generate
inst_vic: entity work.xwb_vic
generic map (
g_address_granularity => BYTE,
g_num_interrupts => num_interrupts,
g_FIXED_POLARITY => True,
g_POLARITY => '1'
)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_gbl_n,
slave_i => vic_out,
slave_o => vic_in,
irqs_i => irqs,
irq_master_o => irq_master
);
end generate;
gen_no_vic: if not g_with_vic generate
vic_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
irq_master <= '0';
end generate;
irqs(3) <= '0';
irqs(4) <= '0';
irqs(5) <= '0';
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master #2 (Etherbone))
-----------------------------------------------------------------------------
gen_wr: if g_WITH_WR generate
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
begin
-- Remap WR registers.
wrc_out_sh <= (cyc => wrc_out.cyc, stb => wrc_out.stb,
adr => wrc_out.adr or x"00020000",
sel => wrc_out.sel, we => wrc_out.we, dat => wrc_out.dat);
cmp_xwrc_board_spec : xwrc_board_spec
generic map (
g_simulation => g_SIMULATION,
g_VERBOSE => g_VERBOSE,
g_with_external_clock_input => TRUE,
g_dpram_initf => g_DPRAM_INITF,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG,
g_STREAMERS_OP_MODE => g_STREAMERS_OP_MODE,
g_TX_STREAMER_PARAMS => g_TX_STREAMER_PARAMS,
g_RX_STREAMER_PARAMS => g_RX_STREAMER_PARAMS,
g_FABRIC_IFACE => g_FABRIC_IFACE)
port map (
areset_n_i => button1_i,
areset_edge_n_i => gn_rst_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_ext_10m,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_pll_aux_o => clk_pll_aux,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
rst_pll_aux_n_o => rst_pll_aux_n,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_in,
eeprom_sda_o => eeprom_sda_out,
eeprom_scl_i => eeprom_scl_in,
eeprom_scl_o => eeprom_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
-- Uart
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- SPI Flash
flash_sclk_o => spi_sclk_o,
flash_ncs_o => spi_ncs_o,
flash_mosi_o => spi_mosi_o,
flash_miso_i => spi_miso_i,
wb_slave_o => wrc_in,
wb_slave_i => wrc_out_sh,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
wrf_snk_i => wrf_snk_i,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_i,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_i,
wb_eth_master_o => wb_eth_master_o,
wb_eth_master_i => wb_eth_master_i,
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => wrc_abscal_rxts_out,
tm_link_up_o => tm_link_up_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o,
led_link_o => led_link_o,
led_act_o => led_act_o);
clk_ddr_333m <= clk_pll_aux(0);
rst_ddr_333m_n <= rst_pll_aux_n(0);
clk_ext_10m <= '0';
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- tri-state onewire access
onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= onewire_b;
-- WR means neither onewire nor spi.
assert not g_WITH_ONEWIRE report "WR is not yet compatible with ONEWIRE"
severity failure;
assert not g_WITH_SPI report "WR is not yet compatible with SPI"
severity failure;
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0',
dat => (others => '0'));
flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0',
dat => (others => '0'));
irqs(1) <= '0';
end generate;
gen_no_wr: if not g_WITH_WR generate
signal clk_125m_pllref : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_62m5 : std_logic;
signal pllout_clk_125m : std_logic;
signal pllout_clk_333m : std_logic;
signal pllout_locked : std_logic;
signal rstlogic_arst : std_logic;
begin
-- Input clock
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3, -- 333 MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_62m5,
CLKOUT1 => pllout_clk_125m,
CLKOUT2 => pllout_clk_333m,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => pllout_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_clk_62m5_buf : BUFG
port map (
O => clk_sys_62m5,
I => pllout_clk_62m5);
cmp_clk_125m_buf : BUFG
port map (
O => clk_ref_125m,
I => pllout_clk_125m);
cmp_clk_333m_buf : BUFG
port map (
O => clk_ddr_333m,
I => pllout_clk_333m);
-- logic AND of all async reset sources (active high)
rstlogic_arst <= (not pllout_locked) and (not gn_rst_n_i);
-- Clocks required to have synced resets
cmp_rstlogic_reset : gc_reset_multi_aasd
generic map (
g_CLOCKS => 3,
g_RST_LEN => 16) -- 16 clock cycles
port map (
arst_i => rstlogic_arst,
clks_i (0) => clk_sys_62m5,
clks_i (1) => clk_ref_125m,
clks_i (2) => clk_ddr_333m,
rst_n_o (0) => rst_sys_62m5_n,
rst_n_o (1) => rst_ref_125m_n,
rst_n_o (2) => rst_ddr_333m_n);
-- Not used.
wrc_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
end generate;
gen_onewire: if g_WITH_ONEWIRE and not g_WITH_WR generate
inst_onewire: entity work.xwb_ds182x_readout
generic map (
g_CLOCK_FREQ_KHZ => 62_500,
g_USE_INTERNAL_PPS => True)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_gbl_n,
wb_i => therm_id_out,
wb_o => therm_id_in,
pps_p_i => '0',
onewire_b => onewire_b
);
end generate;
gen_no_onewire: if not g_WITH_ONEWIRE and not g_WITH_WR generate
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
onewire_b <= 'Z';
end generate;
gen_spi: if g_WITH_SPI and not g_WITH_WR generate
inst_spi: entity work.xwb_spi
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_divider_len => open,
g_max_char_len => open,
g_num_slaves => 1
)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_gbl_n,
slave_i => flash_spi_out,
slave_o => flash_spi_in,
desc_o => open,
int_o => irqs(1),
pad_cs_o(0) => spi_ncs_o,
pad_sclk_o => spi_sclk_o,
pad_mosi_o => spi_mosi_o,
pad_miso_i => spi_miso_i
);
end generate;
gen_no_spi: if not g_WITH_SPI and not g_WITH_WR generate
flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
end generate;
-- DDR3 controller
gen_with_ddr: if g_WITH_DDR generate
cmp_ddr_ctrl_bank3 : entity work.ddr3_ctrl
generic map(
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => "SPEC_BANK3_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => boolean'image(g_SIMULATION /= 0),
g_CALIB_SOFT_IP => "TRUE",
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => clk_ddr_333m,
rst_n_i => ddr_rst,
status_o => ddr_status,
ddr3_dq_b => ddr_dq_b,
ddr3_a_o => ddr_a_o,
ddr3_ba_o => ddr_ba_o,
ddr3_ras_n_o => ddr_ras_n_o,
ddr3_cas_n_o => ddr_cas_n_o,
ddr3_we_n_o => ddr_we_n_o,
ddr3_odt_o => ddr_odt_o,
ddr3_rst_n_o => ddr_reset_n_o,
ddr3_cke_o => ddr_cke_o,
ddr3_dm_o => ddr_ldm_o,
ddr3_udm_o => ddr_udm_o,
ddr3_dqs_p_b => ddr_ldqs_p_b,
ddr3_dqs_n_b => ddr_ldqs_n_b,
ddr3_udqs_p_b => ddr_udqs_p_b,
ddr3_udqs_n_b => ddr_udqs_n_b,
ddr3_clk_p_o => ddr_ck_p_o,
ddr3_clk_n_o => ddr_ck_n_o,
ddr3_rzq_b => ddr_rzq_b,
wb0_rst_n_i => ddr_dma_rst_n_i,
wb0_clk_i => ddr_dma_clk_i,
wb0_sel_i => ddr_dma_wb_i.sel,
wb0_cyc_i => ddr_dma_wb_i.cyc,
wb0_stb_i => ddr_dma_wb_i.stb,
wb0_we_i => ddr_dma_wb_i.we,
wb0_addr_i => ddr_dma_wb_i.adr,
wb0_data_i => ddr_dma_wb_i.dat,
wb0_data_o => ddr_dma_wb_o.dat,
wb0_ack_o => ddr_dma_wb_o.ack,
wb0_stall_o => ddr_dma_wb_o.stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty_o,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_gbl_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => gn_wb_ddr_out.sel,
wb1_cyc_i => gn_wb_ddr_out.cyc,
wb1_stb_i => gn_wb_ddr_out.stb,
wb1_we_i => gn_wb_ddr_out.we,
wb1_addr_i => gn_wb_ddr_out.adr,
wb1_data_i => gn_wb_ddr_out.dat,
wb1_data_o => gn_wb_ddr_in.dat,
wb1_ack_o => gn_wb_ddr_in.ack,
wb1_stall_o => gn_wb_ddr_in.stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
ddr_calib_done <= ddr_status(0);
-- unused Wishbone signals
gn_wb_ddr_in.err <= '0';
gn_wb_ddr_in.rty <= '0';
end generate gen_with_ddr;
gen_without_ddr : if not g_WITH_DDR generate
ddr_calib_done <= '0';
gn_wb_ddr_in <= c_DUMMY_WB_MASTER_IN;
ddr_a_o <= (others => '0');
ddr_ba_o <= (others => '0');
ddr_dq_b <= (others => 'Z');
ddr_cas_n_o <= '0';
ddr_ck_p_o <= '0';
ddr_ck_n_o <= '0';
ddr_cke_o <= '0';
ddr_ldm_o <= '0';
ddr_ldqs_n_b <= 'Z';
ddr_ldqs_p_b <= 'Z';
ddr_udqs_n_b <= 'Z';
ddr_udqs_p_b <= 'Z';
ddr_odt_o <= '0';
ddr_udm_o <= '0';
ddr_ras_n_o <= '0';
ddr_reset_n_o <= '0';
ddr_we_n_o <= '0';
ddr_rzq_b <= 'Z';
ddr_dma_wb_o.dat <= (others => '0');
ddr_dma_wb_o.ack <= '1';
ddr_dma_wb_o.stall <= '0';
ddr_wr_fifo_empty_o <= '0';
end generate gen_without_ddr;
ddr_dma_wb_o.err <= '0';
ddr_dma_wb_o.rty <= '0';
end architecture top;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/ 0000775 0000000 0000000 00000000000 13533225622 0020412 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/common/ 0000775 0000000 0000000 00000000000 13533225622 0021702 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/common/Manifest.py 0000664 0000000 0000000 00000000606 13533225622 0024024 0 ustar 00root root 0000000 0000000 files = ["spec_template_common.ucf"]
ucf_dict = {'wr': "spec_template_wr.ucf",
'onewire': "spec_template_onewire.ucf",
'spi': "spec_template_spi.ucf",
'ddr3': "spec_template_ddr3.ucf"}
for p in spec_template_ucf:
f = ucf_dict.get(p, None)
assert f is not None, "unknown name {} in 'spec_template_ucf'".format(p)
files.append(f)
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/common/spec_template_common.ucf 0000664 0000000 0000000 00000015460 13533225622 0026604 0 ustar 00root root 0000000 0000000 #===============================================================================
# IO Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# GN4124 PCIe bridge signals
#----------------------------------------
NET "gn_rst_n_i" LOC = N20;
NET "gn_p2l_clk_n_i" LOC = M19;
NET "gn_p2l_clk_p_i" LOC = M20;
NET "gn_p2l_rdy_o" LOC = J16;
NET "gn_p2l_dframe_i" LOC = J22;
NET "gn_p2l_valid_i" LOC = L19;
NET "gn_p2l_data_i[0]" LOC = K20;
NET "gn_p2l_data_i[1]" LOC = H22;
NET "gn_p2l_data_i[2]" LOC = H21;
NET "gn_p2l_data_i[3]" LOC = L17;
NET "gn_p2l_data_i[4]" LOC = K17;
NET "gn_p2l_data_i[5]" LOC = G22;
NET "gn_p2l_data_i[6]" LOC = G20;
NET "gn_p2l_data_i[7]" LOC = K18;
NET "gn_p2l_data_i[8]" LOC = K19;
NET "gn_p2l_data_i[9]" LOC = H20;
NET "gn_p2l_data_i[10]" LOC = J19;
NET "gn_p2l_data_i[11]" LOC = E22;
NET "gn_p2l_data_i[12]" LOC = E20;
NET "gn_p2l_data_i[13]" LOC = F22;
NET "gn_p2l_data_i[14]" LOC = F21;
NET "gn_p2l_data_i[15]" LOC = H19;
NET "gn_p_wr_req_i[0]" LOC = M22;
NET "gn_p_wr_req_i[1]" LOC = M21;
NET "gn_p_wr_rdy_o[0]" LOC = L15;
NET "gn_p_wr_rdy_o[1]" LOC = K16;
NET "gn_rx_error_o" LOC = J17;
NET "gn_l2p_clk_n_o" LOC = K22;
NET "gn_l2p_clk_p_o" LOC = K21;
NET "gn_l2p_dframe_o" LOC = U22;
NET "gn_l2p_valid_o" LOC = T18;
NET "gn_l2p_edb_o" LOC = U20;
NET "gn_l2p_data_o[0]" LOC = P16;
NET "gn_l2p_data_o[1]" LOC = P21;
NET "gn_l2p_data_o[2]" LOC = P18;
NET "gn_l2p_data_o[3]" LOC = T20;
NET "gn_l2p_data_o[4]" LOC = V21;
NET "gn_l2p_data_o[5]" LOC = V19;
NET "gn_l2p_data_o[6]" LOC = W22;
NET "gn_l2p_data_o[7]" LOC = Y22;
NET "gn_l2p_data_o[8]" LOC = P22;
NET "gn_l2p_data_o[9]" LOC = R22;
NET "gn_l2p_data_o[10]" LOC = T21;
NET "gn_l2p_data_o[11]" LOC = T19;
NET "gn_l2p_data_o[12]" LOC = V22;
NET "gn_l2p_data_o[13]" LOC = V20;
NET "gn_l2p_data_o[14]" LOC = W20;
NET "gn_l2p_data_o[15]" LOC = Y21;
NET "gn_l2p_rdy_i" LOC = U19;
NET "gn_l_wr_rdy_i[0]" LOC = R20;
NET "gn_l_wr_rdy_i[1]" LOC = T22;
NET "gn_p_rd_d_rdy_i[0]" LOC = N16;
NET "gn_p_rd_d_rdy_i[1]" LOC = P19;
NET "gn_tx_error_i" LOC = M17;
NET "gn_vc_rdy_i[0]" LOC = B21;
NET "gn_vc_rdy_i[1]" LOC = B22;
NET "gn_gpio_b[0]" LOC = U16; # GPIO8
NET "gn_gpio_b[1]" LOC = AB19; # GPIO9
NET "gn_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_clk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clk_n_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_clk_p_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error_i" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_gpio_b[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Misc
#----------------------------------------
NET "button1_n_i" LOC = C22;
NET "button1_n_i" IOSTANDARD = "LVCMOS18";
NET "pcbrev_i[0]" LOC = P5;
NET "pcbrev_i[1]" LOC = P4;
NET "pcbrev_i[2]" LOC = AA2;
NET "pcbrev_i[3]" LOC = AA1;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_scl_b" LOC = F7;
NET "fmc0_sda_b" LOC = F8;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i*" TIG;
NET "fmc0_prsnt_m2c_n_i" TIG;
#===============================================================================
# Timing Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "gn_p2l_clk_p_i" TNM_NET = "gn_p2l_clk";
NET "gn_p2l_clk_n_i" TNM_NET = "gn_p2l_clk";
TIMESPEC TS_gn_p2l_clk = PERIOD "gn_p2l_clk" 5 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref";
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref";
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_pllref" 8 ns HIGH 50%;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
NET "gn_rst_n_i" TIG;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "inst_spec_template/clk_sys_62m5" TNM_NET = sys_clk;
NET "inst_spec_template/clk_ref_125m" TNM_NET = ref_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_clk;
TIMEGRP "sys_grp" = "sys_clk" "ref_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_grp";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMESPEC TS_sys_sync_ffs = FROM sys_grp TO "sys_sync_ffs" TIG;
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_grp";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_* (3x multicycle)
NET "*/gc_sync_word_data[*]" TNM = FFS "sync_word";
TIMESPEC TS_sys_sync_word = FROM sync_word TO sys_clk 48ns DATAPATHONLY;
TIMESPEC TS_ref_sync_word = FROM sync_word TO ref_clk 24ns DATAPATHONLY;
# no gc_sync_word used in GN4124
#TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/common/spec_template_ddr3.ucf 0000664 0000000 0000000 00000007730 13533225622 0026151 0 ustar 00root root 0000000 0000000 ## DDR-3
NET "ddr_rzq_b" LOC = K7;
NET "ddr_we_n_o" LOC = H2;
NET "ddr_udqs_p_b" LOC = V2;
NET "ddr_udqs_n_b" LOC = V1;
NET "ddr_udm_o" LOC = P3;
NET "ddr_reset_n_o" LOC = E3;
NET "ddr_ras_n_o" LOC = M5;
NET "ddr_odt_o" LOC = L6;
NET "ddr_ldqs_p_b" LOC = N3;
NET "ddr_ldqs_n_b" LOC = N1;
NET "ddr_ldm_o" LOC = N4;
NET "ddr_cke_o" LOC = F2;
NET "ddr_ck_p_o" LOC = K4;
NET "ddr_ck_n_o" LOC = K3;
NET "ddr_cas_n_o" LOC = M4;
NET "ddr_dq_b[15]" LOC = Y1;
NET "ddr_dq_b[14]" LOC = Y2;
NET "ddr_dq_b[13]" LOC = W1;
NET "ddr_dq_b[12]" LOC = W3;
NET "ddr_dq_b[11]" LOC = U1;
NET "ddr_dq_b[10]" LOC = U3;
NET "ddr_dq_b[9]" LOC = T1;
NET "ddr_dq_b[8]" LOC = T2;
NET "ddr_dq_b[7]" LOC = M1;
NET "ddr_dq_b[6]" LOC = M2;
NET "ddr_dq_b[5]" LOC = L1;
NET "ddr_dq_b[4]" LOC = L3;
NET "ddr_dq_b[3]" LOC = P1;
NET "ddr_dq_b[2]" LOC = P2;
NET "ddr_dq_b[1]" LOC = R1;
NET "ddr_dq_b[0]" LOC = R3;
NET "ddr_ba_o[2]" LOC = H1;
NET "ddr_ba_o[1]" LOC = J1;
NET "ddr_ba_o[0]" LOC = J3;
NET "ddr_a_o[13]" LOC = J6;
NET "ddr_a_o[12]" LOC = F1;
NET "ddr_a_o[11]" LOC = E1;
NET "ddr_a_o[10]" LOC = J4;
NET "ddr_a_o[9]" LOC = G1;
NET "ddr_a_o[8]" LOC = G3;
NET "ddr_a_o[7]" LOC = K6;
NET "ddr_a_o[6]" LOC = L4;
NET "ddr_a_o[5]" LOC = M3;
NET "ddr_a_o[4]" LOC = H3;
NET "ddr_a_o[3]" LOC = M6;
NET "ddr_a_o[2]" LOC = K5;
NET "ddr_a_o[1]" LOC = K1;
NET "ddr_a_o[0]" LOC = K2;
# DDR IO standards and terminations
NET "ddr_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_p_b" IN_TERM = NONE;
NET "ddr_ldqs_n_b" IN_TERM = NONE;
NET "ddr_udqs_p_b" IN_TERM = NONE;
NET "ddr_udqs_n_b" IN_TERM = NONE;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "inst_spec_template/*cmp_ddr_ctrl_bank?/*/c?_pll_lock" TIG;
NET "inst_spec_template/*cmp_ddr_ctrl_bank?/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_spec_template/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_template/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
# Ignore async reset to DDR controller
NET "inst_spec_template/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "inst_spec_template/clk_ddr_333m" TNM_NET = ddr_clk;
NET "inst_spec_template/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_spec_template/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
# DDR does not use any sync modules
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/common/spec_template_onewire.ucf 0000664 0000000 0000000 00000000377 13533225622 0026765 0 ustar 00root root 0000000 0000000 ###########################################################################
## Onewire interface -> thermometer
###########################################################################
NET "onewire_b" LOC = D4;
NET "onewire_b" IOSTANDARD = "LVCMOS25";
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/common/spec_template_spi.ucf 0000664 0000000 0000000 00000000720 13533225622 0026100 0 ustar 00root root 0000000 0000000 ###########################################################################
## Flash memory SPI interface
###########################################################################
NET "spi_ncs_o" LOC = AA3;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS25";
NET "spi_sclk_o" LOC = Y20;
NET "spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "spi_mosi_o" LOC = AB20;
NET "spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "spi_miso_i" LOC = AA20;
NET "spi_miso_i" IOSTANDARD = "LVCMOS25";
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/common/spec_template_wr.ucf 0000664 0000000 0000000 00000010345 13533225622 0025741 0 ustar 00root root 0000000 0000000 #===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "plldac_sclk_o" LOC = A4;
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" LOC = C4;
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "pll25dac_cs_n_o" LOC = A3;
NET "pll25dac_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_cs_n_o" LOC = B3;
NET "pll20dac_cs_n_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_txp_o" LOC= B16;
NET "sfp_txn_o" LOC= A16;
NET "sfp_rxp_i" LOC= D15;
NET "sfp_rxn_i" LOC= C15;
NET "sfp_mod_def0_i" LOC = G15;
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" LOC = B18;
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_los_i" LOC = D18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD="LVCMOS25";
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD="LVCMOS25";
#----------------------------------------
# SFP LEDs
#----------------------------------------
NET "led_act_o" LOC = D5;
NET "led_act_o" IOSTANDARD = "LVCMOS25";
NET "led_link_o" LOC = E5;
NET "led_link_o" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
NET "clk_125m_gtp_p_i" TNM_NET = "clk_125m_gtp";
NET "clk_125m_gtp_n_i" TNM_NET = "clk_125m_gtp";
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "inst_spec_template/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int[1]" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
#-------------------------------------------------------------
# Constrain the phase between input and sampling clock in DMTD
#-------------------------------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1.25 ns DATAPATHONLY;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "*cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "*cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
# no gc_sync_reg for DMTD
#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
# no gc_sync_word for DMTD or PHY
#TIMESPEC TS_dmtd_sync_word = FROM sync_word TO clk_dmtd 48ns DATAPATHONLY;
#TIMESPEC TS_phy_sync_word = FROM sync_word TO phy_clk 24ns DATAPATHONLY;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/full/ 0000775 0000000 0000000 00000000000 13533225622 0021354 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/full/.gitignore 0000664 0000000 0000000 00000000067 13533225622 0023347 0 ustar 00root root 0000000 0000000 *
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/full/Manifest.py 0000664 0000000 0000000 00000001566 13533225622 0023504 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_full.xise"
syn_tool = "ise"
syn_top = "spec_full"
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/full",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/full/syn_extra_steps.tcl 0000664 0000000 0000000 00000002013 13533225622 0025306 0 ustar 00root root 0000000 0000000 # get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/golden/ 0000775 0000000 0000000 00000000000 13533225622 0021662 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/golden/Manifest.py 0000664 0000000 0000000 00000000665 13533225622 0024011 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden.xise"
syn_tool = "ise"
syn_top = "spec_golden"
modules = {
"local" : [
"../../top/golden",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
],
}
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/golden_wr-150T/ 0000775 0000000 0000000 00000000000 13533225622 0023021 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/golden_wr-150T/.gitignore 0000664 0000000 0000000 00000000067 13533225622 0025014 0 ustar 00root root 0000000 0000000 *
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/golden_wr-150T/Manifest.py 0000664 0000000 0000000 00000001605 13533225622 0025143 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden_wr",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/golden_wr-150T/syn_extra_steps.tcl 0000664 0000000 0000000 00000002013 13533225622 0026753 0 ustar 00root root 0000000 0000000 # get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/golden_wr/ 0000775 0000000 0000000 00000000000 13533225622 0022372 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/golden_wr/.gitignore 0000664 0000000 0000000 00000000067 13533225622 0024365 0 ustar 00root root 0000000 0000000 *
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/golden_wr/Manifest.py 0000664 0000000 0000000 00000001704 13533225622 0024514 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
spec_template_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/syn/golden_wr/syn_extra_steps.tcl 0000664 0000000 0000000 00000002013 13533225622 0026324 0 ustar 00root root 0000000 0000000 # get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/ 0000775 0000000 0000000 00000000000 13533225622 0020403 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/full/ 0000775 0000000 0000000 00000000000 13533225622 0021345 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/full/Manifest.py 0000664 0000000 0000000 00000000116 13533225622 0023463 0 ustar 00root root 0000000 0000000 files = ["spec_full.vhd", "spec_full.ucf"]
modules = {'local': ["../../rtl"]}
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/full/spec_full.ucf 0000664 0000000 0000000 00000035555 13533225622 0024035 0 ustar 00root root 0000000 0000000 #bank 0
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
###########################################################################
## GN4124 PCIe bridge signals
###########################################################################
NET "gn_rst_n" LOC = N20;
NET "gn_rst_n" IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_n" LOC = M19;
NET "gn_p2l_clk_n" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_clk_p" LOC = M20;
NET "gn_p2l_clk_p" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_rdy" LOC = J16;
NET "gn_p2l_rdy" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe" LOC = J22;
NET "gn_p2l_dframe" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid" LOC = L19;
NET "gn_p2l_valid" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[0]" LOC = K20;
NET "gn_p2l_data[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[1]" LOC = H22;
NET "gn_p2l_data[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[2]" LOC = H21;
NET "gn_p2l_data[2]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[3]" LOC = L17;
NET "gn_p2l_data[3]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[4]" LOC = K17;
NET "gn_p2l_data[4]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[5]" LOC = G22;
NET "gn_p2l_data[5]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[6]" LOC = G20;
NET "gn_p2l_data[6]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[7]" LOC = K18;
NET "gn_p2l_data[7]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[8]" LOC = K19;
NET "gn_p2l_data[8]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[9]" LOC = H20;
NET "gn_p2l_data[9]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[10]" LOC = J19;
NET "gn_p2l_data[10]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[11]" LOC = E22;
NET "gn_p2l_data[11]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[12]" LOC = E20;
NET "gn_p2l_data[12]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[13]" LOC = F22;
NET "gn_p2l_data[13]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[14]" LOC = F21;
NET "gn_p2l_data[14]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[15]" LOC = H19;
NET "gn_p2l_data[15]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req[0]" LOC = M22;
NET "gn_p_wr_req[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req[1]" LOC = M21;
NET "gn_p_wr_req[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy[0]" LOC = L15;
NET "gn_p_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy[1]" LOC = K16;
NET "gn_p_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error" LOC = J17;
NET "gn_rx_error" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clk_n" LOC = K22;
NET "gn_l2p_clk_n" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_clk_p" LOC = K21;
NET "gn_l2p_clk_p" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_dframe" LOC = U22;
NET "gn_l2p_dframe" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid" LOC = T18;
NET "gn_l2p_valid" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_edb" LOC = U20;
NET "gn_l2p_edb" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[0]" LOC = P16;
NET "gn_l2p_data[0]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[1]" LOC = P21;
NET "gn_l2p_data[1]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[2]" LOC = P18;
NET "gn_l2p_data[2]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[3]" LOC = T20;
NET "gn_l2p_data[3]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[4]" LOC = V21;
NET "gn_l2p_data[4]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[5]" LOC = V19;
NET "gn_l2p_data[5]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[6]" LOC = W22;
NET "gn_l2p_data[6]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[7]" LOC = Y22;
NET "gn_l2p_data[7]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[8]" LOC = P22;
NET "gn_l2p_data[8]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[9]" LOC = R22;
NET "gn_l2p_data[9]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[10]" LOC = T21;
NET "gn_l2p_data[10]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[11]" LOC = T19;
NET "gn_l2p_data[11]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[12]" LOC = V22;
NET "gn_l2p_data[12]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[13]" LOC = V20;
NET "gn_l2p_data[13]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[14]" LOC = W20;
NET "gn_l2p_data[14]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[15]" LOC = Y21;
NET "gn_l2p_data[15]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy" LOC = U19;
NET "gn_l2p_rdy" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy[0]" LOC = R20;
NET "gn_l_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy[1]" LOC = T22;
NET "gn_l_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy[0]" LOC = N16;
NET "gn_p_rd_d_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy[1]" LOC = P19;
NET "gn_p_rd_d_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error" LOC = M17;
NET "gn_tx_error" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy[0]" LOC = B21;
NET "gn_vc_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy[1]" LOC = B22;
NET "gn_vc_rdy[1]" IOSTANDARD = "SSTL18_I";
# GPIO 8 and 9 of the Genum
NET "GN_GPIO[0]" LOC = U16;
NET "GN_GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "GN_GPIO[1]" LOC = AB19;
NET "GN_GPIO[1]" IOSTANDARD = "LVCMOS25";
## DDR-3
NET "ddr_rzq_b" LOC = K7;
NET "ddr_we_n_o" LOC = H2;
NET "ddr_udqs_p_b" LOC = V2;
NET "ddr_udqs_n_b" LOC = V1;
NET "ddr_udm_o" LOC = P3;
NET "ddr_reset_n_o" LOC = E3;
NET "ddr_ras_n_o" LOC = M5;
NET "ddr_odt_o" LOC = L6;
NET "ddr_ldqs_p_b" LOC = N3;
NET "ddr_ldqs_n_b" LOC = N1;
NET "ddr_ldm_o" LOC = N4;
NET "ddr_cke_o" LOC = F2;
NET "ddr_ck_p_o" LOC = K4;
NET "ddr_ck_n_o" LOC = K3;
NET "ddr_cas_n_o" LOC = M4;
NET "ddr_dq_b[15]" LOC = Y1;
NET "ddr_dq_b[14]" LOC = Y2;
NET "ddr_dq_b[13]" LOC = W1;
NET "ddr_dq_b[12]" LOC = W3;
NET "ddr_dq_b[11]" LOC = U1;
NET "ddr_dq_b[10]" LOC = U3;
NET "ddr_dq_b[9]" LOC = T1;
NET "ddr_dq_b[8]" LOC = T2;
NET "ddr_dq_b[7]" LOC = M1;
NET "ddr_dq_b[6]" LOC = M2;
NET "ddr_dq_b[5]" LOC = L1;
NET "ddr_dq_b[4]" LOC = L3;
NET "ddr_dq_b[3]" LOC = P1;
NET "ddr_dq_b[2]" LOC = P2;
NET "ddr_dq_b[1]" LOC = R1;
NET "ddr_dq_b[0]" LOC = R3;
NET "ddr_ba_o[2]" LOC = H1;
NET "ddr_ba_o[1]" LOC = J1;
NET "ddr_ba_o[0]" LOC = J3;
NET "ddr_a_o[13]" LOC = J6;
NET "ddr_a_o[12]" LOC = F1;
NET "ddr_a_o[11]" LOC = E1;
NET "ddr_a_o[10]" LOC = J4;
NET "ddr_a_o[9]" LOC = G1;
NET "ddr_a_o[8]" LOC = G3;
NET "ddr_a_o[7]" LOC = K6;
NET "ddr_a_o[6]" LOC = L4;
NET "ddr_a_o[5]" LOC = M3;
NET "ddr_a_o[4]" LOC = H3;
NET "ddr_a_o[3]" LOC = M6;
NET "ddr_a_o[2]" LOC = K5;
NET "ddr_a_o[1]" LOC = K1;
NET "ddr_a_o[0]" LOC = K2;
# DDR IO standards and terminations
NET "ddr_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_p_b" IN_TERM = NONE;
NET "ddr_ldqs_n_b" IN_TERM = NONE;
NET "ddr_udqs_p_b" IN_TERM = NONE;
NET "ddr_udqs_n_b" IN_TERM = NONE;
###########################################################################
## SPI interface to DACs
###########################################################################
NET "plldac_sclk_o" LOC = A4;
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" LOC = C4;
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "pll25dac_cs_n_o" LOC = A3;
NET "pll25dac_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_cs_n_o" LOC = B3;
NET "pll20dac_cs_n_o" IOSTANDARD = "LVCMOS25";
###########################################################################
## SFP I/O for transceiver
###########################################################################
#NET "sfp_txp_o" IOSTANDARD = "LVDS_12";
NET "sfp_txp_o" LOC= B16;
#NET "sfp_txn_o" IOSTANDARD = "LVDS_12";
NET "sfp_txn_o" LOC= A16;
#NET "sfp_rxp_i" IOSTANDARD = "LVDS_12";
NET "sfp_rxp_i" LOC= D15;
#NET "sfp_rxn_i" IOSTANDARD = "LVDS_12";
NET "sfp_rxn_i" LOC= C15;
NET "sfp_mod_def0_i" LOC = G15;
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" LOC = B18;
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_los_i" LOC = D18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
###########################################################################
## Onewire interface -> thermometer
###########################################################################
NET "onewire_b" LOC = D4;
NET "onewire_b" IOSTANDARD = "LVCMOS25";
###########################################################################
## UART
###########################################################################
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
###########################################################################
## Flash memory SPI interface
###########################################################################
NET "spi_ncs_o" LOC = AA3;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS25";
NET "spi_sclk_o" LOC = Y20;
NET "spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "spi_mosi_o" LOC = AB20;
NET "spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "spi_miso_i" LOC = AA20;
NET "spi_miso_i" IOSTANDARD = "LVCMOS25";
###########################################################################
## Miscellanous SPEC pins
###########################################################################
NET "led_act_o" LOC = D5;
NET "led_act_o" IOSTANDARD = "LVCMOS25";
NET "led_link_o" LOC = E5;
NET "led_link_o" IOSTANDARD = "LVCMOS25";
NET "button1_i" LOC = C22;
NET "button1_i" IOSTANDARD = "LVCMOS18";
#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[0]" LOC = P5;
NET "pcbrev_i[1]" LOC = P4;
NET "pcbrev_i[2]" LOC = AA2;
NET "pcbrev_i[3]" LOC = AA1;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_scl_b" LOC = F7;
NET "fmc0_sda_b" LOC = F8;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i*" TIG;
NET "fmc0_prsnt_m2c_n_i" TIG;
# GN4124
NET "gn_p2l_clk_p" TNM_NET = "gn_p2l_clkp_grp";
NET "gn_p2l_clk_n" TNM_NET = "gn_p2l_clkn_grp";
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "inst_template/cmp_gn4124_core/cmp_wrapped_gn4124/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "gn_rst_n" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "inst_template/cmp_gn4124_core/cmp_wrapped_gn4124/cmp_clk_in/P_clk" TNM_NET = inst_template/cmp_gn4124_core/cmp_wrapped_gn4124/cmp_clk_in/P_clk;
#NET "inst_template/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = inst_template/cmp_gn4124_core/cmp_clk_in/P_clk;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
# Needed only when DMTD samples 125m refclock (clock has to be fed to D input of
# a flip-flop).
# However, in case of SPEC we use g_divide_input_by_2 generic in the dmtd_with_deglitcher.
# This re-generates 62.5MHz clock from 125Mhz and we don't feed 125M clock directly to D
# input of a flip-flop. This constraint would be needed e.g. for Kintex, where
# refclock is 62.5MHz and we don't use g_divide_input_by_2.
#PIN "WRC_PLATFORM/cmp_pllrefclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/02/20
NET "inst_template/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = inst_template/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "inst_template/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# Force PPS output to always be placed as IOB register
# INST "inst_template/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = FORCE;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "inst_template/*cmp_ddr_ctrl_bank?/*/c?_pll_lock" TIG;
NET "inst_template/*cmp_ddr_ctrl_bank?/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_template/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_template/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
# Ignore async reset to DDR controller
NET "inst_template/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
NET "inst_template/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_template/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/full/spec_full.vhd 0000664 0000000 0000000 00000026370 13533225622 0024034 0 ustar 00root root 0000000 0000000 --------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_full
--
-- description: SPEC "full" design, with access to all peripherals and features
-- of the carrier board.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_full is
generic (
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe : in std_logic; -- Receive Frame
gn_p2l_valid : in std_logic; -- Receive Data Valid
gn_p2l_data : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe : out std_logic; -- Transmit Data Frame
gn_l2p_valid : out std_logic; -- Transmit Data Valid
gn_l2p_edb : out std_logic; -- Packet termination and discard
gn_l2p_data : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error : in std_logic; -- Transmit Error
gn_vc_rdy : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Miscellanous SPEC pins
---------------------------------------------------------------------------
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
-- DDR3
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic
);
end entity spec_full;
architecture top of spec_full is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_template: entity work.spec_template_wr
generic map (
g_with_vic => True,
g_with_onewire => False,
g_with_spi => False,
g_with_ddr => True,
g_dpram_initf => g_dpram_initf,
g_simulation => g_simulation
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n,
gn_p2l_clk_n_i => gn_p2l_clk_n,
gn_p2l_clk_p_i => gn_p2l_clk_p,
gn_p2l_rdy_o => gn_p2l_rdy,
gn_p2l_dframe_i => gn_p2l_dframe,
gn_p2l_valid_i => gn_p2l_valid,
gn_p2l_data_i => gn_p2l_data,
gn_p_wr_req_i => gn_p_wr_req,
gn_p_wr_rdy_o => gn_p_wr_rdy,
gn_rx_error_o => gn_rx_error,
gn_l2p_clk_n_o => gn_l2p_clk_n,
gn_l2p_clk_p_o => gn_l2p_clk_p,
gn_l2p_dframe_o => gn_l2p_dframe,
gn_l2p_valid_o => gn_l2p_valid,
gn_l2p_edb_o => gn_l2p_edb,
gn_l2p_data_o => gn_l2p_data,
gn_l2p_rdy_i => gn_l2p_rdy,
gn_l_wr_rdy_i => gn_l_wr_rdy,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy,
gn_tx_error_i => gn_tx_error,
gn_vc_rdy_i => gn_vc_rdy,
gn_gpio_b => gn_gpio,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_i => button1_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_i.cyc => '0',
ddr_dma_wb_i.stb => '0',
ddr_dma_wb_i.adr => x"0000_0000",
ddr_dma_wb_i.sel => x"00",
ddr_dma_wb_i.we => '0',
ddr_dma_wb_i.dat => x"0000_0000_0000_0000",
ddr_dma_wb_o => open,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end architecture top;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/golden/ 0000775 0000000 0000000 00000000000 13533225622 0021653 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/golden/Manifest.py 0000664 0000000 0000000 00000000122 13533225622 0023766 0 ustar 00root root 0000000 0000000 files = ["spec_golden.vhd", "spec_golden.ucf"]
modules = {'local': ["../../rtl"]}
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/golden/spec_golden.ucf 0000664 0000000 0000000 00000016121 13533225622 0024635 0 ustar 00root root 0000000 0000000 #bank 0
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#NET "SFP_MOD_DEF1_b" LOC = C17;
#NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF0_b" LOC = G15;
#NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF2_b" LOC = G16;
#NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_RATE_SELECT_b" LOC = H14;
#NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_FAULT_i" LOC = A17;
#NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_DISABLE_o" LOC = F17;
#NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
#NET "SFP_LOS_i" LOC = D18;
#NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
#NET "BUTTON1_I" LOC = C22;
#NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
#NET "BUTTON2_I" LOC = D21;
#NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "SPI_NCS_O" LOC = AA3;
NET "SPI_NCS_O" IOSTANDARD = "LVCMOS25";
NET "SPI_SCLK_O" LOC = Y20;
NET "SPI_SCLK_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MOSI_O" LOC = AB20;
NET "SPI_MOSI_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MISO_I" LOC = AA20;
NET "SPI_MISO_I" IOSTANDARD = "LVCMOS25";
NET "GN_RST_N" LOC = N20;
NET "GN_RST_N" IOSTANDARD = "LVCMOS18";
NET "GN_L2P_CLK_N" LOC = K22;
NET "GN_L2P_CLK_N" IOSTANDARD = "DIFF_SSTL18_I";
NET "GN_L2P_CLK_P" LOC = K21;
NET "GN_L2P_CLK_P" IOSTANDARD = "DIFF_SSTL18_I";
NET "GN_L2P_DFRAME" LOC = U22;
NET "GN_L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_EDB" LOC = U20;
NET "GN_L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_RDY" LOC = U19;
NET "GN_L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_VALID" LOC = T18;
NET "GN_L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "GN_L_WR_RDY[0]" LOC = R20;
NET "GN_L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "GN_L_WR_RDY[1]" LOC = T22;
NET "GN_L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_CLK_N" LOC = M19;
NET "GN_P2L_CLK_N" IOSTANDARD = "DIFF_SSTL18_I";
NET "GN_P2L_CLK_P" LOC = M20;
NET "GN_P2L_CLK_P" IOSTANDARD = "DIFF_SSTL18_I";
NET "GN_P2L_DFRAME" LOC = J22;
NET "GN_P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_RDY" LOC = J16;
NET "GN_P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_VALID" LOC = L19;
NET "GN_P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "GN_P_RD_D_RDY[0]" LOC = N16;
NET "GN_P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "GN_P_RD_D_RDY[1]" LOC = P19;
NET "GN_P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "GN_P_WR_RDY[0]" LOC = L15;
NET "GN_P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "GN_P_WR_RDY[1]" LOC = K16;
NET "GN_P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "GN_P_WR_REQ[0]" LOC = M22;
NET "GN_P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "GN_P_WR_REQ[1]" LOC = M21;
NET "GN_P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "GN_RX_ERROR" LOC = J17;
NET "GN_RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "GN_TX_ERROR" LOC = M17;
NET "GN_TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "GN_VC_RDY[0]" LOC = B21;
NET "GN_VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "GN_VC_RDY[1]" LOC = B22;
NET "GN_VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[0]" LOC = P16;
NET "GN_L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[1]" LOC = P21;
NET "GN_L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[2]" LOC = P18;
NET "GN_L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[3]" LOC = T20;
NET "GN_L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[4]" LOC = V21;
NET "GN_L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[5]" LOC = V19;
NET "GN_L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[6]" LOC = W22;
NET "GN_L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[7]" LOC = Y22;
NET "GN_L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[8]" LOC = P22;
NET "GN_L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[9]" LOC = R22;
NET "GN_L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[10]" LOC = T21;
NET "GN_L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[11]" LOC = T19;
NET "GN_L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[12]" LOC = V22;
NET "GN_L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[13]" LOC = V20;
NET "GN_L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[14]" LOC = W20;
NET "GN_L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[15]" LOC = Y21;
NET "GN_L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[0]" LOC = K20;
NET "GN_P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[1]" LOC = H22;
NET "GN_P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[2]" LOC = H21;
NET "GN_P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[3]" LOC = L17;
NET "GN_P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[4]" LOC = K17;
NET "GN_P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[5]" LOC = G22;
NET "GN_P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[6]" LOC = G20;
NET "GN_P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[7]" LOC = K18;
NET "GN_P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[8]" LOC = K19;
NET "GN_P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[9]" LOC = H20;
NET "GN_P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[10]" LOC = J19;
NET "GN_P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[11]" LOC = E22;
NET "GN_P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[12]" LOC = E20;
NET "GN_P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[13]" LOC = F22;
NET "GN_P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[14]" LOC = F21;
NET "GN_P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[15]" LOC = H19;
NET "GN_P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
# GPIO 8 and 9 of the Genum
NET "GN_GPIO[0]" LOC = U16;
NET "GN_GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "GN_GPIO[1]" LOC = AB19;
NET "GN_GPIO[1]" IOSTANDARD = "LVCMOS25";
#NET "LED_RED" LOC = D5;
#NET "LED_RED" IOSTANDARD = "LVCMOS25";
#NET "LED_GREEN" LOC = E5;
#NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
# Onewire interface -> thermometer
NET "onewire_b" LOC = D4;
NET "onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_scl_b" LOC = F7;
NET "fmc0_sda_b" LOC = F8;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
#---------------------------------------------------------------------------------------------
# False Path
#---------------------------------------------------------------------------------------------
# GN4124
NET "gn_rst_n" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "inst_template/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = inst_template/cmp_gn4124_core/cmp_clk_in/P_clk;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "GN_P2L_CLK_p" TNM_NET = "p2l_clkp_grp";
NET "GN_P2L_CLK_n" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "inst_template/cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/golden/spec_golden.vhd 0000664 0000000 0000000 00000011750 13533225622 0024644 0 ustar 00root root 0000000 0000000 --------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_golden
--
-- description: SPEC golden design, without WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity spec_golden is
port (
-- Global ports
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
gn_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
gn_GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
gn_P2L_RDY : out std_logic; -- Rx Buffer Full Flag
gn_P2L_CLK_n : in std_logic; -- Receiver Source Synchronous Clock-
gn_P2L_CLK_p : in std_logic; -- Receiver Source Synchronous Clock+
gn_P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
gn_P2L_DFRAME : in std_logic; -- Receive Frame
gn_P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
gn_P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
gn_L2P_DFRAME : out std_logic; -- Transmit Data Frame
gn_L2P_VALID : out std_logic; -- Transmit Data Valid
gn_L2P_CLK_n : out std_logic; -- Transmitter Source Synchronous Clock-
gn_L2P_CLK_p : out std_logic; -- Transmitter Source Synchronous Clock+
gn_L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
gn_L2P_RDY : in std_logic; -- Tx Buffer Full Flag
gn_L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_TX_ERROR : in std_logic; -- Transmit Error
gn_VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-- Font panel LEDs
-- LED_RED : out std_logic;
-- LED_GREEN : out std_logic;
-- I2C to the FMC
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
onewire_b : inout std_logic;
-- button1_i : in std_logic;
-- button2_i : in std_logic;
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end spec_golden;
architecture rtl of spec_golden is
begin
inst_template: entity work.spec_template
generic map (
g_with_vic => true,
g_with_onewire => true,
g_with_spi => true
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n => gn_rst_n,
gn_gpio => gn_gpio,
gn_p2l_rdy => gn_p2l_rdy,
gn_p2l_clk_n => gn_p2l_clk_n,
gn_p2l_clk_p => gn_p2l_clk_p,
gn_p2l_data => gn_p2l_data,
gn_p2l_dframe => gn_p2l_dframe,
gn_p2l_valid => gn_p2l_valid,
gn_p_wr_req => gn_p_wr_req,
gn_p_wr_rdy => gn_p_wr_rdy,
gn_rx_error => gn_rx_error,
gn_l2p_data => gn_l2p_data,
gn_l2p_dframe => gn_l2p_dframe,
gn_l2p_valid => gn_l2p_valid,
gn_l2p_clk_n => gn_l2p_clk_n,
gn_l2p_clk_p => gn_l2p_clk_p,
gn_l2p_edb => gn_l2p_edb,
gn_l2p_rdy => gn_l2p_rdy,
gn_l_wr_rdy => gn_l_wr_rdy,
gn_p_rd_d_rdy => gn_p_rd_d_rdy,
gn_tx_error => gn_tx_error,
gn_vc_rdy => gn_vc_rdy,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i
);
end rtl;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/golden_wr/ 0000775 0000000 0000000 00000000000 13533225622 0022363 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/golden_wr/Manifest.py 0000664 0000000 0000000 00000000102 13533225622 0024474 0 ustar 00root root 0000000 0000000 files = ["spec_golden_wr.vhd"]
modules = {'local': ["../../rtl"]}
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/golden_wr/spec_golden_wr.ucf 0000664 0000000 0000000 00000026741 13533225622 0026066 0 ustar 00root root 0000000 0000000 #bank 0
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
###########################################################################
## GN4124 PCIe bridge signals
###########################################################################
NET "gn_rst_n" LOC = N20;
NET "gn_rst_n" IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_n" LOC = M19;
NET "gn_p2l_clk_n" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_clk_p" LOC = M20;
NET "gn_p2l_clk_p" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_rdy" LOC = J16;
NET "gn_p2l_rdy" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe" LOC = J22;
NET "gn_p2l_dframe" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid" LOC = L19;
NET "gn_p2l_valid" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[0]" LOC = K20;
NET "gn_p2l_data[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[1]" LOC = H22;
NET "gn_p2l_data[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[2]" LOC = H21;
NET "gn_p2l_data[2]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[3]" LOC = L17;
NET "gn_p2l_data[3]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[4]" LOC = K17;
NET "gn_p2l_data[4]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[5]" LOC = G22;
NET "gn_p2l_data[5]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[6]" LOC = G20;
NET "gn_p2l_data[6]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[7]" LOC = K18;
NET "gn_p2l_data[7]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[8]" LOC = K19;
NET "gn_p2l_data[8]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[9]" LOC = H20;
NET "gn_p2l_data[9]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[10]" LOC = J19;
NET "gn_p2l_data[10]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[11]" LOC = E22;
NET "gn_p2l_data[11]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[12]" LOC = E20;
NET "gn_p2l_data[12]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[13]" LOC = F22;
NET "gn_p2l_data[13]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[14]" LOC = F21;
NET "gn_p2l_data[14]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[15]" LOC = H19;
NET "gn_p2l_data[15]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req[0]" LOC = M22;
NET "gn_p_wr_req[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req[1]" LOC = M21;
NET "gn_p_wr_req[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy[0]" LOC = L15;
NET "gn_p_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy[1]" LOC = K16;
NET "gn_p_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error" LOC = J17;
NET "gn_rx_error" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clk_n" LOC = K22;
NET "gn_l2p_clk_n" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_clk_p" LOC = K21;
NET "gn_l2p_clk_p" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_dframe" LOC = U22;
NET "gn_l2p_dframe" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid" LOC = T18;
NET "gn_l2p_valid" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_edb" LOC = U20;
NET "gn_l2p_edb" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[0]" LOC = P16;
NET "gn_l2p_data[0]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[1]" LOC = P21;
NET "gn_l2p_data[1]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[2]" LOC = P18;
NET "gn_l2p_data[2]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[3]" LOC = T20;
NET "gn_l2p_data[3]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[4]" LOC = V21;
NET "gn_l2p_data[4]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[5]" LOC = V19;
NET "gn_l2p_data[5]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[6]" LOC = W22;
NET "gn_l2p_data[6]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[7]" LOC = Y22;
NET "gn_l2p_data[7]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[8]" LOC = P22;
NET "gn_l2p_data[8]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[9]" LOC = R22;
NET "gn_l2p_data[9]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[10]" LOC = T21;
NET "gn_l2p_data[10]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[11]" LOC = T19;
NET "gn_l2p_data[11]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[12]" LOC = V22;
NET "gn_l2p_data[12]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[13]" LOC = V20;
NET "gn_l2p_data[13]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[14]" LOC = W20;
NET "gn_l2p_data[14]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[15]" LOC = Y21;
NET "gn_l2p_data[15]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy" LOC = U19;
NET "gn_l2p_rdy" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy[0]" LOC = R20;
NET "gn_l_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy[1]" LOC = T22;
NET "gn_l_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy[0]" LOC = N16;
NET "gn_p_rd_d_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy[1]" LOC = P19;
NET "gn_p_rd_d_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error" LOC = M17;
NET "gn_tx_error" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy[0]" LOC = B21;
NET "gn_vc_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy[1]" LOC = B22;
NET "gn_vc_rdy[1]" IOSTANDARD = "SSTL18_I";
# GPIO 8 and 9 of the Genum
NET "GN_GPIO[0]" LOC = U16;
NET "GN_GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "GN_GPIO[1]" LOC = AB19;
NET "GN_GPIO[1]" IOSTANDARD = "LVCMOS25";
###########################################################################
## SPI interface to DACs
###########################################################################
NET "plldac_sclk_o" LOC = A4;
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" LOC = C4;
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "pll25dac_cs_n_o" LOC = A3;
NET "pll25dac_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_cs_n_o" LOC = B3;
NET "pll20dac_cs_n_o" IOSTANDARD = "LVCMOS25";
###########################################################################
## SFP I/O for transceiver
###########################################################################
#NET "sfp_txp_o" IOSTANDARD = "LVDS_12";
NET "sfp_txp_o" LOC= B16;
#NET "sfp_txn_o" IOSTANDARD = "LVDS_12";
NET "sfp_txn_o" LOC= A16;
#NET "sfp_rxp_i" IOSTANDARD = "LVDS_12";
NET "sfp_rxp_i" LOC= D15;
#NET "sfp_rxn_i" IOSTANDARD = "LVDS_12";
NET "sfp_rxn_i" LOC= C15;
NET "sfp_mod_def0_i" LOC = G15;
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" LOC = B18;
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_los_i" LOC = D18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
###########################################################################
## Onewire interface -> thermometer
###########################################################################
NET "onewire_b" LOC = D4;
NET "onewire_b" IOSTANDARD = "LVCMOS25";
###########################################################################
## UART
###########################################################################
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
###########################################################################
## Flash memory SPI interface
###########################################################################
NET "spi_ncs_o" LOC = AA3;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS25";
NET "spi_sclk_o" LOC = Y20;
NET "spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "spi_mosi_o" LOC = AB20;
NET "spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "spi_miso_i" LOC = AA20;
NET "spi_miso_i" IOSTANDARD = "LVCMOS25";
###########################################################################
## Miscellanous SPEC pins
###########################################################################
NET "led_act_o" LOC = D5;
NET "led_act_o" IOSTANDARD = "LVCMOS25";
NET "led_link_o" LOC = E5;
NET "led_link_o" IOSTANDARD = "LVCMOS25";
NET "button1_i" LOC = C22;
NET "button1_i" IOSTANDARD = "LVCMOS18";
#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[0]" LOC = P5;
NET "pcbrev_i[1]" LOC = P4;
NET "pcbrev_i[2]" LOC = AA2;
NET "pcbrev_i[3]" LOC = AA1;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_scl_b" LOC = F7;
NET "fmc0_sda_b" LOC = F8;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i*" TIG;
NET "fmc0_prsnt_m2c_n_i" TIG;
# GN4124
NET "gn_p2l_clk_p" TNM_NET = "gn_p2l_clkp_grp";
NET "gn_p2l_clk_n" TNM_NET = "gn_p2l_clkn_grp";
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "inst_template/cmp_gn4124_core/cmp_wrapped_gn4124/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "gn_rst_n" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "inst_template/cmp_gn4124_core/cmp_wrapped_gn4124/cmp_clk_in/P_clk" TNM_NET = inst_template/cmp_gn4124_core/cmp_wrapped_gn4124/cmp_clk_in/P_clk;
#NET "inst_template/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = inst_template/cmp_gn4124_core/cmp_clk_in/P_clk;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
# Needed only when DMTD samples 125m refclock (clock has to be fed to D input of
# a flip-flop).
# However, in case of SPEC we use g_divide_input_by_2 generic in the dmtd_with_deglitcher.
# This re-generates 62.5MHz clock from 125Mhz and we don't feed 125M clock directly to D
# input of a flip-flop. This constraint would be needed e.g. for Kintex, where
# refclock is 62.5MHz and we don't use g_divide_input_by_2.
#PIN "WRC_PLATFORM/cmp_pllrefclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/02/20
NET "inst_template/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = inst_template/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "inst_template/cmp_xwrc_board_spec/gen_wr.cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# Force PPS output to always be placed as IOB register
# INST "inst_template/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = FORCE;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/hdl/top/golden_wr/spec_golden_wr.vhd 0000664 0000000 0000000 00000023663 13533225622 0026072 0 ustar 00root root 0000000 0000000 --------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_golden_wr
--
-- description: SPEC golden design, with WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_golden_wr is
generic (
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe : in std_logic; -- Receive Frame
gn_p2l_valid : in std_logic; -- Receive Data Valid
gn_p2l_data : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe : out std_logic; -- Transmit Data Frame
gn_l2p_valid : out std_logic; -- Transmit Data Valid
gn_l2p_edb : out std_logic; -- Packet termination and discard
gn_l2p_data : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error : in std_logic; -- Transmit Error
gn_vc_rdy : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Miscellanous SPEC pins
---------------------------------------------------------------------------
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic
);
end entity spec_golden_wr;
architecture top of spec_golden_wr is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_template: entity work.spec_template_wr
generic map (
g_WITH_VIC => True,
g_WITH_ONEWIRE => False,
g_WITH_SPI => False,
g_WITH_DDR => False,
g_WITH_WR => True,
g_dpram_initf => g_dpram_initf,
g_simulation => g_simulation
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n,
gn_p2l_clk_n_i => gn_p2l_clk_n,
gn_p2l_clk_p_i => gn_p2l_clk_p,
gn_p2l_rdy_o => gn_p2l_rdy,
gn_p2l_dframe_i => gn_p2l_dframe,
gn_p2l_valid_i => gn_p2l_valid,
gn_p2l_data_i => gn_p2l_data,
gn_p_wr_req_i => gn_p_wr_req,
gn_p_wr_rdy_o => gn_p_wr_rdy,
gn_rx_error_o => gn_rx_error,
gn_l2p_clk_n_o => gn_l2p_clk_n,
gn_l2p_clk_p_o => gn_l2p_clk_p,
gn_l2p_dframe_o => gn_l2p_dframe,
gn_l2p_valid_o => gn_l2p_valid,
gn_l2p_edb_o => gn_l2p_edb,
gn_l2p_data_o => gn_l2p_data,
gn_l2p_rdy_i => gn_l2p_rdy,
gn_l_wr_rdy_i => gn_l_wr_rdy,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy,
gn_tx_error_i => gn_tx_error,
gn_vc_rdy_i => gn_vc_rdy,
gn_gpio_b => gn_gpio,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_i => button1_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_i.cyc => '0',
ddr_dma_wb_i.stb => '0',
ddr_dma_wb_i.adr => x"0000_0000",
ddr_dma_wb_i.sel => x"00",
ddr_dma_wb_i.we => '0',
ddr_dma_wb_i.dat => x"0000_0000_0000_0000",
ddr_dma_wb_o => open,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end architecture top;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/ 0000775 0000000 0000000 00000000000 13533225622 0020664 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/Makefile 0000664 0000000 0000000 00000001155 13533225622 0022326 0 ustar 00root root 0000000 0000000 -include Makefile.specific
# include parent_common.mk for buildsystem's defines
#use absolute path for REPO_PARENT
REPO_PARENT ?= $(shell /bin/pwd)/..
-include $(REPO_PARENT)/parent_common.mk
DIRS = kernel
.PHONY: all clean modules install modules_install $(DIRS)
all clean modules install modules_install: $(DIRS)
clean: TARGET = clean
modules: TARGET = modules
install: TARGET = install
modules_install: TARGET = modules_install
ENV_VAR := CONFIG_FPGA_MGR_BACKPORT_PATH=$(CONFIG_FPGA_MGR_BACKPORT_PATH)
ENV_VAR += CONFIG_FPGA_MGR_BACKPORT=$(CONFIG_FPGA_MGR_BACKPORT)
$(DIRS):
$(MAKE) -C $@ $(ENV_VAR) $(TARGET)
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/ 0000775 0000000 0000000 00000000000 13533225622 0022144 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/.gitignore 0000664 0000000 0000000 00000000020 13533225622 0024124 0 ustar 00root root 0000000 0000000 spec-core-fpga.h spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/Kbuild 0000664 0000000 0000000 00000002711 13533225622 0023302 0 ustar 00root root 0000000 0000000 # add versions of supermodule. It is useful when spec is included as sub-module
# of a bigger project that we want to track
ifdef CONFIG_SUPER_REPO
ifdef CONFIG_SUPER_REPO_VERSION
SUBMODULE_VERSIONS += MODULE_INFO(version_$(CONFIG_SUPER_REPO),\"$(CONFIG_SUPER_REPO_VERSION)\");
endif
endif
# add versions of used submodules
CONFIG_FPGA_MGR_BACKPORT_INCLUDE := -I$(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS)/include
CONFIG_FPGA_MGR_BACKPORT_INCLUDE += -I$(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS)/include/linux
ccflags-y += -DADDITIONAL_VERSIONS="$(SUBMODULE_VERSIONS)"
ccflags-y += -DVERSION=\"$(VERSION)\"
ccflags-y += -Wall -Werror
ccflags-$(CONFIG_FPGA_MGR_BACKPORT) += -DCONFIG_FPGA_MGR_BACKPORT
ccflags-$(CONFIG_FPGA_MGR_BACKPORT) += $(CONFIG_FPGA_MGR_BACKPORT_INCLUDE)
ccflags-y += -I$(FMC_ABS)/include
# priority to I2C, FMC headers from our sources
LINUXINCLUDE := -I$(FMC_ABS)/include -I$(FMC_ABS)/include/linux -I$(I2C_ABS)/include -I$(I2C_ABS)/include/linux $(LINUXINCLUDE)
ifeq ($(CONFIG_FPGA_MGR_BACKPORT), y)
LINUXINCLUDE := $(CONFIG_FPGA_MGR_BACKPORT_INCLUDE) $(LINUXINCLUDE)
KBUILD_EXTRA_SYMBOLS += $(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS)/drivers/fpga/Module.symvers
endif
KBUILD_EXTRA_SYMBOLS += $(FMC_ABS)/drivers/fmc/Module.symvers
obj-m := spec-fmc-carrier.o
obj-m += gn412x-gpio.o
obj-m += gn412x-fcl.o
obj-m += spec-gn412x-dma.o
obj-m += spi-ocores.o
spec-fmc-carrier-objs := spec-core.o
spec-fmc-carrier-objs += spec-core-fpga.o
spec-fmc-carrier-objs += spec-compat.o
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/Makefile 0000664 0000000 0000000 00000002261 13533225622 0023605 0 ustar 00root root 0000000 0000000 -include Makefile.specific
# include parent_common.mk for buildsystem's defines
#use absolute path for REPO_PARENT
REPO_PARENT ?= $(shell /bin/pwd)/../..
-include $(REPO_PARENT)/parent_common.mk
KVERSION ?= $(shell uname -r)
LINUX ?= /lib/modules/$(KVERSION)/build
TOP_DIR ?= $(shell pwd)/../..
HDL_DIR ?= $(TOP_DIR)/hdl
CONFIG_FPGA_MGR_BACKPORT_PATH_ABS ?= $(abspath $(CONFIG_FPGA_MGR_BACKPORT_PATH))
FMC_ABS ?= $(abspath $(FMC))
I2C_ABS ?= $(abspath $(I2C))
VERSION = $(shell git describe --dirty --long --tags)
CHEBY ?= /usr/bin/cheby
all: modules
.PHONY: all modules clean help install modules_install spec-core-fpga.h
spec-core-fpga.h:
$(CHEBY) --gen-c -i $(HDL_DIR)/rtl/spec_template_regs.cheby > $@
modules help install modules_install: spec-core-fpga.h
$(MAKE) -C $(LINUX) M=$(shell pwd) VERSION=$(VERSION) CONFIG_FPGA_MGR_BACKPORT_PATH_ABS=$(CONFIG_FPGA_MGR_BACKPORT_PATH_ABS) CONFIG_FPGA_MGR_BACKPORT=$(CONFIG_FPGA_MGR_BACKPORT) FMC_ABS=$(FMC_ABS) I2C_ABS=$(I2C_ABS) $@
# be able to run the "clean" rule even if $(LINUX) is not valid
clean:
rm -rf *.o *~ .*.cmd *.ko *.mod.c .tmp_versions Module.symvers \
Module.markers modules.order spec-core-fpga.h
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/gn412x-fcl.c 0000664 0000000 0000000 00000033720 13533225622 0024102 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#include
#include
#include
#include
#include "spec.h"
#include "spec-compat.h"
#include "gn412x.h"
#define FCL_CTRL_START_FSM BIT(0)
#define FCL_CTRL_SPRI_EN BIT(1)
#define FCL_CTRL_FSM_EN BIT(2)
#define FCL_CTRL_SEND_CFG_DATA BIT(3)
#define FCL_CTRL_LAST_BYTE_CNT_1 (0x3 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_2 (0x2 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_3 (0x1 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_4 (0x0 << 4)
#define FCL_CTRL_RESET BIT(6)
#define FCL_CTRL_DATA_PUSH_COMP BIT(7)
#define FCL_CTRL_SPRI_CLK_STOP_EN BIT(8)
#define FCL_SPRI_CLKOUT BIT(0)
#define FCL_SPRI_DATAOUT BIT(1)
#define FCL_SPRI_CONFIG BIT(2)
#define FCL_SPRI_DONE BIT(3)
#define FCL_SPRI_XI_SWAP BIT(4)
#define FCL_SPRI_STATUS BIT(5)
#define FCL_IRQ_SPRI_STATUS BIT(0)
#define FCL_IRQ_TIMER BIT(1)
#define FCL_IRQ_CONFIG_ERROR BIT(2)
#define FCL_IRQ_CONFIG_DONE BIT(3)
#define FCL_IRQ_FIFO_UNDRFL BIT(4)
#define FCL_IRQ_FIFO_HALFFULL BIT(5)
/* Compatibility layer */
static int gn412x_fcl_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count);
static int gn412x_fcl_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info);
static int compat_get_fpga_last_word_size(struct fpga_image_info *info,
size_t count)
{
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
return count;
#else
return info ? info->count : count;
#endif
}
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
static int compat_gn412x_fcl_write_init(struct fpga_manager *mgr,
u32 flags,
const char *buf, size_t count)
{
return gn412x_fcl_write_init(mgr, NULL, buf, count);
}
static int compat_gn412x_fcl_write_complete(struct fpga_manager *mgr,
u32 flags)
{
return gn412x_fcl_write_complete(mgr, NULL);
}
#else
static int compat_gn412x_fcl_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count)
{
return gn412x_fcl_write_init(mgr, info, buf, count);
}
static int compat_gn412x_fcl_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info)
{
return gn412x_fcl_write_complete(mgr, info);
}
#endif
#if KERNEL_VERSION(4, 18, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
static struct fpga_manager *compat_fpga_mgr_create(struct device *dev,
const char *name,
const struct fpga_manager_ops *mops,
void *priv)
{
int err;
err = fpga_mgr_register(dev, name, mops, priv);
if (err)
return NULL;
return (struct fpga_manager *)dev;
}
static void compat_fpga_mgr_free(struct fpga_manager *mgr)
{
fpga_mgr_unregister((struct device *)mgr);
}
static int compat_fpga_mgr_register(struct fpga_manager *mgr)
{
return mgr ? 0 : 1;
}
static void compat_fpga_mgr_unregister(struct fpga_manager *mgr)
{
return mgr ? 0 : 1;
}
#else
static struct fpga_manager *compat_fpga_mgr_create(struct device *dev,
const char *name,
const struct fpga_manager_ops *mops,
void *priv)
{
return fpga_mgr_create(dev, name, mops, priv);
}
static void compat_fpga_mgr_free(struct fpga_manager *mgr)
{
fpga_mgr_free(mgr);
}
static int compat_fpga_mgr_register(struct fpga_manager *mgr)
{
return fpga_mgr_register(mgr);
}
static void compat_fpga_mgr_unregister(struct fpga_manager *mgr)
{
fpga_mgr_unregister(mgr);
}
#endif
/* The real code */
/**
* struct gn412x_dev GN412X device descriptor
* @compl: for IRQ testing
* @int_cfg_gpio: INT_CFG used for GPIO interrupts
*/
struct gn412x_fcl_dev {
void __iomem *mem;
struct fpga_manager *mgr;
struct dentry *dbg_dir;
#define GN412X_DBG_REG_NAME "regs"
struct dentry *dbg_reg;
struct debugfs_regset32 dbg_reg32;
};
#define REG32(_name, _offset) {.name = _name, .offset = _offset}
static const struct debugfs_reg32 gn412x_debugfs_reg32[] = {
REG32("FCL_CTRL", FCL_CTRL),
REG32("FCL_STATUS", FCL_STATUS),
REG32("FCL_IODATA_IN", FCL_IODATA_IN),
REG32("FCL_IODATA_OUT", FCL_IODATA_OUT),
REG32("FCL_EN", FCL_EN),
REG32("FCL_TIMER0", FCL_TIMER_0),
REG32("FCL_TIMER1", FCL_TIMER_1),
REG32("FCL_CLK_DIV", FCL_CLK_DIV),
REG32("FCL_IRQ", FCL_IRQ),
REG32("FCL_TIMER_CTRL", FCL_TIMER_CTRL),
REG32("FCL_IM", FCL_IM),
REG32("FCL_TIMER2_0", FCL_TIMER2_0),
REG32("FCL_TIMER2_1", FCL_TIMER2_1),
REG32("FCL_DBG_STS", FCL_DBG_STS),
};
static int gn4124_dbg_init(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x = platform_get_drvdata(pdev);
struct dentry *dir, *file;
int err;
dir = debugfs_create_dir(dev_name(&pdev->dev), NULL);
if (IS_ERR_OR_NULL(dir)) {
err = PTR_ERR(dir);
dev_warn(&pdev->dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(&pdev->dev), err);
goto err_dir;
}
gn412x->dbg_reg32.regs = gn412x_debugfs_reg32;
gn412x->dbg_reg32.nregs = ARRAY_SIZE(gn412x_debugfs_reg32);
gn412x->dbg_reg32.base = gn412x->mem;
file = debugfs_create_regset32(GN412X_DBG_REG_NAME, 0200,
dir, &gn412x->dbg_reg32);
if (IS_ERR_OR_NULL(file)) {
err = PTR_ERR(file);
dev_warn(&pdev->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
GN412X_DBG_REG_NAME, err);
goto err_reg32;
}
gn412x->dbg_dir = dir;
gn412x->dbg_reg = file;
return 0;
err_reg32:
debugfs_remove_recursive(dir);
err_dir:
return err;
}
static void gn4124_dbg_exit(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x = platform_get_drvdata(pdev);
debugfs_remove_recursive(gn412x->dbg_dir);
}
static uint32_t gn412x_ioread32(struct gn412x_fcl_dev *gn412x,
int reg)
{
return ioread32(gn412x->mem + reg);
}
static void gn412x_iowrite32(struct gn412x_fcl_dev *gn412x,
uint32_t val, int reg)
{
return iowrite32(val, gn412x->mem + reg);
}
static inline uint8_t reverse_bits8(uint8_t x)
{
x = ((x >> 1) & 0x55) | ((x & 0x55) << 1);
x = ((x >> 2) & 0x33) | ((x & 0x33) << 2);
x = ((x >> 4) & 0x0f) | ((x & 0x0f) << 4);
return x;
}
static uint32_t unaligned_bitswap_le32(const uint32_t *ptr32)
{
static uint32_t tmp32;
static uint8_t *tmp8 = (uint8_t *) &tmp32;
static uint8_t *ptr8;
ptr8 = (uint8_t *) ptr32;
*(tmp8 + 0) = reverse_bits8(*(ptr8 + 0));
*(tmp8 + 1) = reverse_bits8(*(ptr8 + 1));
*(tmp8 + 2) = reverse_bits8(*(ptr8 + 2));
*(tmp8 + 3) = reverse_bits8(*(ptr8 + 3));
return tmp32;
}
/**
* it resets the FPGA
*/
static void gn4124_fpga_reset(struct gn412x_fcl_dev *gn412x)
{
uint32_t reg;
/* After reprogramming, reset the FPGA using the gennum register */
reg = gn412x_ioread32(gn412x, GNPCI_SYS_CFG_SYSTEM);
/*
* This _fucking_ register must be written with extreme care,
* becase some fields are "protected" and some are not. *hate*
*/
gn412x_iowrite32(gn412x, (reg & ~0xffff) | 0x3fff,
GNPCI_SYS_CFG_SYSTEM);
gn412x_iowrite32(gn412x, (reg & ~0xffff) | 0x7fff,
GNPCI_SYS_CFG_SYSTEM);
}
/**
* Initialize the gennum
* @gn412x: gn412x device instance
* @last_word_size: last word size in the FPGA bitstream
*
* Return: 0 on success, otherwise a negative error code
*/
static int gn4124_fpga_fcl_init(struct gn412x_fcl_dev *gn412x,
int last_word_size)
{
uint32_t ctrl, en;
int i;
gn412x_iowrite32(gn412x, 0x00, FCL_CLK_DIV);
gn412x_iowrite32(gn412x, FCL_CTRL_RESET, FCL_CTRL);
i = gn412x_ioread32(gn412x, FCL_CTRL);
if (i != FCL_CTRL_RESET) {
pr_err("%s: %i: error\n", __func__, __LINE__);
return -EIO;
}
gn412x_iowrite32(gn412x, 0x00, FCL_CTRL);
gn412x_iowrite32(gn412x, 0x00, FCL_IRQ); /* clear pending irq */
ctrl = 0;
ctrl |= FCL_CTRL_SPRI_EN;
ctrl |= FCL_CTRL_FSM_EN;
ctrl |= FCL_CTRL_SPRI_CLK_STOP_EN;
switch (last_word_size) {
case 3:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_3;
break;
case 2:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_2;
break;
case 1:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_1;
break;
case 0:
ctrl |= FCL_CTRL_LAST_BYTE_CNT_4;
break;
default: return -EINVAL;
}
gn412x_iowrite32(gn412x, ctrl, FCL_CTRL);
gn412x_iowrite32(gn412x, 0x00, FCL_CLK_DIV);
gn412x_iowrite32(gn412x, 0x00, FCL_TIMER_CTRL);
gn412x_iowrite32(gn412x, 0x10, FCL_TIMER_0);
gn412x_iowrite32(gn412x, 0x00, FCL_TIMER_1);
/*
* Set delay before data and clock is applied by FCL
* after SPRI_STATUS is detected being assert.
*/
gn412x_iowrite32(gn412x, 0x08, FCL_TIMER2_0);
gn412x_iowrite32(gn412x, 0x00, FCL_TIMER2_1);
en = 0;
en |= FCL_SPRI_CLKOUT;
en |= FCL_SPRI_DATAOUT;
en |= FCL_SPRI_CONFIG;
en |= FCL_SPRI_XI_SWAP;
gn412x_iowrite32(gn412x, en, FCL_EN);
ctrl |= FCL_CTRL_START_FSM;
gn412x_iowrite32(gn412x, ctrl, FCL_CTRL);
return 0;
}
/**
* Wait for the FPGA to be configured and ready
* @gn412x: device instance
*
* Return: 0 on success,-ETIMEDOUT on failure
*/
static int gn4124_fpga_fcl_waitdone(struct gn412x_fcl_dev *gn412x)
{
unsigned long j;
j = jiffies + 2 * HZ;
while (1) {
uint32_t val = gn412x_ioread32(gn412x, FCL_IRQ);
/* Done */
if (val & 0x8)
return 0;
/* Fail */
if (val & 0x4)
return -EIO;
/* Timeout */
if (time_after(jiffies, j))
return -ETIMEDOUT;
udelay(100);
}
}
/**
* It configures the FPGA with the given image
* @gn412x: gn412x instance
* @data: FPGA configuration code
* @len: image length in bytes
*
* Return: 0 on success, otherwise a negative error code
*/
static int gn4124_fpga_load(struct gn412x_fcl_dev *gn412x,
const void *data, int len)
{
int size32 = (len + 3) >> 2;
int done = 0, wrote = 0;
const uint32_t *data32 = data;
while (size32 > 0) {
/* Check to see if FPGA configuation has error */
int i = gn412x_ioread32(gn412x, FCL_IRQ);
if ((i & FCL_IRQ_CONFIG_DONE) && wrote) {
done = 1;
pr_err("%s: %i: done after %i%i\n",
__func__, __LINE__,
wrote, ((len + 3) >> 2));
} else if ((i & FCL_IRQ_CONFIG_ERROR) && !done) {
pr_err("%s: %i: error after %i/%i\n",
__func__, __LINE__,
wrote, ((len + 3) >> 2));
return -EIO;
}
/* Wait until at least 1/2 of the fifo is empty */
while (gn412x_ioread32(gn412x, FCL_IRQ) & FCL_IRQ_FIFO_HALFFULL)
;
/* Write a few dwords into FIFO at a time. */
for (i = 0; size32 && i < 32; i++) {
gn412x_iowrite32(gn412x, unaligned_bitswap_le32(data32),
FCL_FIFO);
data32++; size32--; wrote++;
}
}
return 0;
}
/**
* It notifies the gennum that the configuration is over
* @gn412x: gn412x device instance
*/
static void gn4124_fpga_fcl_complete(struct gn412x_fcl_dev *gn412x)
{
uint32_t ctrl = 0;
ctrl |= FCL_CTRL_SPRI_EN;
ctrl |= FCL_CTRL_FSM_EN;
ctrl |= FCL_CTRL_DATA_PUSH_COMP;
ctrl |= FCL_CTRL_SPRI_CLK_STOP_EN;
gn412x_iowrite32(gn412x, ctrl, FCL_CTRL);
}
static enum fpga_mgr_states gn412x_fcl_state(struct fpga_manager *mgr)
{
return mgr->state;
}
static int gn412x_fcl_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count)
{
struct gn412x_fcl_dev *gn412x = mgr->priv;
int err = 0, last_word_size;
last_word_size = compat_get_fpga_last_word_size(info, count) & 0x3;
err = gn4124_fpga_fcl_init(gn412x, last_word_size);
if (err < 0)
goto err;
return 0;
err:
return err;
}
static int gn412x_fcl_write(struct fpga_manager *mgr,
const char *buf, size_t count)
{
struct gn412x_fcl_dev *gn412x = mgr->priv;
return gn4124_fpga_load(gn412x, buf, count);
}
static void gn4124_fcl_reset(struct gn412x_fcl_dev *gn412x)
{
gn412x_iowrite32(gn412x, 0x00, FCL_CTRL);
gn412x_iowrite32(gn412x, 0x00, FCL_EN);
}
static int gn412x_fcl_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info)
{
struct gn412x_fcl_dev *gn412x = mgr->priv;
int err;
gn4124_fpga_fcl_complete(gn412x);
err = gn4124_fpga_fcl_waitdone(gn412x);
if (err < 0)
return err;
gn4124_fcl_reset(gn412x);
gn4124_fpga_reset(gn412x);
return 0;
}
static void gn412x_fcl_fpga_remove(struct fpga_manager *mgr)
{
/* do nothing */
}
static const struct fpga_manager_ops gn412x_fcl_ops = {
compat_fpga_ops_initial_header_size
compat_fpga_ops_groups
.state = gn412x_fcl_state,
.write_init = compat_gn412x_fcl_write_init,
.write = gn412x_fcl_write,
.write_complete = compat_gn412x_fcl_write_complete,
.fpga_remove = gn412x_fcl_fpga_remove,
};
static int gn412x_fcl_probe(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x;
struct resource *r;
int err;
gn412x = devm_kzalloc(&pdev->dev, sizeof(*gn412x), GFP_KERNEL);
if (!gn412x)
return -ENOMEM;
platform_set_drvdata(pdev, gn412x);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(&pdev->dev, "Missing memory resource\n");
err = -EINVAL;
goto err_res_mem;
}
gn412x->mem = devm_ioremap(&pdev->dev, r->start, resource_size(r));
if (!gn412x->mem) {
err = -EADDRNOTAVAIL;
goto err_map;
}
gn4124_fcl_reset(gn412x);
gn4124_dbg_init(pdev);
gn412x->mgr = compat_fpga_mgr_create(&pdev->dev,
dev_name(&pdev->dev),
&gn412x_fcl_ops, gn412x);
if (!gn412x->mgr) {
err = -EPERM;
goto err_fpga_create;
}
err = compat_fpga_mgr_register(gn412x->mgr);
if (err)
goto err_fpga_reg;
return 0;
err_fpga_reg:
compat_fpga_mgr_free(gn412x->mgr);
err_fpga_create:
gn4124_dbg_exit(pdev);
devm_iounmap(&pdev->dev, gn412x->mem);
err_map:
err_res_mem:
devm_kfree(&pdev->dev, gn412x);
return err;
}
static int gn412x_fcl_remove(struct platform_device *pdev)
{
struct gn412x_fcl_dev *gn412x = platform_get_drvdata(pdev);
gn4124_dbg_exit(pdev);
if (!gn412x->mgr)
return -ENODEV;
compat_fpga_mgr_unregister(gn412x->mgr);
compat_fpga_mgr_free(gn412x->mgr);
dev_dbg(&pdev->dev, "%s\n", __func__);
return 0;
}
static const struct platform_device_id gn412x_fcl_id[] = {
{
.name = "gn412x-fcl",
},
{ .name = "" }, /* last */
};
static struct platform_driver gn412x_fcl_platform_driver = {
.driver = {
.name = KBUILD_MODNAME,
},
.probe = gn412x_fcl_probe,
.remove = gn412x_fcl_remove,
.id_table = gn412x_fcl_id,
};
module_platform_driver(gn412x_fcl_platform_driver);
MODULE_AUTHOR("Federico Vaga ");
MODULE_DESCRIPTION("GN412X FCL driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(VERSION);
MODULE_DEVICE_TABLE(platform, gn412x_fcl_id);
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/gn412x-gpio.c 0000664 0000000 0000000 00000037445 13533225622 0024304 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#include
#include
#include
#include "spec.h"
#include "gn412x.h"
#include "platform_data/gn412x-gpio.h"
/**
* struct gn412x_gpio_dev GN412X device descriptor
* @compl: for IRQ testing
* @int_cfg_gpio: INT_CFG used for GPIO interrupts
*/
struct gn412x_gpio_dev {
void __iomem *mem;
struct gpio_chip gpiochip;
struct completion compl;
struct gn412x_platform_data *pdata;
struct dentry *dbg_dir;
#define GN412X_DBG_REG_NAME "regs"
struct dentry *dbg_reg;
struct debugfs_regset32 dbg_reg32;
};
static struct gn412x_platform_data gn412x_gpio_pdata_default = {
.int_cfg = 0,
};
static inline struct gn412x_gpio_dev *to_gn412x_gpio_dev_gpio(struct gpio_chip *chip)
{
return container_of(chip, struct gn412x_gpio_dev, gpiochip);
}
enum gn412x_gpio_versions {
GN412X_VER = 0,
};
enum htvic_mem_resources {
GN412X_MEM_BASE = 0,
};
#define REG32(_name, _offset) {.name = _name, .offset = _offset}
static const struct debugfs_reg32 gn412x_debugfs_reg32[] = {
REG32("INT_CTRL", GNINT_CTRL),
REG32("INT_STAT", GNINT_STAT),
REG32("INT_CFG0", GNINT_CFG_0),
REG32("INT_CFG1", GNINT_CFG_1),
REG32("INT_CFG2", GNINT_CFG_2),
REG32("INT_CFG3", GNINT_CFG_3),
REG32("INT_CFG4", GNINT_CFG_4),
REG32("INT_CFG5", GNINT_CFG_5),
REG32("INT_CFG6", GNINT_CFG_6),
REG32("INT_CFG7", GNINT_CFG_7),
REG32("GPIO_BYPASS_MODE", GNGPIO_BYPASS_MODE),
REG32("GPIO_DIRECTION_MODE", GNGPIO_DIRECTION_MODE),
REG32("GPIO_OUTPUT_ENABLE", GNGPIO_OUTPUT_ENABLE),
REG32("GPIO_OUTPUT_VALUE", GNGPIO_OUTPUT_VALUE),
REG32("GPIO_INPUT_VALUE", GNGPIO_INPUT_VALUE),
REG32("GPIO_INT_MASK", GNGPIO_INT_MASK),
REG32("GPIO_INT_MASK_CLR", GNGPIO_INT_MASK_CLR),
REG32("GPIO_INT_MASK_SET", GNGPIO_INT_MASK_SET),
REG32("GPIO_INT_STATUS", GNGPIO_INT_STATUS),
REG32("GPIO_INT_TYPE", GNGPIO_INT_TYPE),
REG32("GPIO_INT_VALUE", GNGPIO_INT_VALUE),
REG32("GPIO_INT_ON_ANY", GNGPIO_INT_ON_ANY),
};
static int gn412x_dbg_init(struct gn412x_gpio_dev *gn412x)
{
struct dentry *dir, *file;
int err;
dir = debugfs_create_dir(dev_name(gn412x->gpiochip.dev), NULL);
if (IS_ERR_OR_NULL(dir)) {
err = PTR_ERR(dir);
dev_warn(gn412x->gpiochip.dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(gn412x->gpiochip.dev), err);
goto err_dir;
}
gn412x->dbg_reg32.regs = gn412x_debugfs_reg32;
gn412x->dbg_reg32.nregs = ARRAY_SIZE(gn412x_debugfs_reg32);
gn412x->dbg_reg32.base = gn412x->mem;
file = debugfs_create_regset32(GN412X_DBG_REG_NAME, 0200,
dir, &gn412x->dbg_reg32);
if (IS_ERR_OR_NULL(file)) {
err = PTR_ERR(file);
dev_warn(gn412x->gpiochip.dev,
"Cannot create debugfs file \"%s\" (%d)\n",
GN412X_DBG_REG_NAME, err);
goto err_reg32;
}
gn412x->dbg_dir = dir;
gn412x->dbg_reg = file;
return 0;
err_reg32:
debugfs_remove_recursive(dir);
err_dir:
return err;
}
static void gn412x_dbg_exit(struct gn412x_gpio_dev *gn412x)
{
debugfs_remove_recursive(gn412x->dbg_dir);
}
static uint32_t gn412x_ioread32(struct gn412x_gpio_dev *gn412x,
int reg)
{
return ioread32(gn412x->mem + reg);
}
static void gn412x_iowrite32(struct gn412x_gpio_dev *gn412x,
uint32_t val, int reg)
{
return iowrite32(val, gn412x->mem + reg);
}
static int gn412x_gpio_reg_read(struct gpio_chip *chip,
int reg, unsigned int offset)
{
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(chip);
return gn412x_ioread32(gn412x, reg) & BIT(offset);
}
static void gn412x_gpio_reg_write(struct gpio_chip *chip,
int reg, unsigned int offset, int value)
{
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(chip);
uint32_t regval;
regval = gn412x_ioread32(gn412x, reg);
if (value)
regval |= BIT(offset);
else
regval &= ~BIT(offset);
gn412x_iowrite32(gn412x, regval, reg);
}
/**
* Enable GPIO interrupts
* @gn412x gn412x device
*
* Return: 0 on success, otherwise a negative error number
*/
static void gn412x_gpio_int_cfg_enable(struct gn412x_gpio_dev *gn412x)
{
uint32_t int_cfg;
int_cfg = gn412x_ioread32(gn412x, GNINT_CFG(gn412x->pdata->int_cfg));
int_cfg |= GNINT_STAT_GPIO;
gn412x_iowrite32(gn412x, int_cfg, GNINT_CFG(gn412x->pdata->int_cfg));
}
/**
* Disable GPIO interrupts from a single configuration space
* @gn412x gn412x device
*
* Return: 0 on success, otherwise a negative error number
*/
static void gn412x_gpio_int_cfg_disable(struct gn412x_gpio_dev *gn412x)
{
uint32_t int_cfg;
int_cfg = gn412x_ioread32(gn412x, GNINT_CFG(gn412x->pdata->int_cfg));
int_cfg &= ~GNINT_STAT_GPIO;
gn412x_iowrite32(gn412x, int_cfg, GNINT_CFG(gn412x->pdata->int_cfg));
}
static int gn412x_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
int val;
val = gn412x_gpio_reg_read(chip, GNGPIO_BYPASS_MODE, offset);
if (val) {
dev_err(chip->dev, "%s GPIO %d is in BYPASS mode\n",
chip->label, offset);
return -EBUSY;
}
return 0;
}
static void gn412x_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
/* set it as input to avoid to drive anything */
gn412x_gpio_reg_write(chip, GNGPIO_DIRECTION_MODE, offset, 1);
}
static int gn412x_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
return !gn412x_gpio_reg_read(chip, GNGPIO_DIRECTION_MODE, offset);
}
static int gn412x_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
gn412x_gpio_reg_write(chip, GNGPIO_DIRECTION_MODE, offset, 1);
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_ENABLE, offset, 0);
return 0;
}
static int gn412x_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
gn412x_gpio_reg_write(chip, GNGPIO_DIRECTION_MODE, offset, 0);
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_ENABLE, offset, 1);
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_VALUE, offset, value);
return 0;
}
static int gn412x_gpio_get(struct gpio_chip *chip,
unsigned int offset)
{
return gn412x_gpio_reg_read(chip, GNGPIO_INPUT_VALUE, offset);
}
static void gn412x_gpio_set(struct gpio_chip *chip,
unsigned int offset, int value)
{
gn412x_gpio_reg_write(chip, GNGPIO_OUTPUT_VALUE, offset, value);
}
/**
* (disable)
*/
static void gn412x_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(gc);
gn412x_iowrite32(gn412x, BIT(d->hwirq), GNGPIO_INT_MASK_SET);
}
/**
* (enable)
*/
static void gn412x_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct gn412x_gpio_dev *gn412x = to_gn412x_gpio_dev_gpio(gc);
gn412x_iowrite32(gn412x, BIT(d->hwirq), GNGPIO_INT_MASK_CLR);
}
static int gn412x_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
/*
* detect errors:
* - level and edge together cannot work
*/
if ((flow_type & IRQ_TYPE_LEVEL_MASK) &&
(flow_type & IRQ_TYPE_EDGE_BOTH)) {
dev_err(gc->dev,
"Impossible to set GPIO IRQ %ld to both LEVEL and EDGE (0x%x)\n",
d->hwirq, flow_type);
return -EINVAL;
}
/* Configure: level or edge (default)? */
if (flow_type & IRQ_TYPE_LEVEL_MASK) {
gn412x_gpio_reg_write(gc, GNGPIO_INT_TYPE, d->hwirq, 1);
} else {
gn412x_gpio_reg_write(gc, GNGPIO_INT_TYPE, d->hwirq, 0);
/* if we want to trigger on any edge */
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
gn412x_gpio_reg_write(gc, GNGPIO_INT_ON_ANY,
d->hwirq, 1);
}
/* Configure: level-low or falling-edge, level-high or raising-edge */
if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
gn412x_gpio_reg_write(gc, GNGPIO_INT_VALUE, d->hwirq, 0);
else
gn412x_gpio_reg_write(gc, GNGPIO_INT_VALUE, d->hwirq, 1);
return IRQ_SET_MASK_OK;
}
/**
* A new IRQ interrupt has been requested
* @d IRQ related data
*
* We need to set the GPIO line to be input and disable completely any
* kind of output. We do not want any alternative function (bypass mode).
*/
static unsigned int gn412x_gpio_irq_startup(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
gn412x_gpio_reg_write(gc, GNGPIO_BYPASS_MODE, d->hwirq, 0);
gn412x_gpio_reg_write(gc, GNGPIO_DIRECTION_MODE, d->hwirq, 1);
gn412x_gpio_reg_write(gc, GNGPIO_OUTPUT_ENABLE, d->hwirq, 0);
gn412x_gpio_direction_input(gc, d->hwirq);
/* FIXME in the original code we had this? What is it? */
/* !!(gennum_readl(spec, GNGPIO_INPUT_VALUE) & bit); */
gn412x_gpio_irq_unmask(d);
return 0;
}
/**
* It disables the GPIO interrupt by masking it
*/
static void gn412x_gpio_irq_disable(struct irq_data *d)
{
gn412x_gpio_irq_mask(d);
}
static void gn412x_gpio_irq_ack(struct irq_data *d)
{
/*
* based on HW design,there is no need to ack HW
* before handle current irq. But this routine is
* necessary for handle_edge_irq
*/
}
static struct irq_chip gn412x_gpio_irq_chip = {
.name = "GN412X-GPIO",
.irq_startup = gn412x_gpio_irq_startup,
.irq_disable = gn412x_gpio_irq_disable,
.irq_mask = gn412x_gpio_irq_mask,
.irq_unmask = gn412x_gpio_irq_unmask,
.irq_set_type = gn412x_gpio_irq_set_type,
.irq_ack = gn412x_gpio_irq_ack,
};
/**
* This will run in hard-IRQ context since we do not have much to do
*/
static irqreturn_t spec_irq_sw_handler(int irq, void *arg)
{
struct gn412x_gpio_dev *gn412x = arg;
/* Ack the interrupts */
gn412x_ioread32(gn412x, GNINT_STAT);
gn412x_iowrite32(gn412x, 0x0000, GNINT_STAT);
complete(&gn412x->compl);
return IRQ_HANDLED;
}
/**
* Handle IRQ from the GPIO block
*/
static irqreturn_t gn412x_gpio_irq_handler_t(int irq, void *arg)
{
struct gn412x_gpio_dev *gn412x = arg;
struct gpio_chip *gc = &gn412x->gpiochip;
unsigned int cascade_irq;
uint32_t gpio_int_status, gpio_int_type;
unsigned long loop;
irqreturn_t ret = IRQ_NONE;
int i;
gpio_int_status = gn412x_ioread32(gn412x, GNGPIO_INT_STATUS);
gpio_int_status &= ~gn412x_ioread32(gn412x, GNGPIO_INT_MASK);
if (!gpio_int_status)
goto out_enable_irq;
loop = gpio_int_status;
for_each_set_bit(i, &loop, GN4124_GPIO_MAX) {
cascade_irq = irq_find_mapping(gc->irqdomain, i);
dev_dbg(gc->dev, "GPIO: %d, IRQ: %d\n", i, cascade_irq);
/*
* Ok, now we execute the handler for the given IRQ. Please
* note that this is not the action requested by the device
* driver but it is the handler defined during the IRQ mapping
*/
handle_nested_irq(cascade_irq);
}
/*
* Level interrupts are cleared only when they are processed. This
* means that at this point (interrupts have been processed) the
* GPIO_INT_STATUS is still set because it is a sticky bit that got
* set again after our first read because we did not handle yet
* the IRQ. For this reason we have to clear it (defentivelly) by
* reading again the register ...
*/
gpio_int_status = gn412x_ioread32(gn412x, GNGPIO_INT_STATUS);
/*
* ... but like this edge interrupts are lost. So write back
* in the register the status of all pending edge interrupts.
* (NOTE: not yet prooven that it works)
*/
gpio_int_type = gn412x_ioread32(gn412x, GNGPIO_INT_TYPE);
gn412x_iowrite32(gn412x, (gpio_int_status & (~gpio_int_type)),
GNGPIO_INT_STATUS);
ret = IRQ_HANDLED;
out_enable_irq:
/* Re-enable the GPIO interrupts, we are done here */
gn412x_gpio_int_cfg_enable(gn412x);
return ret;
}
static irqreturn_t gn412x_gpio_irq_handler_h(int irq, void *arg)
{
struct gn412x_gpio_dev *gn412x = arg;
uint32_t int_stat, int_cfg;
int_cfg = gn412x_ioread32(gn412x, GNINT_CFG(gn412x->pdata->int_cfg));
int_stat = gn412x_ioread32(gn412x, GNINT_STAT);
if (unlikely(!(int_stat & int_cfg)))
return IRQ_NONE;
if (unlikely(int_stat & GNINT_STAT_SW_ALL)) /* only for testing */
return spec_irq_sw_handler(irq, gn412x);
/*
* Do not listen to new interrupts while handling the current GPIOs.
* This may take a while since the chain behind each GPIO can be long.
* If the IRQ behind is level, we do not want this IRQ handeler to be
* called continuously. But on the other hand we do not want other
* devices sharing the same IRQ to wait for us; just to play safe,
* let's disable interrupts. Within the thread we will re-enable them
* when we are ready (like IRQF_ONESHOT).
*/
gn412x_gpio_int_cfg_disable(gn412x);
return IRQ_WAKE_THREAD;
}
static void gn412x_gpio_irq_set_nested_thread(struct gn412x_gpio_dev *gn412x,
unsigned int gpio, bool nest)
{
int irq;
irq = irq_find_mapping(gn412x->gpiochip.irqdomain, gpio);
irq_set_nested_thread(irq, nest);
}
static void gn412x_gpio_irq_set_nested_thread_all(struct gn412x_gpio_dev *gn412x,
bool nest)
{
int i;
for (i = 0; i < GN4124_GPIO_MAX; ++i)
gn412x_gpio_irq_set_nested_thread(gn412x, i, nest);
}
static int gn412x_gpio_probe(struct platform_device *pdev)
{
struct gn412x_gpio_dev *gn412x;
struct resource *r;
int err;
gn412x = devm_kzalloc(&pdev->dev, sizeof(*gn412x), GFP_KERNEL);
if (!gn412x)
return -ENOMEM;
platform_set_drvdata(pdev, gn412x);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(&pdev->dev, "Missing memory resource\n");
err = -EINVAL;
goto err_res_mem;
}
gn412x->mem = devm_ioremap(&pdev->dev, r->start, resource_size(r));
if (!gn412x->mem) {
err = -EADDRNOTAVAIL;
goto err_map;
}
gn412x->pdata = dev_get_platdata(&pdev->dev);
if (!gn412x->pdata) {
dev_warn(&pdev->dev, "Missing platform data, use default\n");
gn412x->pdata = &gn412x_gpio_pdata_default;
}
gn412x_iowrite32(gn412x, 0, GNGPIO_BYPASS_MODE);
gn412x->gpiochip.dev = &pdev->dev;
gn412x->gpiochip.label = "gn412x-gpio";
gn412x->gpiochip.owner = THIS_MODULE;
gn412x->gpiochip.request = gn412x_gpio_request;
gn412x->gpiochip.free = gn412x_gpio_free;
gn412x->gpiochip.get_direction = gn412x_gpio_get_direction;
gn412x->gpiochip.direction_input = gn412x_gpio_direction_input;
gn412x->gpiochip.direction_output = gn412x_gpio_direction_output;
gn412x->gpiochip.get = gn412x_gpio_get;
gn412x->gpiochip.set = gn412x_gpio_set;
gn412x->gpiochip.base = -1;
gn412x->gpiochip.ngpio = GN4124_GPIO_MAX;
gn412x->gpiochip.can_sleep = 0;
err = gpiochip_add(&gn412x->gpiochip);
if (err)
goto err_add;
gn412x_gpio_int_cfg_disable(gn412x);
gn412x_iowrite32(gn412x, 0xFFFF, GNGPIO_INT_MASK_SET);
err = gpiochip_irqchip_add(&gn412x->gpiochip,
&gn412x_gpio_irq_chip,
0, handle_simple_irq,
IRQ_TYPE_NONE);
if (err)
goto err_add_irq;
gn412x_gpio_irq_set_nested_thread_all(gn412x, true);
err = request_threaded_irq(platform_get_irq(pdev, 0),
gn412x_gpio_irq_handler_h,
gn412x_gpio_irq_handler_t,
IRQF_SHARED,
dev_name(gn412x->gpiochip.dev),
gn412x);
if (err) {
dev_err(gn412x->gpiochip.dev, "Can't request IRQ %d (%d)\n",
platform_get_irq(pdev, 0), err);
goto err_req;
}
gn412x_gpio_int_cfg_enable(gn412x);
gn412x_dbg_init(gn412x);
return 0;
err_req:
gn412x_gpio_irq_set_nested_thread_all(gn412x, false);
err_add_irq:
gpiochip_remove(&gn412x->gpiochip);
err_add:
devm_iounmap(&pdev->dev, gn412x->mem);
err_map:
err_res_mem:
devm_kfree(&pdev->dev, gn412x);
return err;
}
static int gn412x_gpio_remove(struct platform_device *pdev)
{
struct gn412x_gpio_dev *gn412x = platform_get_drvdata(pdev);
gn412x_dbg_exit(gn412x);
gn412x_gpio_int_cfg_disable(gn412x);
free_irq(platform_get_irq(pdev, 0), gn412x);
gn412x_gpio_irq_set_nested_thread_all(gn412x, false);
gpiochip_remove(&gn412x->gpiochip);
dev_dbg(&pdev->dev, "%s\n", __func__);
return 0;
}
static const struct platform_device_id gn412x_gpio_id[] = {
{
.name = "gn412x-gpio",
},
{ .name = "" }, /* last */
};
static struct platform_driver gn412x_gpio_platform_driver = {
.driver = {
.name = KBUILD_MODNAME,
},
.probe = gn412x_gpio_probe,
.remove = gn412x_gpio_remove,
.id_table = gn412x_gpio_id,
};
module_platform_driver(gn412x_gpio_platform_driver);
MODULE_AUTHOR("Federico Vaga ");
MODULE_DESCRIPTION("GN412X GPIO driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(VERSION);
MODULE_DEVICE_TABLE(platform, gn412x_gpio_id);
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/gn412x.h 0000664 0000000 0000000 00000004056 13533225622 0023345 0 ustar 00root root 0000000 0000000 /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2010-2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#ifndef __GN412X_H__
#define __GN412X_H__
#define GNINT_STAT_GPIO BIT(15)
#define GNINT_STAT_SW0 BIT(2)
#define GNINT_STAT_SW1 BIT(3)
#define GNINT_STAT_SW_ALL (GNINT_STAT_SW0 | GNINT_STAT_SW1)
/* Registers for GN4124 access */
enum {
/* page 106 */
GNPPCI_MSI_CONTROL = 0x48, /* actually, 3 smaller regs */
GNPPCI_MSI_ADDRESS_LOW = 0x4c,
GNPPCI_MSI_ADDRESS_HIGH = 0x50,
GNPPCI_MSI_DATA = 0x54,
GNPCI_SYS_CFG_SYSTEM = 0x800,
/* page 130 ff */
GNINT_CTRL = 0x810,
GNINT_STAT = 0x814,
GNINT_CFG_0 = 0x820,
GNINT_CFG_1 = 0x824,
GNINT_CFG_2 = 0x828,
GNINT_CFG_3 = 0x82c,
GNINT_CFG_4 = 0x830,
GNINT_CFG_5 = 0x834,
GNINT_CFG_6 = 0x838,
GNINT_CFG_7 = 0x83c,
#define GNINT_CFG(x) (GNINT_CFG_0 + 4 * (x))
/* page 146 ff */
GNGPIO_BASE = 0xA00,
GNGPIO_BYPASS_MODE = GNGPIO_BASE,
GNGPIO_DIRECTION_MODE = GNGPIO_BASE + 0x04, /* 0 == output */
GNGPIO_OUTPUT_ENABLE = GNGPIO_BASE + 0x08,
GNGPIO_OUTPUT_VALUE = GNGPIO_BASE + 0x0C,
GNGPIO_INPUT_VALUE = GNGPIO_BASE + 0x10,
GNGPIO_INT_MASK = GNGPIO_BASE + 0x14, /* 1 == disabled */
GNGPIO_INT_MASK_CLR = GNGPIO_BASE + 0x18, /* irq enable */
GNGPIO_INT_MASK_SET = GNGPIO_BASE + 0x1C, /* irq disable */
GNGPIO_INT_STATUS = GNGPIO_BASE + 0x20,
GNGPIO_INT_TYPE = GNGPIO_BASE + 0x24, /* 1 == level */
GNGPIO_INT_VALUE = GNGPIO_BASE + 0x28, /* 1 == high/rise */
GNGPIO_INT_ON_ANY = GNGPIO_BASE + 0x2C, /* both edges */
/* page 158 ff */
FCL_BASE = 0xB00,
FCL_CTRL = FCL_BASE,
FCL_STATUS = FCL_BASE + 0x04,
FCL_IODATA_IN = FCL_BASE + 0x08,
FCL_IODATA_OUT = FCL_BASE + 0x0C,
FCL_EN = FCL_BASE + 0x10,
FCL_TIMER_0 = FCL_BASE + 0x14,
FCL_TIMER_1 = FCL_BASE + 0x18,
FCL_CLK_DIV = FCL_BASE + 0x1C,
FCL_IRQ = FCL_BASE + 0x20,
FCL_TIMER_CTRL = FCL_BASE + 0x24,
FCL_IM = FCL_BASE + 0x28,
FCL_TIMER2_0 = FCL_BASE + 0x2C,
FCL_TIMER2_1 = FCL_BASE + 0x30,
FCL_DBG_STS = FCL_BASE + 0x34,
FCL_FIFO = 0xE00,
PCI_SYS_CFG_SYSTEM = 0x800
};
#endif
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/platform_data/ 0000775 0000000 0000000 00000000000 13533225622 0024761 5 ustar 00root root 0000000 0000000 spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/platform_data/gn412x-gpio.h 0000664 0000000 0000000 00000000407 13533225622 0027112 0 ustar 00root root 0000000 0000000 /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#ifndef __GN412X_GPIO_H__
#define __GN412X_GPIO_H__
struct gn412x_platform_data {
unsigned int int_cfg;
};
#endif
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/platform_data/spi-ocores.h 0000664 0000000 0000000 00000000705 13533225622 0027217 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#ifndef __SPI_OCORES_PDATA_H__
#define __SPI_OCORES_PDATA_H__
#include
/**
* struct spi_ocores_platform_data - OpenCores SPI data
*/
struct spi_ocores_platform_data {
unsigned int big_endian;
unsigned int clock_hz;
unsigned int num_devices;
struct spi_board_info *devices;
};
#endif
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/spec-compat.c 0000664 0000000 0000000 00000007676 13533225622 0024543 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#include
#include
#include
#include
#include
#include
#include "spec-compat.h"
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
struct fpga_manager *__fpga_mgr_get(struct device *dev)
{
struct fpga_manager *mgr;
int ret = -ENODEV;
mgr = to_fpga_manager(dev);
if (!mgr)
goto err_dev;
/* Get exclusive use of fpga manager */
if (!mutex_trylock(&mgr->ref_mutex)) {
ret = -EBUSY;
goto err_dev;
}
if (!try_module_get(dev->parent->driver->owner))
goto err_ll_mod;
return mgr;
err_ll_mod:
mutex_unlock(&mgr->ref_mutex);
err_dev:
put_device(dev);
return ERR_PTR(ret);
}
static int fpga_mgr_dev_match(struct device *dev, const void *data)
{
return dev->parent == data;
}
/**
* fpga_mgr_get - get an exclusive reference to a fpga mgr
* @dev:parent device that fpga mgr was registered with
*
* Given a device, get an exclusive reference to a fpga mgr.
*
* Return: fpga manager struct or IS_ERR() condition containing error code.
*/
struct fpga_manager *fpga_mgr_get(struct device *dev)
{
struct class *fpga_mgr_class = (struct class *) kallsyms_lookup_name("fpga_mgr_class");
struct device *mgr_dev;
mgr_dev = class_find_device(fpga_mgr_class, NULL, dev, fpga_mgr_dev_match);
if (!mgr_dev)
return ERR_PTR(-ENODEV);
return __fpga_mgr_get(mgr_dev);
}
#endif
static int __compat_spec_fw_load(struct fpga_manager *mgr, const char *name)
{
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE
return fpga_mgr_firmware_load(mgr, 0, name);
#else
struct fpga_image_info image;
memset(&image, 0, sizeof(image));
return fpga_mgr_firmware_load(mgr, &image, name);
#endif
#else
struct fpga_image_info image;
memset(&image, 0, sizeof(image));
image.firmware_name = (char *)name;
image.dev = mgr->dev.parent;
return fpga_mgr_load(mgr, &image);
#endif
}
struct mfd_find_data {
const char *name;
int id;
};
static int mfd_find_device_match(struct device *dev, void *data)
{
struct mfd_find_data *d = data;
struct platform_device *pdev = to_platform_device(dev);
if (strncmp(d->name, mfd_get_cell(pdev)->name,
strnlen(d->name, 32)) != 0)
return 0;
if (d->id >= 0 && pdev->id != d->id)
return 0;
return 1;
}
static struct platform_device *mfd_find_device(struct device *parent,
const char *name,
int id)
{
struct mfd_find_data d = {name, id};
struct device *dev;
dev = device_find_child(parent, (void *)&d, mfd_find_device_match);
if (!dev)
return NULL;
return to_platform_device(dev);
}
int compat_spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name)
{
struct fpga_manager *mgr;
struct platform_device *fpga_pdev;
int err;
fpga_pdev = mfd_find_device(&spec_gn412x->pdev->dev, "gn412x-fcl", -1);
if (!fpga_pdev)
return -ENODEV;
mgr = fpga_mgr_get(&fpga_pdev->dev);
if (IS_ERR(mgr))
return -ENODEV;
err = fpga_mgr_lock(mgr);
if (err)
goto out;
err = __compat_spec_fw_load(mgr, name);
fpga_mgr_unlock(mgr);
out:
fpga_mgr_put(mgr);
return err;
}
int compat_gpiod_add_lookup_table(struct gpiod_lookup_table *table)
{
void (*gpiod_add_lookup_table_p)(struct gpiod_lookup_table *table);
gpiod_add_lookup_table_p = (void *) kallsyms_lookup_name("gpiod_add_lookup_table");
if (gpiod_add_lookup_table_p)
gpiod_add_lookup_table_p(table);
else
return WARN(1, "Cannot find 'gpiod_add_lookup_table'");
return 0;
}
#if KERNEL_VERSION(4, 3, 0) > LINUX_VERSION_CODE
void gpiod_remove_lookup_table(struct gpiod_lookup_table *table)
{
struct mutex *gpio_lookup_lock_p = (void *) kallsyms_lookup_name("gpio_lookup_lock");
mutex_lock(gpio_lookup_lock_p);
list_del(&table->list);
mutex_unlock(gpio_lookup_lock_p);
}
#endif
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/spec-compat.h 0000664 0000000 0000000 00000003667 13533225622 0024544 0 ustar 00root root 0000000 0000000 /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#ifndef __SPEC_COMPAT_H__
#define __SPEC_COMPAT_H__
#include
#include
#include
#include
#include "spec.h"
#if KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE
/* So that we select the buffer size because smaller */
#define compat_fpga_ops_initial_header_size .initial_header_size = 0xFFFFFFFF,
#else
#define compat_fpga_ops_initial_header_size .initial_header_size = 0,
#endif
#else
#define compat_fpga_ops_initial_header_size
#endif
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
#define compat_fpga_ops_groups
#else
#define compat_fpga_ops_groups .groups = NULL,
#endif
#if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE && !defined(CONFIG_FPGA_MGR_BACKPORT)
struct fpga_image_info;
#endif
int compat_spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name);
#if KERNEL_VERSION(3, 11, 0) > LINUX_VERSION_CODE
#define __ATTR_RW(_name) __ATTR(_name, (S_IWUSR | S_IRUGO), \
_name##_show, _name##_store)
#define __ATTR_WO(_name) { \
.attr = { .name = __stringify(_name), .mode = S_IWUSR }, \
.store = _name##_store, \
}
#define DEVICE_ATTR_RW(_name) \
struct device_attribute dev_attr_##_name = __ATTR_RW(_name)
#define DEVICE_ATTR_RO(_name) \
struct device_attribute dev_attr_##_name = __ATTR_RO(_name)
#define DEVICE_ATTR_WO(_name) \
struct device_attribute dev_attr_##_name = __ATTR_WO(_name)
#endif
#if KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE
#define GPIO_PERSISTENT (0 << 3)
#endif
extern int compat_gpiod_add_lookup_table(struct gpiod_lookup_table *table);
#if KERNEL_VERSION(4, 3, 0) > LINUX_VERSION_CODE
extern void gpiod_remove_lookup_table(struct gpiod_lookup_table *table);
#endif
#endif /* __SPEC_COMPAT_H__ */
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/spec-core-fpga.c 0000664 0000000 0000000 00000055557 13533225622 0025124 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "spec.h"
#include "spec-compat.h"
#include "platform_data/spi-ocores.h"
enum spec_fpga_irq_lines {
SPEC_FPGA_IRQ_FMC_I2C = 0,
SPEC_FPGA_IRQ_SPI,
SPEC_FPGA_IRQ_DMA_DONE,
};
enum spec_fpga_csr_offsets {
SPEC_FPGA_CSR_APP_OFF = SPEC_TEMPLATE_REGS_CSR + 0x00,
SPEC_FPGA_CSR_RESETS = SPEC_TEMPLATE_REGS_CSR + 0x04,
SPEC_FPGA_CSR_FMC_PRESENT = SPEC_TEMPLATE_REGS_CSR + 0x08,
SPEC_FPGA_CSR_GN4124_STATUS = SPEC_TEMPLATE_REGS_CSR + 0x0C,
SPEC_FPGA_CSR_DDR_STATUS = SPEC_TEMPLATE_REGS_CSR + 0x10,
SPEC_FPGA_CSR_PCB_REV = SPEC_TEMPLATE_REGS_CSR + 0x14,
};
enum spec_fpga_csr_fields {
SPEC_FPGA_CSR_DDR_STATUS_DONE = 0x1,
};
enum spec_fpga_therm_offsets {
SPEC_FPGA_THERM_SERID_MSB = SPEC_TEMPLATE_REGS_THERM_ID + 0x0,
SPEC_FPGA_THERM_SERID_LSB = SPEC_TEMPLATE_REGS_THERM_ID + 0x4,
SPEC_FPGA_THERM_TEMP = SPEC_TEMPLATE_REGS_THERM_ID + 0x8,
};
enum spec_fpga_meta_cap_mask {
SPEC_META_CAP_VIC = BIT(0),
SPEC_META_CAP_THERM = BIT(1),
SPEC_META_CAP_SPI = BIT(2),
SPEC_META_CAP_WR = BIT(3),
SPEC_META_CAP_BLD = BIT(4),
SPEC_META_CAP_DMA = BIT(5),
};
static const struct debugfs_reg32 spec_fpga_debugfs_reg32[] = {
{
.name = "Application offset",
.offset = SPEC_FPGA_CSR_APP_OFF,
},
{
.name = "Resets",
.offset = SPEC_FPGA_CSR_RESETS,
},
{
.name = "FMC present",
.offset = SPEC_FPGA_CSR_FMC_PRESENT,
},
{
.name = "GN4124 Status",
.offset = SPEC_FPGA_CSR_GN4124_STATUS,
},
{
.name = "DDR Status",
.offset = SPEC_FPGA_CSR_DDR_STATUS,
},
{
.name = "PCB revision",
.offset = SPEC_FPGA_CSR_PCB_REV,
},
};
static int spec_fpga_dbg_bld_info(struct seq_file *s, void *offset)
{
struct spec_fpga *spec_fpga = s->private;
int off;
if (!(spec_fpga->meta->cap & SPEC_META_CAP_BLD)) {
seq_puts(s, "not available\n");
return 0;
}
for (off = SPEC_TEMPLATE_REGS_BUILDINFO;
off < SPEC_TEMPLATE_REGS_BUILDINFO + SPEC_TEMPLATE_REGS_BUILDINFO_SIZE -1;
off++) {
char tmp = ioread8(spec_fpga->fpga + off);
if (!tmp)
return 0;
seq_putc(s, tmp);
}
return 0;
}
static int spec_fpga_dbg_bld_info_open(struct inode *inode,
struct file *file)
{
struct spec_gn412x *spec = inode->i_private;
return single_open(file, spec_fpga_dbg_bld_info, spec);
}
static const struct file_operations spec_fpga_dbg_bld_info_ops = {
.owner = THIS_MODULE,
.open = spec_fpga_dbg_bld_info_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int spec_fpga_dbg_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pdev = to_pci_dev(spec_fpga->dev.parent);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
int err;
spec_fpga->dbg_dir_fpga = debugfs_create_dir(dev_name(&spec_fpga->dev),
spec_gn412x->dbg_dir);
if (IS_ERR_OR_NULL(spec_fpga->dbg_dir_fpga)) {
err = PTR_ERR(spec_fpga->dbg_dir_fpga);
dev_err(&spec_fpga->dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(&spec_fpga->dev), err);
return err;
}
spec_fpga->dbg_csr_reg.regs = spec_fpga_debugfs_reg32;
spec_fpga->dbg_csr_reg.nregs = ARRAY_SIZE(spec_fpga_debugfs_reg32);
spec_fpga->dbg_csr_reg.base = spec_fpga->fpga;
spec_fpga->dbg_csr = debugfs_create_regset32(SPEC_DBG_CSR_NAME, 0200,
spec_fpga->dbg_dir_fpga,
&spec_fpga->dbg_csr_reg);
if (IS_ERR_OR_NULL(spec_fpga->dbg_csr)) {
err = PTR_ERR(spec_fpga->dbg_csr);
dev_warn(&spec_fpga->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
SPEC_DBG_CSR_NAME, err);
goto err;
}
spec_fpga->dbg_bld_info = debugfs_create_file(SPEC_DBG_BLD_INFO_NAME, 0444,
spec_fpga->dbg_dir_fpga,
spec_fpga,
&spec_fpga_dbg_bld_info_ops);
if (IS_ERR_OR_NULL(spec_fpga->dbg_bld_info)) {
err = PTR_ERR(spec_fpga->dbg_bld_info);
dev_err(&spec_fpga->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
SPEC_DBG_BLD_INFO_NAME, err);
goto err;
}
return 0;
err:
debugfs_remove_recursive(spec_fpga->dbg_dir_fpga);
return err;
}
static void spec_fpga_dbg_exit(struct spec_fpga *spec_fpga)
{
debugfs_remove_recursive(spec_fpga->dbg_dir_fpga);
}
static inline uint32_t spec_fpga_csr_app_offset(struct spec_fpga *spec_fpga)
{
return ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_APP_OFF);
}
static inline uint32_t spec_fpga_csr_pcb_rev(struct spec_fpga *spec_fpga)
{
return ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_PCB_REV);
}
static struct resource spec_fpga_vic_res[] = {
{
.name = "htvic-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_TEMPLATE_REGS_VIC,
.end = SPEC_TEMPLATE_REGS_VIC + SPEC_TEMPLATE_REGS_VIC_SIZE -1,
}, {
.name = "htvic-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = 0,
.end = 0,
},
};
/* Vector Interrupt Controller */
static int spec_fpga_vic_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pcidev);
unsigned long pci_start = pci_resource_start(pcidev, 0);
const unsigned int res_n = ARRAY_SIZE(spec_fpga_vic_res);
struct resource res[ARRAY_SIZE(spec_fpga_vic_res)];
struct platform_device *pdev;
if (!(spec_fpga->meta->cap & SPEC_META_CAP_VIC))
return 0;
memcpy(&res, spec_fpga_vic_res, sizeof(spec_fpga_vic_res));
res[0].start += pci_start;
res[0].end += pci_start;
res[1].start = gpiod_to_irq(spec_gn412x->gpiod[GN4124_GPIO_IRQ1]);
res[1].end = res[1].start;
pdev = platform_device_register_resndata(&spec_fpga->dev,
"htvic-spec",
PLATFORM_DEVID_AUTO,
res, res_n,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
spec_fpga->vic_pdev = pdev;
return 0;
}
static void spec_fpga_vic_exit(struct spec_fpga *spec_fpga)
{
if (spec_fpga->vic_pdev) {
platform_device_unregister(spec_fpga->vic_pdev);
spec_fpga->vic_pdev = NULL;
}
}
/* DMA engine */
static struct resource spec_fpga_dma_res[] = {
{
.name = "spec-gn412x-dma-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_TEMPLATE_REGS_DMA,
.end = SPEC_TEMPLATE_REGS_DMA + SPEC_TEMPLATE_REGS_DMA_SIZE - 1,
}, {
.name = "spec-gn412x-dma-irq-done",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = 0,
.end = 0,
},
};
static int spec_fpga_dma_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
unsigned long pci_start = pci_resource_start(pcidev, 0);
const unsigned int res_n = ARRAY_SIZE(spec_fpga_dma_res);
struct resource res[ARRAY_SIZE(spec_fpga_dma_res)];
struct platform_device *pdev;
struct irq_domain *vic_domain;
uint32_t ddr_status;
if (!(spec_fpga->meta->cap & SPEC_META_CAP_DMA))
return 0;
mdelay(1);
ddr_status = ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_DDR_STATUS);
if (!(ddr_status & SPEC_FPGA_CSR_DDR_STATUS_DONE)) {
dev_err(&spec_fpga->dev,
"Failed to load DMA engine: DDR controller not calibrated - 0x%x.\n",
ddr_status);
return -ENODEV;
}
vic_domain = irq_find_host((void *)&spec_fpga->vic_pdev->dev);
if (!vic_domain) {
dev_err(&spec_fpga->dev,
"Failed to load DMA engine: missing can't find VIC.\n");
return -ENODEV;
}
memcpy(&res, spec_fpga_dma_res, sizeof(spec_fpga_dma_res));
res[0].start += pci_start;
res[0].end += pci_start;
res[1].start = irq_find_mapping(vic_domain, SPEC_FPGA_IRQ_DMA_DONE);
pdev = platform_device_register_resndata(&spec_fpga->dev,
"spec-gn412x-dma",
PLATFORM_DEVID_AUTO,
res, res_n,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
spec_fpga->dma_pdev = pdev;
return 0;
}
static void spec_fpga_dma_exit(struct spec_fpga *spec_fpga)
{
if (spec_fpga->dma_pdev) {
platform_device_unregister(spec_fpga->dma_pdev);
spec_fpga->dma_pdev = NULL;
}
}
/* MFD devices */
enum spec_fpga_mfd_devs_enum {
SPEC_FPGA_MFD_FMC_I2C = 0,
SPEC_FPGA_MFD_SPI,
};
static struct resource spec_fpga_fmc_i2c_res[] = {
{
.name = "i2c-ocores-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_TEMPLATE_REGS_FMC_I2C,
.end = SPEC_TEMPLATE_REGS_FMC_I2C + SPEC_TEMPLATE_REGS_FMC_I2C_SIZE -1,
}, {
.name = "i2c-ocores-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = SPEC_FPGA_IRQ_FMC_I2C,
.end = SPEC_FPGA_IRQ_FMC_I2C,
},
};
#define SPEC_FPGA_WB_CLK_HZ 62500000
#define SPEC_FPGA_WB_CLK_KHZ (SPEC_FPGA_WB_CLK_HZ / 1000)
static struct ocores_i2c_platform_data spec_fpga_fmc_i2c_pdata = {
.reg_shift = 2, /* 32bit aligned */
.reg_io_width = 4,
.clock_khz = SPEC_FPGA_WB_CLK_KHZ,
.big_endian = 0,
.num_devices = 0,
.devices = NULL,
};
static struct resource spec_fpga_spi_res[] = {
{
.name = "spi-ocores-mem",
.flags = IORESOURCE_MEM,
.start = SPEC_TEMPLATE_REGS_FLASH_SPI,
.end = SPEC_TEMPLATE_REGS_FLASH_SPI + SPEC_TEMPLATE_REGS_FLASH_SPI_SIZE - 1,
}, {
.name = "spi-ocores-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = SPEC_FPGA_IRQ_SPI,
.end = SPEC_FPGA_IRQ_SPI,
},
};
struct flash_platform_data spec_flash_pdata = {
.name = "spec-flash",
.parts = NULL,
.nr_parts = 0,
.type = "m25p32",
};
static struct spi_board_info spec_fpga_spi_devices_info[] = {
{
.modalias = "m25p32",
.max_speed_hz = SPEC_FPGA_WB_CLK_HZ / 128,
.chip_select = 0,
.platform_data = &spec_flash_pdata,
}
};
static struct spi_ocores_platform_data spec_fpga_spi_pdata = {
.big_endian = 0,
.clock_hz = SPEC_FPGA_WB_CLK_HZ,
.num_devices = ARRAY_SIZE(spec_fpga_spi_devices_info),
.devices = spec_fpga_spi_devices_info,
};
static const struct mfd_cell spec_fpga_mfd_devs[] = {
[SPEC_FPGA_MFD_FMC_I2C] = {
.name = "i2c-ohwr",
.platform_data = &spec_fpga_fmc_i2c_pdata,
.pdata_size = sizeof(spec_fpga_fmc_i2c_pdata),
.num_resources = ARRAY_SIZE(spec_fpga_fmc_i2c_res),
.resources = spec_fpga_fmc_i2c_res,
},
[SPEC_FPGA_MFD_SPI] = {
.name = "spi-ocores",
.platform_data = &spec_fpga_spi_pdata,
.pdata_size = sizeof(spec_fpga_spi_pdata),
.num_resources = ARRAY_SIZE(spec_fpga_spi_res),
.resources = spec_fpga_spi_res,
},
};
static inline size_t __fpga_mfd_devs_size(void)
{
#define SPEC_FPGA_MFD_DEVS_MAX 4
return (sizeof(struct mfd_cell) * SPEC_FPGA_MFD_DEVS_MAX);
}
static int spec_fpga_devices_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
struct mfd_cell *fpga_mfd_devs;
struct irq_domain *vic_domain;
unsigned int n_mfd = 0;
int err;
fpga_mfd_devs = devm_kzalloc(&spec_fpga->dev,
__fpga_mfd_devs_size(),
GFP_KERNEL);
if (!fpga_mfd_devs)
return -ENOMEM;
memcpy(&fpga_mfd_devs[n_mfd],
&spec_fpga_mfd_devs[SPEC_FPGA_MFD_FMC_I2C],
sizeof(fpga_mfd_devs[n_mfd]));
n_mfd++;
if (spec_fpga->meta->cap & SPEC_META_CAP_SPI) {
memcpy(&fpga_mfd_devs[n_mfd],
&spec_fpga_mfd_devs[SPEC_FPGA_MFD_SPI],
sizeof(fpga_mfd_devs[n_mfd]));
n_mfd++;
}
vic_domain = irq_find_host((void *)&spec_fpga->vic_pdev->dev);
if (!vic_domain) {
/* Remove IRQ resource from all devices */
fpga_mfd_devs[0].num_resources = 1; /* FMC I2C */
fpga_mfd_devs[1].num_resources = 1; /* SPI */
}
err = mfd_add_devices(&spec_fpga->dev,
PLATFORM_DEVID_AUTO,
fpga_mfd_devs, n_mfd,
&pcidev->resource[0],
0, vic_domain);
if (err)
goto err_mfd;
return 0;
err_mfd:
devm_kfree(&spec_fpga->dev, fpga_mfd_devs);
return err;
}
static void spec_fpga_devices_exit(struct spec_fpga *spec_fpga)
{
mfd_remove_devices(&spec_fpga->dev);
}
/* Thermometer */
static ssize_t temperature_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
if (spec_fpga->meta->cap & SPEC_META_CAP_THERM) {
uint32_t temp = ioread32(spec_fpga->fpga + SPEC_FPGA_THERM_TEMP);
return snprintf(buf, PAGE_SIZE, "%d.%d C\n",
temp / 16, (temp & 0xF) * 1000 / 16);
} else {
return snprintf(buf, PAGE_SIZE, "-.- C\n");
}
}
static DEVICE_ATTR_RO(temperature);
static ssize_t serial_number_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
if (spec_fpga->meta->cap & SPEC_META_CAP_THERM) {
uint32_t msb = ioread32(spec_fpga->fpga + SPEC_FPGA_THERM_SERID_MSB);
uint32_t lsb = ioread32(spec_fpga->fpga + SPEC_FPGA_THERM_SERID_LSB);
return snprintf(buf, PAGE_SIZE, "0x%08x%08x\n", msb, lsb);
} else {
return snprintf(buf, PAGE_SIZE, "0x----------------\n");
}
}
static DEVICE_ATTR_RO(serial_number);
static struct attribute *spec_fpga_therm_attrs[] = {
&dev_attr_serial_number.attr,
&dev_attr_temperature.attr,
NULL,
};
static const struct attribute_group spec_fpga_therm_group = {
.name = "thermometer",
.attrs = spec_fpga_therm_attrs,
};
/* CSR attributes */
static ssize_t pcb_rev_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
return snprintf(buf, PAGE_SIZE, "0x%x\n",
spec_fpga_csr_pcb_rev(spec_fpga));
}
static DEVICE_ATTR_RO(pcb_rev);
static ssize_t application_offset_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
return snprintf(buf, PAGE_SIZE, "0x%x\n",
spec_fpga_csr_app_offset(spec_fpga));
}
static DEVICE_ATTR_RO(application_offset);
enum spec_fpga_csr_resets {
SPEC_FPGA_CSR_RESETS_ALL = BIT(0),
SPEC_FPGA_CSR_RESETS_APP = BIT(1),
};
static void spec_fpga_app_reset(struct spec_fpga *spec_fpga, bool val)
{
uint32_t resets;
resets = ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_RESETS);
if (val)
resets |= SPEC_FPGA_CSR_RESETS_APP;
else
resets &= ~SPEC_FPGA_CSR_RESETS_APP;
iowrite32(resets, spec_fpga->fpga + SPEC_FPGA_CSR_RESETS);
}
static void spec_fpga_app_restart(struct spec_fpga *spec_fpga)
{
spec_fpga_app_reset(spec_fpga, true);
udelay(1);
spec_fpga_app_reset(spec_fpga, false);
udelay(1);
}
static ssize_t reset_app_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct spec_fpga *spec_fpga = to_spec_fpga(dev);
uint32_t resets;
resets = ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_RESETS);
return snprintf(buf, PAGE_SIZE, "%d\n",
!!(resets & SPEC_FPGA_CSR_RESETS_APP));
}
static ssize_t reset_app_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
spec_fpga_app_reset(to_spec_fpga(dev), val);
return count;
}
static DEVICE_ATTR(reset_app, 0644, reset_app_show, reset_app_store);
static struct attribute *spec_fpga_csr_attrs[] = {
&dev_attr_pcb_rev.attr,
&dev_attr_application_offset.attr,
&dev_attr_reset_app.attr,
NULL,
};
static const struct attribute_group spec_fpga_csr_group = {
.attrs = spec_fpga_csr_attrs,
};
/* FMC */
#define SPEC_FMC_SLOTS 1
static inline u8 spec_fmc_presence(struct spec_fpga *spec_fpga)
{
return (ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_FMC_PRESENT) & 0x1);
}
static int spec_fmc_is_present(struct fmc_carrier *carrier,
struct fmc_slot *slot)
{
struct spec_fpga *spec_fpga = carrier->priv;
return spec_fmc_presence(spec_fpga);
}
static const struct fmc_carrier_operations spec_fmc_ops = {
.owner = THIS_MODULE,
.is_present = spec_fmc_is_present,
};
static int spec_i2c_find_adapter(struct device *dev, void *data)
{
struct spec_fpga *spec_fpga = data;
struct i2c_adapter *adap, *adap_parent;
if (dev->type != &i2c_adapter_type)
return 0;
adap = to_i2c_adapter(dev);
adap_parent = i2c_parent_is_i2c_adapter(adap);
if (!adap_parent)
return 0;
/* We have a muxed I2C master */
if (&spec_fpga->dev != adap_parent->dev.parent->parent)
return 0;
/* Found! Return the bus ID */
return i2c_adapter_id(adap);
}
/**
* Get the I2C adapter associated with an FMC slot
* @data: data used to find the correct I2C bus
* @slot_nr: FMC slot number
*
* Return: the I2C bus to be used
*/
static int spec_i2c_get_bus(struct spec_fpga *spec_fpga)
{
return i2c_for_each_dev(spec_fpga, spec_i2c_find_adapter);
}
/**
* Create an FMC interface
*/
static int spec_fmc_init(struct spec_fpga *spec_fpga)
{
int err;
spec_fpga->slot_info.i2c_bus_nr = spec_i2c_get_bus(spec_fpga);
if (spec_fpga->slot_info.i2c_bus_nr <= 0)
return -ENODEV;
spec_fpga->slot_info.ga = 0;
spec_fpga->slot_info.lun = 1;
err = fmc_carrier_register(&spec_fpga->dev, &spec_fmc_ops,
SPEC_FMC_SLOTS, &spec_fpga->slot_info,
spec_fpga);
if (err) {
dev_err(spec_fpga->dev.parent,
"Failed to register as FMC carrier\n");
goto err_fmc;
}
return 0;
err_fmc:
return err;
}
static int spec_fmc_exit(struct spec_fpga *spec_fpga)
{
return fmc_carrier_unregister(&spec_fpga->dev);
}
/* FPGA Application */
/**
* Build the platform_device_id->name from metadata
*
* The byte order on SPEC is little endian, but we want to convert it
* in string. Use big-endian read to swap word and get the string order
* from MSB to LSB
*/
static int spec_fpga_app_id_build(struct spec_fpga *spec_fpga,
unsigned long app_off,
char *id, unsigned int size)
{
uint32_t vendor = ioread32be(spec_fpga->fpga + app_off + FPGA_META_VENDOR);
uint32_t device = ioread32be(spec_fpga->fpga + app_off + FPGA_META_DEVICE);
memset(id, 0, size);
if (vendor == 0xFF000000) {
dev_warn(&spec_fpga->dev, "Vendor UUID not supported yet\n");
return -ENODEV;
} else {
snprintf(id, size, "id:%4phN%4phN", &vendor, &device);
}
return 0;
}
static int spec_fpga_app_init(struct spec_fpga *spec_fpga)
{
#define SPEC_FPGA_APP_NAME_MAX 47
#define SPEC_FPGA_APP_IRQ_BASE 6
#define SPEC_FPGA_APP_RES_N (32 - SPEC_FPGA_APP_IRQ_BASE + 1)
struct pci_dev *pcidev = to_pci_dev(spec_fpga->dev.parent);
unsigned int res_n = SPEC_FPGA_APP_RES_N;
struct resource res[SPEC_FPGA_APP_RES_N] = {
[0] = {
.name = "app-mem",
.flags = IORESOURCE_MEM,
},
};
struct platform_device *pdev;
struct irq_domain *vic_domain;
char app_name[SPEC_FPGA_APP_NAME_MAX];
unsigned long app_offset;
int err;
app_offset = spec_fpga_csr_app_offset(spec_fpga);
if (!app_offset) {
dev_warn(&spec_fpga->dev, "Application not found\n");
return 0;
}
res[0].start = pci_resource_start(pcidev, 0) + app_offset;
res[0].end = pci_resource_end(pcidev, 0);
if (spec_fpga->vic_pdev)
vic_domain = irq_find_host((void *)&spec_fpga->vic_pdev->dev);
else
vic_domain = NULL;
if (vic_domain) {
int i, hwirq;
for (i = 1, hwirq = SPEC_FPGA_APP_IRQ_BASE;
i < SPEC_FPGA_APP_RES_N;
++i, ++hwirq) {
res[i].name = "app-irq",
res[i].flags = IORESOURCE_IRQ,
res[i].start = irq_find_mapping(vic_domain, hwirq);
res[i].end = res[1].start;
}
} else {
res_n = 1;
}
err = spec_fpga_app_id_build(spec_fpga, app_offset,
app_name, SPEC_FPGA_APP_NAME_MAX);
if (err)
return err;
spec_fpga_app_restart(spec_fpga);
pdev = platform_device_register_resndata(&spec_fpga->dev,
app_name, PLATFORM_DEVID_AUTO,
res, res_n,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
spec_fpga->app_pdev = pdev;
return 0;
}
static void spec_fpga_app_exit(struct spec_fpga *spec_fpga)
{
if (spec_fpga->app_pdev) {
platform_device_unregister(spec_fpga->app_pdev);
spec_fpga->app_pdev = NULL;
}
}
static bool spec_fpga_is_valid(struct spec_gn412x *spec_gn412x,
struct spec_meta_id *meta)
{
if ((meta->bom & SPEC_META_BOM_END_MASK) != SPEC_META_BOM_LE) {
dev_err(&spec_gn412x->pdev->dev,
"Expected Little Endian devices BOM: 0x%x\n",
meta->bom);
return false;
}
if ((meta->bom & SPEC_META_BOM_VER_MASK) != 0) {
dev_err(&spec_gn412x->pdev->dev,
"Unknow Metadata specification version BOM: 0x%x\n",
meta->bom);
return false;
}
if (meta->vendor != SPEC_META_VENDOR_ID ||
meta->device != SPEC_META_DEVICE_ID) {
dev_err(&spec_gn412x->pdev->dev,
"Unknow vendor/device ID: %08x:%08x\n",
meta->vendor, meta->device);
return false;
}
if ((meta->version & SPEC_META_VERSION_MASK) != SPEC_META_VERSION_1_4) {
dev_err(&spec_gn412x->pdev->dev,
"Unknow version: %08x\n", meta->version);
return false;
}
return true;
}
static void spec_release(struct device *dev)
{
}
static int spec_uevent(struct device *dev, struct kobj_uevent_env *env)
{
return 0;
}
static const struct attribute_group *spec_groups[] = {
&spec_fpga_therm_group,
&spec_fpga_csr_group,
NULL
};
static const struct device_type spec_fpga_type = {
.name = "spec",
.release = spec_release,
.uevent = spec_uevent,
.groups = spec_groups,
};
/**
* Initialize carrier devices on FPGA
*/
int spec_fpga_init(struct spec_gn412x *spec_gn412x)
{
struct spec_fpga *spec_fpga;
struct resource *r0 = &spec_gn412x->pdev->resource[0];
int err;
spec_fpga = kzalloc(sizeof(*spec_fpga), GFP_KERNEL);
if (!spec_fpga)
return -ENOMEM;
spec_gn412x->spec_fpga = spec_fpga;
spec_fpga->fpga = ioremap(r0->start, resource_size(r0));
if (!spec_fpga->fpga) {
err = -ENOMEM;
goto err_map;
}
spec_fpga->meta = spec_fpga->fpga + SPEC_META_BASE;
if (!spec_fpga_is_valid(spec_gn412x, spec_fpga->meta)) {
err = -EINVAL;
goto err_valid;
}
spec_fpga->dev.parent = &spec_gn412x->pdev->dev;
spec_fpga->dev.driver = spec_gn412x->pdev->dev.driver;
spec_fpga->dev.type = &spec_fpga_type;
err = dev_set_name(&spec_fpga->dev, "spec-%s",
dev_name(&spec_gn412x->pdev->dev));
if (err)
goto err_name;
err = device_register(&spec_fpga->dev);
if (err) {
dev_err(&spec_gn412x->pdev->dev, "Failed to register '%s'\n",
dev_name(&spec_gn412x->pdev->dev));
goto err_dev;
}
spec_fpga_dbg_init(spec_fpga);
err = spec_fpga_vic_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize VIC %d\n", err);
goto err_vic;
}
err = spec_fpga_dma_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize DMA %d\n", err);
goto err_dma;
}
err = spec_fpga_devices_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize Devices %d\n", err);
goto err_devs;
}
err = spec_fmc_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize FMC %d\n", err);
goto err_fmc;
}
err = spec_fpga_app_init(spec_fpga);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to initialize APP %d\n", err);
goto err_app;
}
return 0;
err_app:
spec_fmc_exit(spec_fpga);
err_fmc:
spec_fpga_devices_exit(spec_fpga);
err_devs:
spec_fpga_dma_exit(spec_fpga);
err_dma:
spec_fpga_vic_exit(spec_fpga);
err_vic:
return err;
err_dev:
err_name:
err_valid:
iounmap(spec_fpga->fpga);
err_map:
kfree(spec_fpga);
spec_gn412x->spec_fpga = NULL;
return err;
}
int spec_fpga_exit(struct spec_gn412x *spec_gn412x)
{
struct spec_fpga *spec_fpga = spec_gn412x->spec_fpga;
if (!spec_fpga)
return 0;
spec_fpga_app_exit(spec_fpga);
spec_fmc_exit(spec_fpga);
spec_fpga_devices_exit(spec_fpga);
spec_fpga_dma_exit(spec_fpga);
spec_fpga_vic_exit(spec_fpga);
spec_fpga_dbg_exit(spec_fpga);
device_unregister(&spec_fpga->dev);
iounmap(spec_fpga->fpga);
kfree(spec_fpga);
spec_gn412x->spec_fpga = NULL;
return 0;
}
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/spec-core.c 0000664 0000000 0000000 00000044257 13533225622 0024204 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*
* Driver for SPEC (Simple PCI FMC carrier) board.
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "platform_data/gn412x-gpio.h"
#include "spec.h"
#include "spec-compat.h"
static char *spec_fw_name_45t = "spec-golden-45T.bin";
static char *spec_fw_name_100t = "spec-golden-100T.bin";
static char *spec_fw_name_150t = "spec-golden-150T.bin";
char *spec_fw_name = "";
module_param_named(fw_name, spec_fw_name, charp, 0444);
static int spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name);
/* Debugging */
static int spec_irq_dbg_info(struct seq_file *s, void *offset)
{
struct spec_gn412x *spec_gn412x = s->private;
seq_printf(s, "'%s':\n", dev_name(&spec_gn412x->pdev->dev));
seq_printf(s, " redirect: %d\n",
to_pci_dev(&spec_gn412x->pdev->dev)->irq);
seq_puts(s, " irq-mapping:\n");
seq_puts(s, " - hardware: 8\n");
seq_printf(s, " linux: %d\n",
gpiod_to_irq(spec_gn412x->gpiod[GN4124_GPIO_IRQ1]));
seq_puts(s, " - hardware: 9\n");
seq_printf(s, " linux: %d\n",
gpiod_to_irq(spec_gn412x->gpiod[GN4124_GPIO_IRQ0]));
return 0;
}
static int spec_irq_dbg_info_open(struct inode *inode, struct file *file)
{
struct spec_gn412x *spec = inode->i_private;
return single_open(file, spec_irq_dbg_info, spec);
}
static const struct file_operations spec_irq_dbg_info_ops = {
.owner = THIS_MODULE,
.open = spec_irq_dbg_info_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static ssize_t spec_dbg_fw_write(struct file *file,
const char __user *buf,
size_t count, loff_t *ppos)
{
struct spec_gn412x *spec_gn412x = file->private_data;
int err;
if (!buf || !count) {
dev_err(&spec_gn412x->pdev->dev, "Invalid input\n");
return -EINVAL;
}
err = spec_fw_load(spec_gn412x, buf);
if (err)
return err;
return count;
}
static int spec_dbg_fw_open(struct inode *inode, struct file *file)
{
file->private_data = inode->i_private;
return 0;
}
static const struct file_operations spec_dbg_fw_ops = {
.owner = THIS_MODULE,
.open = spec_dbg_fw_open,
.write = spec_dbg_fw_write,
};
static int spec_dbg_meta(struct seq_file *s, void *offset)
{
struct spec_gn412x *spec_gn412x = s->private;
struct resource *r0 = &spec_gn412x->pdev->resource[0];
struct spec_meta_id __iomem *meta;
meta = ioremap(r0->start + SPEC_META_BASE, sizeof(*meta));
if (!meta) {
dev_warn(&spec_gn412x->pdev->dev, "%s: Mapping failed\n",
__func__);
return -ENOMEM;
}
seq_printf(s, "'%s':\n", dev_name(&spec_gn412x->pdev->dev));
seq_puts(s, "Metadata:\n");
seq_printf(s, " - Vendor: 0x%08x\n", meta->vendor);
seq_printf(s, " - Device: 0x%08x\n", meta->device);
seq_printf(s, " - Version: 0x%08x\n", meta->version);
seq_printf(s, " - BOM: 0x%08x\n", meta->bom);
seq_printf(s, " - SourceID: 0x%08x%08x%08x%08x\n",
meta->src[0],
meta->src[1],
meta->src[2],
meta->src[3]);
seq_printf(s, " - CapabilityMask: 0x%08x\n", meta->cap);
seq_printf(s, " - VendorUUID: 0x%08x%08x%08x%08x\n",
meta->uuid[0],
meta->uuid[1],
meta->uuid[2],
meta->uuid[3]);
iounmap(meta);
return 0;
}
static int spec_dbg_meta_open(struct inode *inode, struct file *file)
{
struct spec_gn412x *spec = inode->i_private;
return single_open(file, spec_dbg_meta, spec);
}
static const struct file_operations spec_dbg_meta_ops = {
.owner = THIS_MODULE,
.open = spec_dbg_meta_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
/**
* It initializes the debugfs interface
* @spec: SPEC device instance
*
* Return: 0 on success, otherwise a negative error number
*/
static int spec_dbg_init(struct spec_gn412x *spec_gn412x)
{
struct device *dev = &spec_gn412x->pdev->dev;
spec_gn412x->dbg_dir = debugfs_create_dir(dev_name(dev),
NULL);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_dir)) {
dev_err(dev, "Cannot create debugfs directory (%ld)\n",
PTR_ERR(spec_gn412x->dbg_dir));
return PTR_ERR(spec_gn412x->dbg_dir);
}
spec_gn412x->dbg_info = debugfs_create_file(SPEC_DBG_INFO_NAME, 0444,
spec_gn412x->dbg_dir,
spec_gn412x,
&spec_irq_dbg_info_ops);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_info)) {
dev_err(dev, "Cannot create debugfs file \"%s\" (%ld)\n",
SPEC_DBG_INFO_NAME, PTR_ERR(spec_gn412x->dbg_info));
return PTR_ERR(spec_gn412x->dbg_info);
}
spec_gn412x->dbg_fw = debugfs_create_file(SPEC_DBG_FW_NAME, 0200,
spec_gn412x->dbg_dir,
spec_gn412x,
&spec_dbg_fw_ops);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_fw)) {
dev_err(dev, "Cannot create debugfs file \"%s\" (%ld)\n",
SPEC_DBG_FW_NAME, PTR_ERR(spec_gn412x->dbg_fw));
return PTR_ERR(spec_gn412x->dbg_fw);
}
spec_gn412x->dbg_meta = debugfs_create_file(SPEC_DBG_META_NAME, 0200,
spec_gn412x->dbg_dir,
spec_gn412x,
&spec_dbg_meta_ops);
if (IS_ERR_OR_NULL(spec_gn412x->dbg_meta)) {
dev_err(dev, "Cannot create debugfs file \"%s\" (%ld)\n",
SPEC_DBG_META_NAME, PTR_ERR(spec_gn412x->dbg_meta));
return PTR_ERR(spec_gn412x->dbg_meta);
}
return 0;
}
/**
* It removes the debugfs interface
* @spec: SPEC device instance
*/
static void spec_dbg_exit(struct spec_gn412x *spec_gn412x)
{
debugfs_remove_recursive(spec_gn412x->dbg_dir);
}
/* SPEC GPIO configuration */
static void spec_gpio_fpga_select_set(struct spec_gn412x *spec_gn412x,
enum spec_fpga_select sel)
{
switch (sel) {
case SPEC_FPGA_SELECT_FPGA_FLASH:
case SPEC_FPGA_SELECT_GN4124_FPGA:
case SPEC_FPGA_SELECT_GN4124_FLASH:
gpiod_set_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0],
!!(sel & 0x1));
gpiod_set_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1],
!!(sel & 0x2));
break;
default:
break;
}
}
static enum spec_fpga_select spec_gpio_fpga_select_get(struct spec_gn412x *spec_gn412x)
{
enum spec_fpga_select sel = 0;
sel |= !!gpiod_get_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1]) << 1;
sel |= !!gpiod_get_value(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0]) << 0;
return sel;
}
static const struct gpiod_lookup_table spec_gpiod_table = {
.table = {
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_BOOTSEL0,
"bootsel", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_BOOTSEL1,
"bootsel", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SPRI_DIN,
"spi", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SPRI_FLASH_CS,
"spi", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_IRQ0,
"irq", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_IRQ1,
"irq", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SCL,
"i2c", 0,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
GPIO_LOOKUP_IDX("gn412x-gpio", GN4124_GPIO_SDA,
"i2c", 1,
GPIO_ACTIVE_HIGH | GPIO_PERSISTENT),
{},
}
};
static inline size_t spec_gpiod_table_size(void)
{
return sizeof(struct gpiod_lookup_table) +
(sizeof(struct gpiod_lookup) * 9);
}
static int spec_gpio_init_table(struct spec_gn412x *spec_gn412x)
{
struct gpiod_lookup_table *lookup;
int err = 0;
lookup = kzalloc(spec_gpiod_table_size(), GFP_KERNEL);
if (!lookup)
return -ENOMEM;
memcpy(lookup, &spec_gpiod_table, spec_gpiod_table_size());
lookup->dev_id = kstrdup(dev_name(&spec_gn412x->pdev->dev), GFP_KERNEL);
if (!lookup->dev_id)
goto err_dup;
spec_gn412x->gpiod_table = lookup;
err = compat_gpiod_add_lookup_table(spec_gn412x->gpiod_table);
if (err)
goto err_lookup;
return 0;
err_lookup:
kfree(lookup->dev_id);
err_dup:
kfree(lookup);
return err;
}
static void spec_gpio_exit_table(struct spec_gn412x *spec_gn412x)
{
struct gpiod_lookup_table *lookup = spec_gn412x->gpiod_table;
gpiod_remove_lookup_table(spec_gn412x->gpiod_table);
kfree(lookup->dev_id);
kfree(lookup);
spec_gn412x->gpiod_table = NULL;
}
/**
* Configure bootsel GPIOs
*
* Note: Because of a BUG in RedHat kernel 3.10 we re-set direction
*/
static int spec_gpio_init_bootsel(struct spec_gn412x *spec_gn412x)
{
struct gpio_desc *gpiod;
int err;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "bootsel", 0,
GPIOD_OUT_HIGH);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel0;
}
err = gpiod_direction_output(gpiod, 1);
if (err) {
gpiod_put(gpiod);
goto err_out0;
}
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0] = gpiod;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "bootsel", 1,
GPIOD_OUT_HIGH);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel1;
}
err = gpiod_direction_output(gpiod, 1);
if (err) {
gpiod_put(gpiod);
goto err_out1;
}
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1] = gpiod;
return 0;
err_out1:
err_sel1:
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0]);
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0] = NULL;
err_out0:
err_sel0:
return err;
}
static void spec_gpio_exit_bootsel(struct spec_gn412x *spec_gn412x)
{
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1]);
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL1] = NULL;
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0]);
spec_gn412x->gpiod[GN4124_GPIO_BOOTSEL0] = NULL;
}
/**
* Configure IRQ GPIOs
*
* Note: Because of a BUG in RedHat kernel 3.10 we re-set direction
*/
static int spec_gpio_init_irq(struct spec_gn412x *spec_gn412x)
{
struct gpio_desc *gpiod;
int err;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "irq", 0, GPIOD_IN);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel0;
}
err = gpiod_direction_input(gpiod);
if (err) {
gpiod_put(gpiod);
goto err_out0;
}
spec_gn412x->gpiod[GN4124_GPIO_IRQ0] = gpiod;
gpiod = gpiod_get_index(&spec_gn412x->pdev->dev, "irq", 1, GPIOD_IN);
if (IS_ERR(gpiod)) {
err = PTR_ERR(gpiod);
goto err_sel1;
}
err = gpiod_direction_input(gpiod);
if (err) {
gpiod_put(gpiod);
goto err_out1;
}
spec_gn412x->gpiod[GN4124_GPIO_IRQ1] = gpiod;
return 0;
err_out1:
err_sel1:
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_IRQ0]);
spec_gn412x->gpiod[GN4124_GPIO_IRQ0] = NULL;
err_out0:
err_sel0:
return err;
}
static void spec_gpio_exit_irq(struct spec_gn412x *spec_gn412x)
{
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_IRQ1]);
spec_gn412x->gpiod[GN4124_GPIO_IRQ1] = NULL;
gpiod_put(spec_gn412x->gpiod[GN4124_GPIO_IRQ0]);
spec_gn412x->gpiod[GN4124_GPIO_IRQ0] = NULL;
}
static int spec_gpio_init(struct spec_gn412x *spec_gn412x)
{
int err;
err = spec_gpio_init_table(spec_gn412x);
if (err)
return err;
err = spec_gpio_init_bootsel(spec_gn412x);
if (err)
goto err_bootsel;
err = spec_gpio_init_irq(spec_gn412x);
if (err)
goto err_irq;
return 0;
err_irq:
spec_gpio_exit_bootsel(spec_gn412x);
err_bootsel:
spec_gpio_exit_table(spec_gn412x);
return err;
}
static void spec_gpio_exit(struct spec_gn412x *spec_gn412x)
{
spec_gpio_exit_irq(spec_gn412x);
spec_gpio_exit_bootsel(spec_gn412x);
spec_gpio_exit_table(spec_gn412x);
}
/* SPEC sub-devices */
static struct gn412x_platform_data gn412x_gpio_pdata = {
.int_cfg = 0,
};
static struct resource gn412x_gpio_res[] = {
{
.name = "gn412x-gpio-mem",
.flags = IORESOURCE_MEM,
.start = 0,
.end = 0x1000 - 1,
}, {
.name = "gn412x-gpio-irq",
.flags = IORESOURCE_IRQ,
.start = 0,
.end = 0,
}
};
static struct resource gn412x_fcl_res[] = {
{
.name = "gn412x-fcl-mem",
.flags = IORESOURCE_MEM,
.start = 0,
.end = 0x1000 - 1,
}, {
.name = "gn412x-fcl-irq",
.flags = IORESOURCE_IRQ,
.start = 0,
.end = 0,
}
};
enum spec_mfd_enum {
SPEC_MFD_GN412X_GPIO = 0,
SPEC_MFD_GN412X_FCL,
};
static const struct mfd_cell spec_mfd_devs[] = {
[SPEC_MFD_GN412X_GPIO] = {
.name = "gn412x-gpio",
.platform_data = &gn412x_gpio_pdata,
.pdata_size = sizeof(gn412x_gpio_pdata),
.num_resources = ARRAY_SIZE(gn412x_gpio_res),
.resources = gn412x_gpio_res,
},
[SPEC_MFD_GN412X_FCL] = {
.name = "gn412x-fcl",
.platform_data = NULL,
.pdata_size = 0,
.num_resources = ARRAY_SIZE(gn412x_fcl_res),
.resources = gn412x_fcl_res,
},
};
/**
* Return the SPEC defult FPGA firmware name based on PCI ID
* @spec: SPEC device
*
* Return: FPGA firmware name
*/
static const char *spec_fw_name_init_get(struct spec_gn412x *spec_gn412x)
{
if (strlen(spec_fw_name) > 0)
return spec_fw_name;
switch (spec_gn412x->pdev->device) {
case PCI_DEVICE_ID_SPEC_45T:
return spec_fw_name_45t;
case PCI_DEVICE_ID_SPEC_100T:
return spec_fw_name_100t;
case PCI_DEVICE_ID_SPEC_150T:
return spec_fw_name_150t;
default:
return NULL;
}
}
/**
* Load FPGA code
* @spec: SPEC device
* @name: FPGA bitstream file name
*
* Return: 0 on success, otherwise a negative error number
*/
static int spec_fw_load(struct spec_gn412x *spec_gn412x, const char *name)
{
enum spec_fpga_select sel;
int err;
dev_dbg(&spec_gn412x->pdev->dev, "Writing firmware '%s'\n", name);
err = spec_fpga_exit(spec_gn412x);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Cannot remove FPGA device instances. Try to remove them manually and to reload this device instance\n");
return err;
}
mutex_lock(&spec_gn412x->mtx);
sel = spec_gpio_fpga_select_get(spec_gn412x);
spec_gpio_fpga_select_set(spec_gn412x, SPEC_FPGA_SELECT_GN4124_FPGA);
err = compat_spec_fw_load(spec_gn412x, name);
if (err)
goto out;
err = spec_fpga_init(spec_gn412x);
if (err)
dev_warn(&spec_gn412x->pdev->dev,
"FPGA incorrectly programmed %d\n", err);
out:
spec_gpio_fpga_select_set(spec_gn412x, sel);
mutex_unlock(&spec_gn412x->mtx);
return err;
}
static ssize_t bootselect_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
enum spec_fpga_select sel;
if (strncmp("fpga-flash", buf, 8) == 0) {
sel = SPEC_FPGA_SELECT_FPGA_FLASH;
} else if (strncmp("gn4124-fpga", buf, 8) == 0) {
sel = SPEC_FPGA_SELECT_GN4124_FPGA;
} else if (strncmp("gn4124-flash", buf, 8) == 0) {
sel = SPEC_FPGA_SELECT_GN4124_FLASH;
} else {
dev_err(dev, "Unknown bootselect option '%s'\n",
buf);
return -EINVAL;
}
mutex_lock(&spec_gn412x->mtx);
spec_gpio_fpga_select_set(spec_gn412x, sel);
mutex_unlock(&spec_gn412x->mtx);
return count;
}
static ssize_t bootselect_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
enum spec_fpga_select sel;
sel = spec_gpio_fpga_select_get(spec_gn412x);
switch (sel) {
case SPEC_FPGA_SELECT_FPGA_FLASH:
return snprintf(buf, PAGE_SIZE, "fpga-flash\n");
case SPEC_FPGA_SELECT_GN4124_FPGA:
return snprintf(buf, PAGE_SIZE, "gn4124-fpga\n");
case SPEC_FPGA_SELECT_GN4124_FLASH:
return snprintf(buf, PAGE_SIZE, "gn4124-flash\n");
default:
dev_err(dev, "Unknown bootselect option '%x'\n",
sel);
return -EINVAL;
}
}
static DEVICE_ATTR(bootselect, 0644, bootselect_show, bootselect_store);
/**
* Load golden bitstream on FGPA
*/
static ssize_t load_golden_fpga_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
int err;
err = spec_fw_load(spec_gn412x, spec_fw_name_init_get(spec_gn412x));
return err < 0 ? err : count;
}
static DEVICE_ATTR_WO(load_golden_fpga);
static struct attribute *gn412x_fpga_attrs[] = {
&dev_attr_load_golden_fpga.attr,
&dev_attr_bootselect.attr,
NULL,
};
static const struct attribute_group gn412x_fpga_group = {
.name = "fpga-options",
.attrs = gn412x_fpga_attrs,
};
static int spec_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct spec_gn412x *spec_gn412x;
int err = 0;
spec_gn412x = kzalloc(sizeof(*spec_gn412x), GFP_KERNEL);
if (!spec_gn412x)
return -ENOMEM;
mutex_init(&spec_gn412x->mtx);
pci_set_drvdata(pdev, spec_gn412x);
spec_gn412x->pdev = pdev;
err = pci_enable_device(pdev);
if (err) {
dev_err(&pdev->dev, "Failed to enable PCI device (%d)\n",
err);
goto err_enable;
}
pci_set_master(pdev);
err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
spec_mfd_devs,
ARRAY_SIZE(spec_mfd_devs),
&pdev->resource[4], pdev->irq, NULL);
if (err) {
dev_err(&spec_gn412x->pdev->dev,
"Failed to add MFD devices (%d)\n",
err);
goto err_mfd;
}
err = spec_gpio_init(spec_gn412x);
if (err) {
dev_err(&pdev->dev, "Failed to get GPIOs (%d)\n", err);
goto err_sgpio;
}
err = sysfs_create_group(&pdev->dev.kobj, &gn412x_fpga_group);
if (err)
goto err_sysfs;
spec_dbg_init(spec_gn412x);
mutex_lock(&spec_gn412x->mtx);
err = spec_fpga_init(spec_gn412x);
if (err)
dev_warn(&pdev->dev,
"FPGA incorrectly programmed or empty (%d)\n", err);
mutex_unlock(&spec_gn412x->mtx);
return 0;
err_sysfs:
spec_gpio_exit(spec_gn412x);
err_sgpio:
mfd_remove_devices(&pdev->dev);
err_mfd:
pci_disable_device(pdev);
err_enable:
kfree(spec_gn412x);
return err;
}
static void spec_remove(struct pci_dev *pdev)
{
struct spec_gn412x *spec_gn412x = pci_get_drvdata(pdev);
spec_fpga_exit(spec_gn412x);
spec_dbg_exit(spec_gn412x);
sysfs_remove_group(&pdev->dev.kobj, &gn412x_fpga_group);
spec_gpio_exit(spec_gn412x);
mfd_remove_devices(&pdev->dev);
pci_disable_device(pdev);
kfree(spec_gn412x);
}
static const struct pci_device_id spec_pci_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_45T)},
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_100T)},
{PCI_DEVICE(PCI_VENDOR_ID_CERN, PCI_DEVICE_ID_SPEC_150T)},
{0,},
};
static struct pci_driver spec_driver = {
.driver = {
.owner = THIS_MODULE,
},
.name = "spec-fmc-carrier",
.probe = spec_probe,
.remove = spec_remove,
.id_table = spec_pci_tbl,
};
module_pci_driver(spec_driver);
MODULE_AUTHOR("Federico Vaga ");
MODULE_LICENSE("GPL v2");
MODULE_VERSION(VERSION);
MODULE_DESCRIPTION("Driver for the 'Simple PCIe FMC Carrier' a.k.a. SPEC");
MODULE_DEVICE_TABLE(pci, spec_pci_tbl);
MODULE_SOFTDEP("pre: gn412x_gpio gn412x_fcl htvic spec_gn412x_dma i2c_mux i2c_ohwr spi-ocores");
ADDITIONAL_VERSIONS;
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/spec-gn412x-dma.c 0000664 0000000 0000000 00000056241 13533225622 0025032 0 ustar 00root root 0000000 0000000 /**
* Copyright (C) 2017 CERN (www.cern.ch)
* Author: Federico Vaga
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
/* Kernel functions not exported */
#if 0
/*
* Take it from the sources, like if this driver was part
* of that directory
*/
#include <../drivers/dma/dmaengine.h>
#else
/**
* dma_cookie_complete - complete a descriptor
* @tx: descriptor to complete
*
* Mark this descriptor complete by updating the channels completed
* cookie marker. Zero the descriptors cookie to prevent accidental
* repeated completions.
*
* Note: caller is expected to hold a lock to prevent concurrency.
*/
static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
{
BUG_ON(tx->cookie < DMA_MIN_COOKIE);
tx->chan->completed_cookie = tx->cookie;
tx->cookie = 0;
}
/**
* dma_cookie_init - initialize the cookies for a DMA channel
* @chan: dma channel to initialize
*/
static inline void dma_cookie_init(struct dma_chan *chan)
{
chan->cookie = DMA_MIN_COOKIE;
chan->completed_cookie = DMA_MIN_COOKIE;
}
/**
* dma_cookie_assign - assign a DMA engine cookie to the descriptor
* @tx: descriptor needing cookie
*
* Assign a unique non-zero per-channel cookie to the descriptor.
* Note: caller is expected to hold a lock to prevent concurrency.
*/
static inline dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx)
{
struct dma_chan *chan = tx->chan;
dma_cookie_t cookie;
cookie = chan->cookie + 1;
if (cookie < DMA_MIN_COOKIE)
cookie = DMA_MIN_COOKIE;
tx->cookie = chan->cookie = cookie;
return cookie;
}
/**
* dma_cookie_status - report cookie status
* @chan: dma channel
* @cookie: cookie we are interested in
* @state: dma_tx_state structure to return last/used cookies
*
* Report the status of the cookie, filling in the state structure if
* non-NULL. No locking is required.
*/
static inline enum dma_status dma_cookie_status(struct dma_chan *chan,
dma_cookie_t cookie, struct dma_tx_state *state)
{
dma_cookie_t used, complete;
used = chan->cookie;
complete = chan->completed_cookie;
if (state) {
state->last = complete;
state->used = used;
state->residue = 0;
}
return dma_async_is_complete(cookie, complete, used);
}
#endif
enum gn412x_dma_regs {
GN412X_DMA_CTRL = 0x00,
GN412X_DMA_STAT = 0x04,
GN412X_DMA_ADDR_MEM = 0x08,
GN412X_DMA_ADDR_L = 0x0C,
GN412X_DMA_ADDR_H = 0x10,
GN412X_DMA_LEN = 0x14,
GN412X_DMA_NEXT_L = 0x18,
GN412X_DMA_NEXT_H = 0x1C,
GN412X_DMA_ATTR = 0x20,
GN412X_DMA_CUR_ADDR_MEM = 0x24,
GN412X_DMA_CUR_ADDR_L = 0x28,
GN412X_DMA_CUR_ADDR_H = 0x2C,
GN412X_DMA_CUR_LEN = 0x30,
};
enum gn412x_dma_regs_ctrl {
GN412X_DMA_CTRL_START = BIT(0),
GN412X_DMA_CTRL_ABORT = BIT(1),
GN412X_DMA_CTRL_SWAPPING = 0xC,
};
enum gn412x_dma_ctrl_swapping {
GN412X_DMA_CTRL_SWAPPING_NONE = 0,
GN412X_DMA_CTRL_SWAPPING_16,
GN412X_DMA_CTRL_SWAPPING_16_WORD,
GN412X_DMA_CTRL_SWAPPING_32,
};
#define GN412X_DMA_ATTR_DIR_MEM_TO_DEV (1 << 0)
#define GN412X_DMA_ATTR_CHAIN (1 << 1)
struct gn412x_dma_tx;
/**
* List of device identifiers
*/
enum gn412x_dma_id_enum {
GN412X_DMA_GN4124_IPCORE = 0,
};
enum gn412x_dma_state {
GN412X_DMA_STAT_IDLE = 0,
GN412X_DMA_STAT_BUSY,
GN412X_DMA_STAT_ERROR,
GN412X_DMA_STAT_ABORTED,
};
#define GN412X_DMA_STAT_ACK BIT(2)
/**
* Transfer descriptor an hardware transfer
* @start_addr: pointer where start to retrieve data from device memory
* @dma_addr_l: low 32bit of the dma address on host memory
* @dma_addr_h: high 32bit of the dma address on host memory
* @dma_len: number of bytes to transfer from device to host
* @next_addr_l: low 32bit of the address of the next memory area to use
* @next_addr_h: high 32bit of the address of the next memory area to use
* @attribute: dma information about data transferm. At the moment it is used
* only to provide the "last item" bit, direction is fixed to
* device->host
*
* note: it must be a power of 2 in order to be used also as alignement
* within the DMA pool
*/
struct gn412x_dma_tx_hw {
uint32_t start_addr;
uint32_t dma_addr_l;
uint32_t dma_addr_h;
uint32_t dma_len;
uint32_t next_addr_l;
uint32_t next_addr_h;
uint32_t attribute;
uint32_t reserved; /* alignement */
};
/**
* DMA channel descriptor
* @chan: dmaengine channel
* @pending_list: list of pending transfers
* @tx_curr: current transfer
* @task: tasklet for DMA start
* @lock: protects: pending_list, tx_curr, sconfig
* @sconfig: channel configuration to be used
* @error: number of errors detected
*/
struct gn412x_dma_chan {
struct dma_chan chan;
struct list_head pending_list;
struct gn412x_dma_tx *tx_curr;
struct tasklet_struct task;
spinlock_t lock;
struct dma_slave_config sconfig;
unsigned int error;
};
static inline struct gn412x_dma_chan *to_gn412x_dma_chan(struct dma_chan *_ptr)
{
return container_of(_ptr, struct gn412x_dma_chan, chan);
}
static inline bool gn412x_dma_has_pending_tx(struct gn412x_dma_chan *gn412x_dma_chan)
{
return !list_empty(&gn412x_dma_chan->pending_list);
}
/**
* DMA device descriptor
* @pdev: platform device associated
* @addr: component base address
* @dma: dmaengine device
* @chan: list of DMA channels
* @pool: shared DMA pool for HW descriptors
* @pool_list: list of HW descriptor allocated
*/
struct gn412x_dma_device {
struct platform_device *pdev;
void __iomem *addr;
struct dma_device dma;
struct gn412x_dma_chan chan;
struct dma_pool *pool;
struct list_head *pool_list;
struct dentry *dbg_dir;
#define GN412X_DMA_DBG_REG_NAME "regs"
struct dentry *dbg_reg;
struct debugfs_regset32 dbg_reg32;
};
static inline struct gn412x_dma_device *to_gn412x_dma_device(struct dma_device *_ptr)
{
return container_of(_ptr, struct gn412x_dma_device, dma);
}
/**
* DMA transfer descriptor
* @tx: dmaengine descriptor
* @sgl_hw: scattelist HW descriptors
* @sg_len: number of entries in the scatterlist
* @list: token to indentify this transfer in the pending list
*/
struct gn412x_dma_tx {
struct dma_async_tx_descriptor tx;
struct gn412x_dma_tx_hw **sgl_hw;
unsigned int sg_len;
struct list_head list;
};
static inline struct gn412x_dma_tx *to_gn412x_dma_tx(struct dma_async_tx_descriptor *_ptr)
{
return container_of(_ptr, struct gn412x_dma_tx, tx);
}
#define REG32(_name, _offset) {.name = _name, .offset = _offset}
static const struct debugfs_reg32 gn412x_dma_debugfs_reg32[] = {
REG32("DMACTRLR", GN412X_DMA_CTRL),
REG32("DMASTATR", GN412X_DMA_STAT),
REG32("DMACSTARTR", GN412X_DMA_ADDR_MEM),
REG32("DMAHSTARTLR", GN412X_DMA_ADDR_L),
REG32("DMAHSTARTHR", GN412X_DMA_ADDR_H),
REG32("DMALENR", GN412X_DMA_LEN),
REG32("DMANEXTLR", GN412X_DMA_NEXT_L),
REG32("DMANEXTHR", GN412X_DMA_NEXT_H),
REG32("DMAATTRIBR", GN412X_DMA_ATTR),
REG32("DMACURCSTARTR", GN412X_DMA_CUR_ADDR_MEM),
REG32("DMACURHSTARTLR", GN412X_DMA_CUR_ADDR_L),
REG32("DMACURHSTARTHR", GN412X_DMA_CUR_ADDR_H),
REG32("DMACURLENR", GN412X_DMA_CUR_LEN),
};
/**
* Start DMA transfer
* @gn412x_dma: DMA device
*/
static void gn412x_dma_ctrl_start(struct gn412x_dma_device *gn412x_dma)
{
uint32_t ctrl;
ctrl = ioread32(gn412x_dma->addr + GN412X_DMA_CTRL);
ctrl |= GN412X_DMA_CTRL_START;
iowrite32(ctrl, gn412x_dma->addr + GN412X_DMA_CTRL);
dev_dbg(&gn412x_dma->pdev->dev, "%s: stat: 0x%x\n",
__func__, ioread32(gn412x_dma->addr + GN412X_DMA_STAT));
}
/**
* Abort on going DMA transfer
* @gn412x_dma: DMA device
*/
static void gn412x_dma_ctrl_abort(struct gn412x_dma_device *gn412x_dma)
{
uint32_t ctrl;
ctrl = ioread32(gn412x_dma->addr + GN412X_DMA_CTRL);
ctrl |= GN412X_DMA_CTRL_ABORT;
iowrite32(ctrl, gn412x_dma->addr + GN412X_DMA_CTRL);
}
/**
* Set swapping option
* @gn412x_dma: DMA device
* @swap: swapping option
*/
static void gn412x_dma_ctrl_swapping(struct gn412x_dma_device *gn412x_dma,
enum gn412x_dma_ctrl_swapping swap)
{
uint32_t ctrl = swap;
iowrite32(ctrl, gn412x_dma->addr + GN412X_DMA_CTRL);
}
static enum gn412x_dma_state gn412x_dma_state(struct gn412x_dma_device *gn412x_dma)
{
return ioread32(gn412x_dma->addr + GN412X_DMA_STAT);
}
static bool gn412x_dma_is_busy(struct gn412x_dma_device *gn412x_dma)
{
uint32_t status;
status = ioread32(gn412x_dma->addr + GN412X_DMA_STAT);
return status & GN412X_DMA_STAT_BUSY;
}
static bool gn412x_dma_is_abort(struct gn412x_dma_device *gn412x_dma)
{
uint32_t status;
status = ioread32(gn412x_dma->addr + GN412X_DMA_STAT);
return status & GN412X_DMA_STAT_ABORTED;
}
static void gn412x_dma_irq_ack(struct gn412x_dma_device *gn412x_dma)
{
iowrite32(GN412X_DMA_STAT_ACK, gn412x_dma->addr + GN412X_DMA_STAT);
}
static void gn412x_dma_config(struct gn412x_dma_device *gn412x_dma,
struct gn412x_dma_tx_hw *tx_hw)
{
iowrite32(tx_hw->start_addr, gn412x_dma->addr + GN412X_DMA_ADDR_MEM);
iowrite32(tx_hw->dma_addr_l, gn412x_dma->addr + GN412X_DMA_ADDR_L);
iowrite32(tx_hw->dma_addr_h, gn412x_dma->addr + GN412X_DMA_ADDR_H);
iowrite32(tx_hw->dma_len, gn412x_dma->addr + GN412X_DMA_LEN);
iowrite32(tx_hw->next_addr_l, gn412x_dma->addr + GN412X_DMA_NEXT_L);
iowrite32(tx_hw->next_addr_h, gn412x_dma->addr + GN412X_DMA_NEXT_H);
iowrite32(tx_hw->attribute, gn412x_dma->addr + GN412X_DMA_ATTR);
}
static int gn412x_dma_alloc_chan_resources(struct dma_chan *dchan)
{
struct gn412x_dma_chan *chan = to_gn412x_dma_chan(dchan);
memset(&chan->sconfig, 0, sizeof(struct dma_slave_config));
chan->sconfig.direction = DMA_DEV_TO_MEM;
return 0;
}
static void gn412x_dma_free_chan_resources(struct dma_chan *dchan)
{
}
/**
* Add a descriptor to the pending DMA transfer queue.
* This will not trigger any DMA transfer: here we just collect DMA
* transfer descriptions.
*/
static dma_cookie_t gn412x_dma_tx_submit(struct dma_async_tx_descriptor *tx)
{
struct gn412x_dma_tx *gn412x_dma_tx = to_gn412x_dma_tx(tx);
struct gn412x_dma_chan *chan = to_gn412x_dma_chan(tx->chan);
dma_cookie_t cookie;
unsigned long flags;
dev_dbg(&tx->chan->dev->device, "%s submit %p\n", __func__, tx);
spin_lock_irqsave(&chan->lock, flags);
cookie = dma_cookie_assign(tx);
list_add_tail(&gn412x_dma_tx->list, &chan->pending_list);
spin_unlock_irqrestore(&chan->lock, flags);
return cookie;
}
static void gn412x_dma_prep_fixup(struct gn412x_dma_tx_hw *tx_hw,
dma_addr_t next_addr)
{
if (!tx_hw || !next_addr)
return;
tx_hw->next_addr_l = ((next_addr >> 0) & 0xFFFFFFFF);
tx_hw->next_addr_h = ((next_addr >> 32) & 0xFFFFFFFF);
}
static void gn412x_dma_prep(struct gn412x_dma_tx_hw *tx_hw,
struct scatterlist *sg,
dma_addr_t start_addr)
{
tx_hw->start_addr = start_addr & 0xFFFFFFFF;
tx_hw->dma_addr_l = sg_dma_address(sg);
tx_hw->dma_addr_l &= 0xFFFFFFFF;
tx_hw->dma_addr_h = ((uint64_t)sg_dma_address(sg) >> 32);
tx_hw->dma_addr_h &= 0xFFFFFFFF;
tx_hw->dma_len = sg_dma_len(sg);
tx_hw->next_addr_l = 0x00000000;
tx_hw->next_addr_h = 0x00000000;
tx_hw->attribute = 0x0;
if (!sg_is_last(sg))
tx_hw->attribute = GN412X_DMA_ATTR_CHAIN;
}
static struct dma_async_tx_descriptor *gn412x_dma_prep_slave_sg(
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
enum dma_transfer_direction direction, unsigned long flags,
void *context)
{
struct gn412x_dma_device *gn412x_dma = to_gn412x_dma_device(chan->device);
struct dma_slave_config *sconfig = &to_gn412x_dma_chan(chan)->sconfig;
struct gn412x_dma_tx *gn412x_dma_tx;
struct scatterlist *sg;
dma_addr_t src_addr;
int i;
if (unlikely(direction != DMA_DEV_TO_MEM)) {
dev_err(&chan->dev->device,
"Support only DEV -> MEM transfers\n");
goto err;
}
if (unlikely(sconfig->direction != direction)) {
dev_err(&chan->dev->device,
"Transfer and slave configuration disagree on DMA direction\n");
goto err;
}
if (unlikely(!sgl || !sg_len)) {
dev_err(&chan->dev->device,
"You must provide a DMA scatterlist\n");
goto err;
}
gn412x_dma_tx = kzalloc(sizeof(struct gn412x_dma_tx), GFP_NOWAIT);
if (!gn412x_dma_tx)
goto err;
dma_async_tx_descriptor_init(&gn412x_dma_tx->tx, chan);
gn412x_dma_tx->tx.tx_submit = gn412x_dma_tx_submit;
gn412x_dma_tx->sg_len = sg_len;
/* Configure the hardware for this transfer */
gn412x_dma_tx->sgl_hw = kcalloc(sizeof(struct gn412x_dma_tx_hw *),
gn412x_dma_tx->sg_len,
GFP_KERNEL);
if (!gn412x_dma_tx->sgl_hw)
goto err_alloc_sglhw;
src_addr = sconfig->src_addr;
for_each_sg(sgl, sg, sg_len, i) {
dma_addr_t phys;
if (sg_dma_len(sg) > dma_get_max_seg_size(chan->device->dev)) {
dev_err(&chan->dev->device,
"Maximum transfer size %d, got %d on transfer %d\n",
0x3FFF, sg_dma_len(sg), i);
goto err_alloc_pool;
}
gn412x_dma_tx->sgl_hw[i] = dma_pool_alloc(gn412x_dma->pool,
GFP_DMA,
&phys);
if (!gn412x_dma_tx->sgl_hw[i])
goto err_alloc_pool;
if (i > 0) {
/*
* To build the chained transfer the previous
* descriptor (sgl_hw[i - 1]) must point to
* the physical address of current one (phys)
*/
gn412x_dma_prep_fixup(gn412x_dma_tx->sgl_hw[i - 1],
phys);
} else {
gn412x_dma_tx->tx.phys = phys;
}
gn412x_dma_prep(gn412x_dma_tx->sgl_hw[i], sg, src_addr);
src_addr += sg_dma_len(sg);
}
for_each_sg(sgl, sg, sg_len, i) {
struct gn412x_dma_tx_hw *tx_hw = gn412x_dma_tx->sgl_hw[i];
dev_dbg(&chan->dev->device,
"%s\n"
"\tsegment: %d\n"
"\tstart_addr: 0x%x\n"
"\tdma_addr_l: 0x%x\n"
"\tdma_addr_h: 0x%x\n"
"\tdma_len: 0x%x\n"
"\tnext_addr_l: 0x%x\n"
"\tnext_addr_h: 0x%x\n"
"\tattribute: 0x%x\n",
__func__, i,
tx_hw->start_addr,
tx_hw->dma_addr_l,
tx_hw->dma_addr_h,
tx_hw->dma_len,
tx_hw->next_addr_l,
tx_hw->next_addr_h,
tx_hw->attribute);
}
dev_dbg(&chan->dev->device, "%s prepared %p\n", __func__, &gn412x_dma_tx->tx);
return &gn412x_dma_tx->tx;
err_alloc_pool:
while(--i >= 0)
dma_pool_free(gn412x_dma->pool,
gn412x_dma_tx->sgl_hw[i],
gn412x_dma_tx->tx.phys);
kfree(gn412x_dma_tx->sgl_hw);
err_alloc_sglhw:
kfree(gn412x_dma_tx);
err:
return NULL;
}
static void gn412x_dma_schedule_next(struct gn412x_dma_chan *gn412x_dma_chan)
{
unsigned long flags;
bool pending;
spin_lock_irqsave(&gn412x_dma_chan->lock, flags);
pending = gn412x_dma_has_pending_tx(gn412x_dma_chan);
spin_unlock_irqrestore(&gn412x_dma_chan->lock, flags);
if (pending)
tasklet_schedule(&gn412x_dma_chan->task);
}
static void gn412x_dma_issue_pending(struct dma_chan *chan)
{
gn412x_dma_schedule_next(to_gn412x_dma_chan(chan));
}
static void gn412x_dma_start_task(unsigned long arg)
{
struct gn412x_dma_chan *chan = (struct gn412x_dma_chan *)arg;
struct gn412x_dma_device *gn412x_dma = to_gn412x_dma_device(chan->chan.device);
unsigned long flags;
if (unlikely(gn412x_dma_is_busy(gn412x_dma))) {
dev_err(&gn412x_dma->pdev->dev,
"Failed to start DMA transfer: channel busy\n");
return;
}
spin_lock_irqsave(&chan->lock, flags);
if (gn412x_dma_has_pending_tx(chan)) {
struct gn412x_dma_tx *tx;
tx = list_first_entry(&chan->pending_list,
struct gn412x_dma_tx, list);
list_del(&tx->list);
gn412x_dma_config(gn412x_dma, tx->sgl_hw[0]);
gn412x_dma_ctrl_swapping(gn412x_dma,
GN412X_DMA_CTRL_SWAPPING_NONE);
gn412x_dma_ctrl_start(gn412x_dma);
chan->tx_curr = tx;
}
spin_unlock_irqrestore(&chan->lock, flags);
}
static enum dma_status gn412x_dma_tx_status(struct dma_chan *chan,
dma_cookie_t cookie,
struct dma_tx_state *state)
{
return DMA_ERROR;
}
static int gn412x_dma_slave_config(struct dma_chan *chan,
struct dma_slave_config *sconfig)
{
struct gn412x_dma_chan *gn412x_dma_chan = to_gn412x_dma_chan(chan);
unsigned long flags;
spin_lock_irqsave(&gn412x_dma_chan->lock, flags);
memcpy(&gn412x_dma_chan->sconfig, sconfig,
sizeof(struct dma_slave_config));
spin_unlock_irqrestore(&gn412x_dma_chan->lock, flags);
return 0;
}
static int gn412x_dma_terminate_all(struct dma_chan *chan)
{
struct gn412x_dma_device *gn412x_dma = to_gn412x_dma_device(chan->device);
gn412x_dma_ctrl_abort(gn412x_dma);
/* FIXME remove all pending */
if (!gn412x_dma_is_abort(gn412x_dma)) {
dev_err(&gn412x_dma->pdev->dev,
"Failed to abort DMA transfer\n");
return -EINVAL;
}
return 0;
}
static int gn412x_dma_device_control(struct dma_chan *chan,
enum dma_ctrl_cmd cmd,
unsigned long arg)
{
switch (cmd) {
case DMA_SLAVE_CONFIG:
return gn412x_dma_slave_config(chan,
(struct dma_slave_config *)arg);
case DMA_TERMINATE_ALL:
return gn412x_dma_terminate_all(chan);
case DMA_PAUSE:
break;
case DMA_RESUME:
break;
default:
break;
}
return -ENODEV;
}
static irqreturn_t gn412x_dma_irq_handler(int irq, void *arg)
{
struct gn412x_dma_device *gn412x_dma = arg;
struct gn412x_dma_chan *chan = &gn412x_dma->chan;
struct gn412x_dma_tx *tx;
unsigned long flags;
unsigned int i;
enum gn412x_dma_state state;
/* FIXME check for spurious - need HDL fix */
gn412x_dma_irq_ack(gn412x_dma);
spin_lock_irqsave(&chan->lock, flags);
tx = chan->tx_curr;
chan->tx_curr = NULL;
spin_unlock_irqrestore(&chan->lock, flags);
state = gn412x_dma_state(gn412x_dma);
switch (state) {
case GN412X_DMA_STAT_IDLE:
dma_cookie_complete(&tx->tx);
if (tx->tx.callback)
tx->tx.callback(tx->tx.callback_param);
break;
case GN412X_DMA_STAT_ERROR:
dev_err(&gn412x_dma->pdev->dev,
"DMA transfer failed: error\n");
break;
default:
dev_err(&gn412x_dma->pdev->dev,
"DMA transfer failed: inconsitent state %d\n",
state);
break;
}
/* Clean up memory */
for (i = 0; i < tx->sg_len; ++i)
dma_pool_free(gn412x_dma->pool, tx->sgl_hw[i], tx->tx.phys);
kfree(tx->sgl_hw);
kfree(tx);
gn412x_dma_schedule_next(chan);
return IRQ_HANDLED;
}
static int gn412x_dma_dbg_init(struct gn412x_dma_device *gn412x_dma)
{
struct dentry *dir, *file;
int err;
dir = debugfs_create_dir(dev_name(&gn412x_dma->pdev->dev), NULL);
if (IS_ERR_OR_NULL(dir)) {
err = PTR_ERR(dir);
dev_warn(&gn412x_dma->pdev->dev,
"Cannot create debugfs directory \"%s\" (%d)\n",
dev_name(&gn412x_dma->pdev->dev), err);
goto err_dir;
}
gn412x_dma->dbg_reg32.regs = gn412x_dma_debugfs_reg32;
gn412x_dma->dbg_reg32.nregs = ARRAY_SIZE(gn412x_dma_debugfs_reg32);
gn412x_dma->dbg_reg32.base = gn412x_dma->addr;
file = debugfs_create_regset32(GN412X_DMA_DBG_REG_NAME, 0200,
dir, &gn412x_dma->dbg_reg32);
if (IS_ERR_OR_NULL(file)) {
err = PTR_ERR(file);
dev_warn(&gn412x_dma->pdev->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
GN412X_DMA_DBG_REG_NAME, err);
goto err_reg32;
}
gn412x_dma->dbg_dir = dir;
gn412x_dma->dbg_reg = file;
return 0;
err_reg32:
debugfs_remove_recursive(dir);
err_dir:
return err;
}
static void gn412x_dma_dbg_exit(struct gn412x_dma_device *gn412x_dma)
{
debugfs_remove_recursive(gn412x_dma->dbg_dir);
}
/**
* Configure DMA Engine configuration
*/
static int gn412x_dma_engine_init(struct gn412x_dma_device *gn412x_dma,
struct device *parent)
{
struct dma_device *dma = &gn412x_dma->dma;
dma->dev = parent;
if (dma_set_mask(dma->dev, DMA_BIT_MASK(64))) {
/* Check if hardware supports 32-bit DMA */
if (dma_set_mask(dma->dev, DMA_BIT_MASK(32))) {
dev_err(dma->dev,
"32-bit DMA addressing not available\n");
return -EINVAL;
}
}
INIT_LIST_HEAD(&dma->channels);
dma_cap_zero(dma->cap_mask);
dma_cap_set(DMA_SLAVE, dma->cap_mask);
dma_cap_set(DMA_PRIVATE, dma->cap_mask);
dma->device_alloc_chan_resources = gn412x_dma_alloc_chan_resources;
dma->device_free_chan_resources = gn412x_dma_free_chan_resources;
dma->device_prep_slave_sg = gn412x_dma_prep_slave_sg;
dma->device_control = gn412x_dma_device_control;
dma->device_tx_status = gn412x_dma_tx_status;
dma->device_issue_pending = gn412x_dma_issue_pending;
gn412x_dma->chan.chan.device = dma;
list_add_tail(&gn412x_dma->chan.chan.device_node, &dma->channels);
INIT_LIST_HEAD(&gn412x_dma->chan.pending_list);
spin_lock_init(&gn412x_dma->chan.lock);
tasklet_init(&gn412x_dma->chan.task, gn412x_dma_start_task,
(unsigned long)&gn412x_dma->chan);
dma_set_max_seg_size(dma->dev, 0x7FFF);
gn412x_dma->pool = dma_pool_create(dev_name(dma->dev), dma->dev,
sizeof(struct gn412x_dma_tx_hw),
sizeof(struct gn412x_dma_tx_hw),
0);
if (!gn412x_dma->pool)
return -ENOMEM;
return 0;
}
/**
* Release DMa engine configuration
*/
static void gn412x_dma_engine_exit(struct gn412x_dma_device *gn412x_dma)
{
dma_pool_destroy(gn412x_dma->pool);
}
/**
* It creates a new instance of the GN4124 DMA engine
* @pdev: platform device
*
* @return: 0 on success otherwise a negative error code
*/
static int gn412x_dma_probe(struct platform_device *pdev)
{
struct gn412x_dma_device *gn412x_dma;
const struct resource *r;
int err;
/* FIXME set DMA mask on pdev? */
gn412x_dma = kzalloc(sizeof(struct gn412x_dma_device), GFP_KERNEL);
if (!gn412x_dma)
return -ENOMEM;
gn412x_dma->pdev = pdev;
platform_set_drvdata(pdev, gn412x_dma);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(&pdev->dev, "Missing memory resource\n");
err = -EINVAL;
goto err_res_mem;
}
gn412x_dma->addr = ioremap(r->start, resource_size(r));
if (!gn412x_dma->addr) {
err = -EADDRNOTAVAIL;
goto err_map;
}
err = request_any_context_irq(platform_get_irq(pdev, 0),
gn412x_dma_irq_handler, 0,
dev_name(&pdev->dev), gn412x_dma);
if (err < 0)
goto err_irq;
/* Get the pci_dev device because it is the one configured for DMA */
err = gn412x_dma_engine_init(gn412x_dma, pdev->dev.parent->parent);
if (err) {
dev_err(&pdev->dev, "Can't allocate DMA pool\n");
goto err_dma_init;
}
err = dma_async_device_register(&gn412x_dma->dma);
if (err)
goto err_reg;
gn412x_dma_dbg_init(gn412x_dma);
return 0;
err_reg:
gn412x_dma_engine_exit(gn412x_dma);
err_dma_init:
free_irq(platform_get_irq(pdev, 0), gn412x_dma);
err_irq:
iounmap(gn412x_dma->addr);
err_map:
err_res_mem:
kfree(gn412x_dma);
return err;
}
/**
* It removes an instance of the GN4124 DMA engine
* @pdev: platform device
*
* @return: 0 on success otherwise a negative error code
*/
static int gn412x_dma_remove(struct platform_device *pdev)
{
struct gn412x_dma_device *gn412x_dma = platform_get_drvdata(pdev);
gn412x_dma_dbg_exit(gn412x_dma);
dmaengine_terminate_all(&gn412x_dma->chan.chan);
dma_async_device_unregister(&gn412x_dma->dma);
gn412x_dma_engine_exit(gn412x_dma);
free_irq(platform_get_irq(pdev, 0), gn412x_dma);
iounmap(gn412x_dma->addr);
kfree(gn412x_dma);
return 0;
}
/**
* List of all the compatible devices
*/
static const struct platform_device_id gn412x_dma_id[] = {
{
.name = "spec-gn412x-dma",
.driver_data = GN412X_DMA_GN4124_IPCORE,
},
{ .name = "" }, /* last */
};
struct platform_driver gn412x_dma_driver = {
.driver = {
.name = KBUILD_MODNAME,
},
.probe = gn412x_dma_probe,
.remove = gn412x_dma_remove,
.id_table = gn412x_dma_id
};
module_platform_driver(gn412x_dma_driver);
MODULE_AUTHOR("Federico Vaga ");
MODULE_DESCRIPTION("SPEC GN4124 IP-Core DMA engine");
MODULE_LICENSE("GPL");
MODULE_VERSION(VERSION);
MODULE_DEVICE_TABLE(platform, gn412x_dma_id);
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/spec.h 0000664 0000000 0000000 00000010230 13533225622 0023243 0 ustar 00root root 0000000 0000000 /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2010-2019 CERN (www.cern.ch)
* Author: Federico Vaga
* Author: Alessandro Rubini
*/
#ifndef __SPEC_H__
#define __SPEC_H__
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "gn412x.h"
#include "spec-core-fpga.h"
#define SPEC_FMC_SLOTS 1
/* On FPGA components */
#define PCI_VENDOR_ID_CERN (0x10DC)
#define PCI_DEVICE_ID_SPEC_45T (0x018D)
#define PCI_DEVICE_ID_SPEC_100T (0x01A2)
#define PCI_DEVICE_ID_SPEC_150T (0x01A3)
#define PCI_VENDOR_ID_GENNUM (0x1A39)
#define PCI_DEVICE_ID_GN4124 (0x0004)
#define GN4124_GPIO_MAX 16
#define GN4124_GPIO_BOOTSEL0 15
#define GN4124_GPIO_BOOTSEL1 14
#define GN4124_GPIO_SPRI_DIN 13
#define GN4124_GPIO_SPRI_FLASH_CS 12
#define GN4124_GPIO_IRQ0 9
#define GN4124_GPIO_IRQ1 8
#define GN4124_GPIO_SCL 5
#define GN4124_GPIO_SDA 4
/**
* @SPEC_FPGA_SELECT_FPGA_FLASH: (default) the FPGA is an SPI master that can
* access the flash (at boot it takes its
* configuration from flash)
* @SPEC_FPGA_SELECT_GN4124_FPGA: the GN4124 can configure the FPGA
* @SPEC_FPGA_SELECT_GN4124_FLASH: the GN4124 is an SPI master that can access
* the flash
*/
enum spec_fpga_select {
SPEC_FPGA_SELECT_FPGA_FLASH = 0x3,
SPEC_FPGA_SELECT_GN4124_FPGA = 0x1,
SPEC_FPGA_SELECT_GN4124_FLASH = 0x0,
};
enum {
/* Metadata */
FPGA_META_VENDOR = 0x00,
FPGA_META_DEVICE = 0x04,
FPGA_META_VERSION = 0x08,
FPGA_META_BOM = 0x0C,
FPGA_META_SRC = 0x10,
FPGA_META_CAP = 0x20,
FPGA_META_UUID = 0x30,
};
enum {
/* Metadata */
SPEC_META_BASE = SPEC_TEMPLATE_REGS_METADATA,
SPEC_META_VENDOR = SPEC_META_BASE + FPGA_META_VENDOR,
SPEC_META_DEVICE = SPEC_META_BASE + FPGA_META_DEVICE,
SPEC_META_VERSION = SPEC_META_BASE + FPGA_META_VERSION,
SPEC_META_BOM = SPEC_META_BASE + FPGA_META_BOM,
SPEC_META_SRC = SPEC_META_BASE + FPGA_META_SRC,
SPEC_META_CAP = SPEC_META_BASE + FPGA_META_CAP,
SPEC_META_UUID = SPEC_META_BASE + FPGA_META_UUID,
};
#define SPEC_META_VENDOR_ID PCI_VENDOR_ID_CERN
#define SPEC_META_DEVICE_ID 0x53504543
#define SPEC_META_BOM_LE 0xFFFE0000
#define SPEC_META_BOM_END_MASK 0xFFFF0000
#define SPEC_META_BOM_VER_MASK 0x0000FFFF
#define SPEC_META_VERSION_MASK 0xFFFF0000
#define SPEC_META_VERSION_1_4 0x01040000
/**
* struct spec_meta_id Metadata
*/
struct spec_meta_id {
uint32_t vendor;
uint32_t device;
uint32_t version;
uint32_t bom;
uint32_t src[4];
uint32_t cap;
uint32_t uuid[4];
};
/**
* struct spec_fpga - it contains data to handle the FPGA
*
* @pdev: pointer to the PCI device
* @fpga:
* @meta:
* @vic_pdev:
* @app_pdev:
* @slot_info:
* @dbg_dir_fpga:
* @dbg_csr:
* @dbg_csr_reg:
*/
struct spec_fpga {
struct device dev;
void __iomem *fpga;
struct spec_meta_id __iomem *meta;
struct platform_device *vic_pdev;
struct platform_device *dma_pdev;
struct platform_device *app_pdev;
struct fmc_slot_info slot_info;
struct dentry *dbg_dir_fpga;
#define SPEC_DBG_CSR_NAME "csr_regs"
struct dentry *dbg_csr;
struct debugfs_regset32 dbg_csr_reg;
#define SPEC_DBG_BLD_INFO_NAME "build_info"
struct dentry *dbg_bld_info;
};
/**
* struct spec_gn412x - it contains data to handle the PCB
*
* @pdev: pointer to the PCI device
* @mtx: it protects FPGA device/configuration loading
*/
struct spec_gn412x {
struct pci_dev *pdev;
struct mutex mtx;
struct gpiod_lookup_table *gpiod_table;
struct gpio_desc *gpiod[GN4124_GPIO_MAX];
struct dentry *dbg_dir;
#define SPEC_DBG_INFO_NAME "info"
struct dentry *dbg_info;
#define SPEC_DBG_FW_NAME "fpga_firmware"
struct dentry *dbg_fw;
#define SPEC_DBG_META_NAME "fpga_device_metadata"
struct dentry *dbg_meta;
struct spec_fpga *spec_fpga;
};
static inline struct spec_fpga *to_spec_fpga(struct device *_dev)
{
return container_of(_dev, struct spec_fpga, dev);
}
extern int spec_fpga_init(struct spec_gn412x *spec_gn412x);
extern int spec_fpga_exit(struct spec_gn412x *spec_gn412x);
#endif /* __SPEC_H__ */
spec-e1a905645e6e6420c2d2d19e82040d20a2315103/software/kernel/spi-ocores.c 0000664 0000000 0000000 00000040012 13533225622 0024370 0 ustar 00root root 0000000 0000000 // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "platform_data/spi-ocores.h"
#define SPI_OCORES_BUF_SIZE 4
#define SPI_OCORES_CS_MAX_N 8
/* SPI register */
#define SPI_OCORES_RX(x) (x * SPI_OCORES_BUF_SIZE)
#define SPI_OCORES_TX(x) (x * SPI_OCORES_BUF_SIZE)
#define SPI_OCORES_CTRL 0x10
#define SPI_OCORES_DIV 0x14
#define SPI_OCORES_CS 0x18
/* SPI control register fields mask */
#define SPI_OCORES_CTRL_CHAR_LEN 0x007F
#define SPI_OCORES_CTRL_GO 0x0100 /* go/busy */
#define SPI_OCORES_CTRL_BUSY 0x0100 /* go/busy */
#define SPI_OCORES_CTRL_Rx_NEG 0x0200
#define SPI_OCORES_CTRL_Tx_NEG 0x0400
#define SPI_OCORES_CTRL_LSB 0x0800
#define SPI_OCORES_CTRL_IE 0x1000
#define SPI_OCORES_CTRL_ASS 0x2000
#define SPI_OCORES_FLAG_POLL BIT(0)
struct spi_ocores {
struct spi_master *master;
unsigned long flags;
void __iomem *mem;
unsigned int clock_hz;
uint32_t ctrl_base;
/* Current transfer */
struct spi_transfer *cur_xfer;
uint32_t cur_ctrl;
uint32_t cur_divider;
const void *cur_tx_buf;
void *cur_rx_buf;
unsigned int cur_len;
void (*cur_tx_push)(struct spi_ocores *sp);
void (*cur_rx_pop)(struct spi_ocores *sp);
/* Register Access functions */
uint32_t (*read)(struct spi_ocores *sp, unsigned int reg);
void (*write)(struct spi_ocores *sp, uint32_t val, unsigned int reg);
};
enum spi_ocores_type {
TYPE_OCORES = 0,
};
static inline uint32_t spi_ocores_ioread32(struct spi_ocores *sp,
unsigned int reg)
{
return ioread32(sp->mem + reg);
}
static inline void spi_ocores_iowrite32(struct spi_ocores *sp,
uint32_t val, unsigned int reg)
{
iowrite32(val, sp->mem + reg);
}
static inline uint32_t spi_ocores_ioread32be(struct spi_ocores *sp,
unsigned int reg)
{
return ioread32be(sp->mem + reg);
}
static inline void spi_ocores_iowrite32be(struct spi_ocores *sp,
uint32_t val, unsigned int reg)
{
iowrite32be(val, sp->mem + reg);
}
static inline struct spi_ocores *spi_ocoresdev_to_sp(struct spi_device *spi)
{
return spi_master_get_devdata(spi->master);
}
/**
* Configure controller according to SPI device needs
*/
static int spi_ocores_setup(struct spi_device *spi)
{
return 0;
}
/**
* Release resources used by the SPI device
*/
static void spi_ocores_cleanup(struct spi_device *spi)
{
}
/**
* Configure controller
*/
static void spi_ocores_hw_xfer_config(struct spi_ocores *sp,
uint32_t ctrl,
uint16_t divider)
{
ctrl &= ~SPI_OCORES_CTRL_GO; /* be sure to not start */
sp->write(sp, ctrl, SPI_OCORES_CTRL);
sp->write(sp, divider, SPI_OCORES_DIV);
}
/**
* Transmit data in FIFO
*/
static void spi_ocores_hw_xfer_go(struct spi_ocores *sp)
{
uint32_t ctrl;
ctrl = sp->read(sp, SPI_OCORES_CTRL);
ctrl |= SPI_OCORES_CTRL_GO;
sp->write(sp, ctrl, SPI_OCORES_CTRL);
}
/**
* Slave Select
*/
static void spi_ocores_hw_xfer_cs(struct spi_ocores *sp,
unsigned int cs,
unsigned int val)
{
uint32_t ss;
ss = sp->read(sp, SPI_OCORES_CS);
if (val)
ss |= BIT(cs);
else
ss &= ~BIT(cs);
sp->write(sp, ss, SPI_OCORES_CS);
}
/**
* Write a TX register
*/
static void spi_ocores_tx_set(struct spi_ocores *sp,
unsigned int idx, uint32_t val)
{
if (WARN(idx > 3, "Invalid TX register index %d (min:0, max: 3)\n",
idx))
return;
sp->write(sp, val, SPI_OCORES_TX(idx));
}
/**
* Read an RX register
*/
static uint32_t spi_ocores_rx_get(struct spi_ocores *sp, unsigned int idx)
{
uint32_t val;
if (WARN(idx > 3, "Invalid RX register index %d (min:0, max: 3)\n",
idx))
return 0;
val = sp->read(sp, SPI_OCORES_RX(idx));
return val;
}
/**
* Get current bits per word
* @sp: SPI OCORE controller
*
* Return: number of bits_per_word
*/
static uint8_t spi_ocores_hw_xfer_bits_per_word(struct spi_ocores *sp)
{
uint8_t nbits;
nbits = (sp->cur_xfer && sp->cur_xfer->bits_per_word) ?
sp->cur_xfer->bits_per_word :
sp->master->cur_msg->spi->bits_per_word;
return nbits;
}
static void spi_ocores_hw_xfer_tx_push8(struct spi_ocores *sp)
{
uint32_t data;
if (!sp->cur_tx_buf)
return;
data = *((uint8_t *)sp->cur_tx_buf);
sp->cur_tx_buf += 1;
spi_ocores_tx_set(sp, 0, data);
}
static void spi_ocores_hw_xfer_tx_push16(struct spi_ocores *sp)
{
uint32_t data;
if (!sp->cur_tx_buf)
return;
data = *((uint16_t *)sp->cur_tx_buf);
sp->cur_tx_buf += 2;
spi_ocores_tx_set(sp, 0, data);
}
static void spi_ocores_hw_xfer_tx_push32(struct spi_ocores *sp)
{
uint32_t data;
if (!sp->cur_tx_buf)
return;
data = *((uint32_t *)sp->cur_tx_buf);
sp->cur_tx_buf += 4;
spi_ocores_tx_set(sp, 0, data);
}
static void spi_ocores_hw_xfer_tx_push64(struct spi_ocores *sp)
{
int i;
if (!sp->cur_tx_buf)
return;
for (i = 0; i < 2; ++i) {
uint32_t data;
data = *((uint32_t *)sp->cur_tx_buf);
sp->cur_tx_buf += 4;
spi_ocores_tx_set(sp, i, data);
}
}
static void spi_ocores_hw_xfer_tx_push128(struct spi_ocores *sp)
{
int i;
if (!sp->cur_tx_buf)
return;
for (i = 0; i < 4; ++i) {
uint32_t data;
data = *((uint32_t *)sp->cur_tx_buf);
sp->cur_tx_buf += 4;
spi_ocores_tx_set(sp, i, data);
}
}
static void spi_ocores_hw_xfer_rx_pop8(struct spi_ocores *sp)
{
uint32_t data;
if (!sp->cur_rx_buf)
return;
data = spi_ocores_rx_get(sp, 0) & 0x000000FF;
*((uint8_t *)sp->cur_rx_buf) = data;
sp->cur_rx_buf += 1;
}
static void spi_ocores_hw_xfer_rx_pop16(struct spi_ocores *sp)
{
uint32_t data;
if (!sp->cur_rx_buf)
return;
data = spi_ocores_rx_get(sp, 0) & 0x0000FFFF;
*((uint16_t *)sp->cur_rx_buf) = data;
sp->cur_rx_buf += 2;
}
static void spi_ocores_hw_xfer_rx_pop32(struct spi_ocores *sp)
{
uint32_t data;
if (!sp->cur_rx_buf)
return;
data = spi_ocores_rx_get(sp, 0) & 0xFFFFFFFF;
*((uint32_t *)sp->cur_rx_buf) = data;
sp->cur_rx_buf += 4;
}
static void spi_ocores_hw_xfer_rx_pop64(struct spi_ocores *sp)
{
int i;
if (!sp->cur_rx_buf)
return;
for (i = 0; i < 2; ++i) {
uint32_t data;
data = spi_ocores_rx_get(sp, i) & 0xFFFFFFFF;
*((uint32_t *)sp->cur_rx_buf) = data;
sp->cur_rx_buf += 4;
}
}
static void spi_ocores_hw_xfer_rx_pop128(struct spi_ocores *sp)
{
int i;
if (!sp->cur_rx_buf)
return;
for (i = 0; i < 4; ++i) {
uint32_t data;
data = spi_ocores_rx_get(sp, i) & 0xFFFFFFFF;
*((uint32_t *)sp->cur_rx_buf) = data;
sp->cur_rx_buf += 4;
}
}
static void spi_ocores_hw_xfer_start(struct spi_ocores *sp)
{
unsigned int cs = sp->master->cur_msg->spi->chip_select;
/* Optimize:
* Probably we can avoid to write CTRL DIVIDER and CS everytime
*/
spi_ocores_hw_xfer_config(sp, sp->cur_ctrl, sp->cur_divider);
spi_ocores_hw_xfer_cs(sp, cs, 1);
spi_ocores_hw_xfer_go(sp);
}
/**
* Wait until something change in a given register
* @sp: SPI OCORE controller
* @reg: register to query
* @mask: bitmask to apply on register value
* @val: expected result
* @timeout: timeout in jiffies
*
* Timeout is necessary to avoid to stay here forever when the chip
* does not answer correctly.
*
* Return: 0 on success, -ETIMEDOUT on timeout
*/
static int spi_ocores_wait(struct spi_ocores *sp,
int reg, uint32_t mask, uint32_t val,
const unsigned long timeout)
{
unsigned long j;
j = jiffies + timeout;
while (1) {
uint32_t tmp = sp->read(sp, reg);
if ((tmp & mask) == val)
break;
if (time_after(jiffies, j))
return -ETIMEDOUT;
}
return 0;
}
/**
* Wait transfer completion
* @sp: SPI OCORE controller
* @timeoute: in jiffies
*
* return: 0 on success, -ETIMEDOUT on timeout
*/
static int spi_ocores_hw_xfer_wait_complete(struct spi_ocores *sp,
const unsigned long timeout)
{
return spi_ocores_wait(sp, SPI_OCORES_CTRL,
SPI_OCORES_CTRL_BUSY, 0, timeout);
}
/**
* Finish Linux SPI transfer
* @sp: SPI OCORE controller
* @xfer: Linux SPI transfer to finish
*
* Return: 0 on success, otherwise a negative errno
*/
static int spi_ocores_sw_xfer_finish(struct spi_ocores *sp)
{
if (sp->cur_xfer->delay_usecs)
udelay(sp->cur_xfer->delay_usecs);
if (sp->cur_xfer->cs_change) {
unsigned int cs;
cs = sp->master->cur_msg->spi->chip_select;
spi_ocores_hw_xfer_cs(sp, cs, 0);
}
spi_ocores_hw_xfer_config(sp, 0, 0);
sp->cur_tx_buf = NULL;
sp->cur_rx_buf = NULL;
sp->cur_len = 0;
return 0;
}
/**
* Initialize data for next software transfer
* @sp: SPI OCORE controller
*
* Return: 0 on success,
* -ENODATA when there are no transfers left,
* -EINVAL invalid bit per word
*/
static int spi_ocores_sw_xfer_next_init(struct spi_ocores *sp)
{
struct list_head *head = &sp->master->cur_msg->transfers;
uint8_t nbits;
uint32_t hz;
nbits = spi_ocores_hw_xfer_bits_per_word(sp);
if (nbits > 128)
return -EINVAL;
if (!sp->cur_xfer) {
sp->cur_xfer = list_first_entry_or_null(head,
struct spi_transfer,
transfer_list);
} else {
if (list_is_last(&sp->cur_xfer->transfer_list, head))
return -ENODATA;
sp->cur_xfer = list_next_entry(sp->cur_xfer, transfer_list);
}
if (WARN(!sp->cur_xfer, "Invalid SPI transfer"))
return -EINVAL;
sp->cur_ctrl = sp->ctrl_base;
if(sp->master->cur_msg->spi->mode & SPI_LSB_FIRST)
sp->cur_ctrl |= SPI_OCORES_CTRL_LSB;
sp->cur_ctrl |= (nbits & SPI_OCORES_CTRL_CHAR_LEN);
if (sp->cur_xfer->speed_hz)
hz = sp->cur_xfer->speed_hz;
else
hz = sp->master->cur_msg->spi->max_speed_hz;
sp->cur_divider = (sp->clock_hz / (hz * 2)) - 1;
sp->cur_tx_buf = sp->cur_xfer->tx_buf;
sp->cur_rx_buf = sp->cur_xfer->rx_buf;
sp->cur_len = sp->cur_xfer->len;
/* set operations */
if (nbits >= 8) {
sp->cur_tx_push = spi_ocores_hw_xfer_tx_push8;
sp->cur_rx_pop = spi_ocores_hw_xfer_rx_pop8;
} else if (nbits >= 16) {
sp->cur_tx_push = spi_ocores_hw_xfer_tx_push16;
sp->cur_rx_pop = spi_ocores_hw_xfer_rx_pop16;
} else if (nbits >= 32) {
sp->cur_tx_push = spi_ocores_hw_xfer_tx_push32;
sp->cur_rx_pop = spi_ocores_hw_xfer_rx_pop32;
} else if (nbits >= 64) {
sp->cur_tx_push = spi_ocores_hw_xfer_tx_push64;
sp->cur_rx_pop = spi_ocores_hw_xfer_rx_pop64;
} else if (nbits >= 128) {
sp->cur_tx_push = spi_ocores_hw_xfer_tx_push128;
sp->cur_rx_pop = spi_ocores_hw_xfer_rx_pop128;
}
return 0;
}
/**
* Start next software transfer
* @sp: SPI OCORE controller
*
* Return: 0 on success, -ENODEV when missing transfers
*/
static int spi_ocores_sw_xfer_next_start(struct spi_ocores *sp)
{
int err;
err = spi_ocores_sw_xfer_next_init(sp);
if (err)
return err;
sp->cur_tx_push(sp);
spi_ocores_hw_xfer_start(sp);
return 0;
}
/**
* TX pending status
* @sp: SPI OCORE controller
* Return: True is there are still pending data in the current transfer
*/
static bool spi_ocores_sw_xfer_pending(struct spi_ocores *sp)
{
return sp->cur_len;
}
/**
* Process an SPI transfer
* @sp: SPI OCORE controller
*
* Return: 0 on success, -ENODATA when there is nothing to process
*/
static int spi_ocores_process(struct spi_ocores *sp)
{
uint32_t ctrl = sp->read(sp, SPI_OCORES_CTRL);
uint8_t nbits;
if (ctrl & SPI_OCORES_CTRL_BUSY)
return -ENODATA;
sp->cur_rx_pop(sp);
/*
* When we read is because a complete HW transfer is over, so we
* can safely decrease the counter of pending bytes
*/
nbits = spi_ocores_hw_xfer_bits_per_word(sp);
sp->cur_len -= (nbits / 8); /* FIXME not working for !pow2 */
if (spi_ocores_sw_xfer_pending(sp)) {
sp->cur_tx_push(sp);
spi_ocores_hw_xfer_start(sp);
} else {
int err;
spi_ocores_sw_xfer_finish(sp);
err = spi_ocores_sw_xfer_next_start(sp);
if (err) {
/* Error or no more transfers */
sp->cur_xfer = NULL;
sp->master->cur_msg->status = 0;
spi_finalize_current_message(sp->master);
}
}
return 0;
}
/**
* Process an SPI transfer
* @sp: SPI OCORE controller
* @timeout: timeout in milli-seconds
*
* Return: 0 on success, -ENODATA when there is nothing to process, -ETIMEDOUT
* when is still pending after timeout
*/
static int spi_ocores_process_poll(struct spi_ocores *sp, unsigned int timeout)
{
int err;
err = spi_ocores_hw_xfer_wait_complete(sp, msecs_to_jiffies(timeout));
if (err)
return err;
err = spi_ocores_process(sp);
if (err)
return err;
return 0;
}
static irqreturn_t spi_ocores_irq_handler(int irq, void *arg)
{
struct spi_ocores *sp = arg;
int err;
err = spi_ocores_process(sp);
if (err)
return IRQ_NONE;
return IRQ_HANDLED;
}
/**
* Transfer one SPI message
*/
static int spi_ocores_transfer_one_message(struct spi_master *master,
struct spi_message *mesg)
{
struct spi_ocores *sp = spi_master_get_devdata(master);
int err = 0;
err = spi_ocores_sw_xfer_next_start(sp);
if (sp->flags & SPI_OCORES_FLAG_POLL) {
do {
err = spi_ocores_process_poll(sp, 100);
} while (!err);
}
return 0;
}
static int spi_ocores_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct spi_ocores *sp;
struct spi_ocores_platform_data *pdata;
struct resource *r;
int err;
int irq;
int i;
master = spi_alloc_master(&pdev->dev, sizeof(*sp));
if (!master) {
dev_err(&pdev->dev, "failed to allocate spi master\n");
return -ENOMEM;
}
sp = spi_master_get_devdata(master);
platform_set_drvdata(pdev, sp);
sp->master = master;
pdata = pdev->dev.platform_data;
if (!pdata) {
err = -EINVAL;
goto err_get_pdata;
}
sp->clock_hz = pdata->clock_hz;
/* configure SPI master */
master->setup = spi_ocores_setup;
master->cleanup = spi_ocores_cleanup;
master->transfer_one_message = spi_ocores_transfer_one_message;
master->num_chipselect = SPI_OCORES_CS_MAX_N;
master->bits_per_word_mask = BIT(32 - 1);
master->mode_bits = SPI_LSB_FIRST;
if (pdata->big_endian) {
sp->read = spi_ocores_ioread32be;
sp->write = spi_ocores_iowrite32be;
} else {
sp->read = spi_ocores_ioread32;
sp->write = spi_ocores_iowrite32;
}
/* assign resources */
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
sp->mem = devm_ioremap_resource(&pdev->dev, r);
if (IS_ERR(sp->mem)) {
err = PTR_ERR(sp->mem);
goto err_get_mem;
}
irq = platform_get_irq(pdev, 0);
if (irq == -ENXIO) {
sp->flags |= SPI_OCORES_FLAG_POLL;
} else {
if (irq < 0) {
err = irq;
goto err_get_irq;
}
}
if (!(sp->flags & SPI_OCORES_FLAG_POLL)) {
sp->ctrl_base |= SPI_OCORES_CTRL_IE;
err = request_any_context_irq(irq, spi_ocores_irq_handler,
0, pdev->name, sp);
if (err < 0) {
dev_err(&pdev->dev, "Cannot claim IRQ\n");
goto err_irq;
}
}
err = spi_register_master(master);
if (err)
goto err_reg_spi;
for (i = 0; i < pdata->num_devices; ++i) {
struct spi_device *sdev;
sdev = spi_new_device(master, &pdata->devices[i]);
if (!sdev)
dev_err(&pdev->dev,
"Cannot register SPI device '%s'\n",
pdata->devices[i].modalias);
}
return 0;
err_reg_spi:
pr_info("%s:%d\n", __func__, __LINE__);
if (!(sp->flags & SPI_OCORES_FLAG_POLL))
free_irq(irq, sp);
err_irq:
err_get_irq:
pr_info("%s:%d\n", __func__, __LINE__);
devm_iounmap(&pdev->dev, sp->mem);
err_get_mem:
err_get_pdata:
pr_info("%s:%d\n", __func__, __LINE__);
spi_master_put(master);
return err;
}
static int spi_ocores_remove(struct platform_device *pdev)
{
struct spi_ocores *sp = platform_get_drvdata(pdev);
int irq = platform_get_irq(pdev, 0);
if (irq > 0)
free_irq(irq, sp);
spi_unregister_master(sp->master);
devm_iounmap(&pdev->dev, sp->mem);
platform_set_drvdata(pdev, NULL);
spi_master_put(sp->master);
return 0;
}
static const struct platform_device_id spi_ocores_id_table[] = {
{
.name = "ocores-spi",
.driver_data = TYPE_OCORES,
},
{
.name = "spi-ocores",
.driver_data = TYPE_OCORES,
},
{ .name = "" }, /* last */
};
static struct platform_driver spi_ocores_driver = {
.probe = spi_ocores_probe,
.remove = spi_ocores_remove,
.driver = {
.name = "ocores-spi",
.owner = THIS_MODULE,
},
.id_table = spi_ocores_id_table,
};
module_platform_driver(spi_ocores_driver);
MODULE_AUTHOR("Federico Vaga ");
MODULE_DESCRIPTION("SPI controller driver for OHWR General-Cores SPI Master");
MODULE_LICENSE("GPL");
MODULE_VERSION(VERSION);
MODULE_DEVICE_TABLE(platform, spi_ocores_id_table);