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Simple PCIe FMC carrier SPEC - Software
Commit 96a81d1a authored by Benoit Rat's avatar Benoit Rat
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Merge branch 'klyone-20190412-fix_copyright_licenses' into 'starting-kit-master' 

Klyone 20190412 fix copyright licenses

See merge request !1
parents e76f5ca3 25ec5c3d
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Showing with 6 additions and 4 deletions
kernel/spec-sdb-scan.c
View file @ 96a81d1a
/* /*
* Copyright (C) 2019 Seven Solutions (sevensols.com) * Copyright (C) 2019 CERN (www.cern.ch)
* Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com> * Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com>
* *
* Released according to the GNU GPL, version 2 or any later version. * Released according to the GNU GPL, version 2 or any later version.
* *
* This work is part of the White Rabbit project, a research effort led
* by CERN, the European Institute for Nuclear Research.
*/ */
#include <linux/firmware.h> #include <linux/firmware.h>
...@@ -149,9 +151,9 @@ static void fpga_dev_release(struct device *dev){} ...@@ -149,9 +151,9 @@ static void fpga_dev_release(struct device *dev){}
#define FPGA_DEVS_NIC_DEV_NIC 0 #define FPGA_DEVS_NIC_DEV_NIC 0
#define FPGA_DEVS_NIC_DEV_NIC_IRQ 1 #define FPGA_DEVS_NIC_DEV_NIC_IRQ 1
#define FPGA_DEVS_NIC_DEV_EP 1 #define FPGA_DEVS_NIC_DEV_EP 1
#define FPGA_DEVS_NIC_DEV_TXTSU 2 #define FPGA_DEVS_NIC_DEV_TXTSU 3
#define FPGA_DEVS_NIC_DEV_TXTSU_IRQ 0 #define FPGA_DEVS_NIC_DEV_TXTSU_IRQ 0
#define FPGA_DEVS_NIC_DEV_PPSG 3 #define FPGA_DEVS_NIC_DEV_PPSG 2
#define FPGA_DEVS_NIC_DEV_NUM 4 #define FPGA_DEVS_NIC_DEV_NUM 4
#define FPGA_DEVS_NIC_DEV_PDEV_NAME "spec-nic" #define FPGA_DEVS_NIC_DEV_PDEV_NAME "spec-nic"
#define FPGA_DEVS_NIC_DEV_PDEV_RELEASE_F fpga_dev_release #define FPGA_DEVS_NIC_DEV_PDEV_RELEASE_F fpga_dev_release
...@@ -177,8 +179,8 @@ static struct fpga_dev fpga_devs[] = ...@@ -177,8 +179,8 @@ static struct fpga_dev fpga_devs[] =
FPGA_DEVS_CREATE_BEGIN_DEV(FPGA_DEVS_NIC_DEV,FPGA_DEVS_NIC_DEV_NAME) FPGA_DEVS_CREATE_BEGIN_DEV(FPGA_DEVS_NIC_DEV,FPGA_DEVS_NIC_DEV_NAME)
FPGA_DEV_CREATE_SFULL(FPGA_DEVS_NIC_DEV_NIC,SDB_NIC_NAME,SDB_CERN_VENDOR,SDB_NIC_PID,FPGA_DEVS_NIC_DEV_NIC_IRQ) FPGA_DEV_CREATE_SFULL(FPGA_DEVS_NIC_DEV_NIC,SDB_NIC_NAME,SDB_CERN_VENDOR,SDB_NIC_PID,FPGA_DEVS_NIC_DEV_NIC_IRQ)
FPGA_DEV_CREATE(FPGA_DEVS_NIC_DEV_EP,SDB_EP_NAME,SDB_CERN_VENDOR,SDB_EP_PID) FPGA_DEV_CREATE(FPGA_DEVS_NIC_DEV_EP,SDB_EP_NAME,SDB_CERN_VENDOR,SDB_EP_PID)
FPGA_DEV_CREATE_SFULL(FPGA_DEVS_NIC_DEV_TXTSU,SDB_TXTSU_NAME,SDB_CERN_VENDOR,SDB_TXTSU_PID,FPGA_DEVS_NIC_DEV_TXTSU_IRQ)
FPGA_DEV_CREATE(FPGA_DEVS_NIC_DEV_PPSG,SDB_PPSG_NAME,SDB_CERN_VENDOR,SDB_PPSG_PID) FPGA_DEV_CREATE(FPGA_DEVS_NIC_DEV_PPSG,SDB_PPSG_NAME,SDB_CERN_VENDOR,SDB_PPSG_PID)
FPGA_DEV_CREATE_SFULL(FPGA_DEVS_NIC_DEV_TXTSU,SDB_TXTSU_NAME,SDB_CERN_VENDOR,SDB_TXTSU_PID,FPGA_DEVS_NIC_DEV_TXTSU_IRQ)
FPGA_DEVS_CREATE_END_DEV(FPGA_DEVS_NIC_DEV_NUM,FPGA_DEVS_NIC_DEV_PDEV_NAME,FPGA_DEVS_NIC_DEV_PDEV_RELEASE_F) FPGA_DEVS_CREATE_END_DEV(FPGA_DEVS_NIC_DEV_NUM,FPGA_DEVS_NIC_DEV_PDEV_NAME,FPGA_DEVS_NIC_DEV_PDEV_RELEASE_F)
/* DIO */ /* DIO */
FPGA_DEVS_CREATE_BEGIN_DEV(FPGA_DEVS_DIO_DEV,FPGA_DEVS_DIO_DEV_NAME) FPGA_DEVS_CREATE_BEGIN_DEV(FPGA_DEVS_DIO_DEV,FPGA_DEVS_DIO_DEV_NAME)
......
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