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-- Title          : Wishbone slave core for FMC DIO 5ch TTL Port
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-- File           : wb_slave_fmc_dio_ch5_ttl.vhd
-- Author         : auto-generated by wbgen2 from wb_slave_fmc_dio_ch5_ttl.wb
-- Created        : Mon Feb 24 02:35:48 2014
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_slave_fmc_dio_ch5_ttl.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity wb_slave_fmc_dio_5ch_ttl is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(3 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    fmc_dio_async_clk_i                      : in     std_logic;
-- Port for asynchronous (clock: fmc_dio_async_clk_i) std_logic_vector field: 'Pin directions' in reg: 'Pin direction register'
    fmc_dio_ddr_o                            : out    std_logic_vector(4 downto 0);
-- Port for asynchronous (clock: fmc_dio_async_clk_i) std_logic_vector field: 'Pin input state' in reg: 'Pin state register'
    fmc_dio_psr_i                            : in     std_logic_vector(4 downto 0);
-- Ports for asynchronous (clock: fmc_dio_async_clk_i) PASS_THROUGH field: 'Pin output value' in reg: 'Pin output register'
    fmc_dio_pdr_o                            : out    std_logic_vector(4 downto 0);
    fmc_dio_pdr_wr_o                         : out    std_logic;
-- Port for asynchronous (clock: fmc_dio_async_clk_i) std_logic_vector field: 'Pin terminations' in reg: 'Pin termination register'
    fmc_dio_term_o                           : out    std_logic_vector(4 downto 0);
-- Ports for asynchronous (clock: fmc_dio_async_clk_i) PASS_THROUGH field: 'Set output pin register' in reg: 'Set output pin register'
    fmc_dio_sopr_o                           : out    std_logic_vector(4 downto 0);
    fmc_dio_sopr_wr_o                        : out    std_logic;
-- Ports for asynchronous (clock: fmc_dio_async_clk_i) PASS_THROUGH field: 'Clear output pin register' in reg: 'Clear output pin register'
    fmc_dio_copr_o                           : out    std_logic_vector(4 downto 0);
    fmc_dio_copr_wr_o                        : out    std_logic;
-- Port for asynchronous (clock: fmc_dio_async_clk_i) BIT field: 'FMC DIO Bottom LED' in reg: 'LED signaling interface'
    fmc_dio_leds_bot_o                       : out    std_logic;
-- Port for asynchronous (clock: fmc_dio_async_clk_i) BIT field: 'FMC DIO Top LED' in reg: 'LED signaling interface'
    fmc_dio_leds_top_o                       : out    std_logic
  );
end wb_slave_fmc_dio_5ch_ttl;

architecture syn of wb_slave_fmc_dio_5ch_ttl is

signal fmc_dio_ddr_int                          : std_logic_vector(4 downto 0);
signal fmc_dio_ddr_swb                          : std_logic      ;
signal fmc_dio_ddr_swb_delay                    : std_logic      ;
signal fmc_dio_ddr_swb_s0                       : std_logic      ;
signal fmc_dio_ddr_swb_s1                       : std_logic      ;
signal fmc_dio_ddr_swb_s2                       : std_logic      ;
signal fmc_dio_psr_int                          : std_logic_vector(4 downto 0);
signal fmc_dio_psr_lwb                          : std_logic      ;
signal fmc_dio_psr_lwb_delay                    : std_logic      ;
signal fmc_dio_psr_lwb_in_progress              : std_logic      ;
signal fmc_dio_psr_lwb_s0                       : std_logic      ;
signal fmc_dio_psr_lwb_s1                       : std_logic      ;
signal fmc_dio_psr_lwb_s2                       : std_logic      ;
signal fmc_dio_pdr_wr_int                       : std_logic      ;
signal fmc_dio_pdr_wr_int_delay                 : std_logic      ;
signal fmc_dio_pdr_wr_sync0                     : std_logic      ;
signal fmc_dio_pdr_wr_sync1                     : std_logic      ;
signal fmc_dio_pdr_wr_sync2                     : std_logic      ;
signal fmc_dio_term_int                         : std_logic_vector(4 downto 0);
signal fmc_dio_term_swb                         : std_logic      ;
signal fmc_dio_term_swb_delay                   : std_logic      ;
signal fmc_dio_term_swb_s0                      : std_logic      ;
signal fmc_dio_term_swb_s1                      : std_logic      ;
signal fmc_dio_term_swb_s2                      : std_logic      ;
signal fmc_dio_sopr_wr_int                      : std_logic      ;
signal fmc_dio_sopr_wr_int_delay                : std_logic      ;
signal fmc_dio_sopr_wr_sync0                    : std_logic      ;
signal fmc_dio_sopr_wr_sync1                    : std_logic      ;
signal fmc_dio_sopr_wr_sync2                    : std_logic      ;
signal fmc_dio_copr_wr_int                      : std_logic      ;
signal fmc_dio_copr_wr_int_delay                : std_logic      ;
signal fmc_dio_copr_wr_sync0                    : std_logic      ;
signal fmc_dio_copr_wr_sync1                    : std_logic      ;
signal fmc_dio_copr_wr_sync2                    : std_logic      ;
signal fmc_dio_leds_bot_int                     : std_logic      ;
signal fmc_dio_leds_bot_sync0                   : std_logic      ;
signal fmc_dio_leds_bot_sync1                   : std_logic      ;
signal fmc_dio_leds_top_int                     : std_logic      ;
signal fmc_dio_leds_top_sync0                   : std_logic      ;
signal fmc_dio_leds_top_sync1                   : std_logic      ;
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(3 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      fmc_dio_ddr_int <= "00000";
      fmc_dio_ddr_swb <= '0';
      fmc_dio_ddr_swb_delay <= '0';
      fmc_dio_psr_lwb <= '0';
      fmc_dio_psr_lwb_delay <= '0';
      fmc_dio_psr_lwb_in_progress <= '0';
      fmc_dio_pdr_wr_int <= '0';
      fmc_dio_pdr_wr_int_delay <= '0';
      fmc_dio_term_int <= "00000";
      fmc_dio_term_swb <= '0';
      fmc_dio_term_swb_delay <= '0';
      fmc_dio_sopr_wr_int <= '0';
      fmc_dio_sopr_wr_int_delay <= '0';
      fmc_dio_copr_wr_int <= '0';
      fmc_dio_copr_wr_int_delay <= '0';
      fmc_dio_leds_bot_int <= '0';
      fmc_dio_leds_top_int <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          ack_in_progress <= '0';
        else
          fmc_dio_ddr_swb <= fmc_dio_ddr_swb_delay;
          fmc_dio_ddr_swb_delay <= '0';
          fmc_dio_psr_lwb <= fmc_dio_psr_lwb_delay;
          fmc_dio_psr_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fmc_dio_psr_lwb_in_progress = '1')) then
            rddata_reg(4 downto 0) <= fmc_dio_psr_int;
            fmc_dio_psr_lwb_in_progress <= '0';
          end if;
          fmc_dio_pdr_wr_int <= fmc_dio_pdr_wr_int_delay;
          fmc_dio_pdr_wr_int_delay <= '0';
          fmc_dio_term_swb <= fmc_dio_term_swb_delay;
          fmc_dio_term_swb_delay <= '0';
          fmc_dio_sopr_wr_int <= fmc_dio_sopr_wr_int_delay;
          fmc_dio_sopr_wr_int_delay <= '0';
          fmc_dio_copr_wr_int <= fmc_dio_copr_wr_int_delay;
          fmc_dio_copr_wr_int_delay <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(3 downto 0) is
          when "0000" => 
            if (wb_we_i = '1') then
              fmc_dio_ddr_int <= wrdata_reg(4 downto 0);
              fmc_dio_ddr_swb <= '1';
              fmc_dio_ddr_swb_delay <= '1';
            end if;
            rddata_reg(4 downto 0) <= fmc_dio_ddr_int;
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0001" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              fmc_dio_psr_lwb <= '1';
              fmc_dio_psr_lwb_delay <= '1';
              fmc_dio_psr_lwb_in_progress <= '1';
            end if;
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0010" => 
            if (wb_we_i = '1') then
              fmc_dio_pdr_wr_int <= '1';
              fmc_dio_pdr_wr_int_delay <= '1';
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0011" => 
            if (wb_we_i = '1') then
              fmc_dio_term_int <= wrdata_reg(4 downto 0);
              fmc_dio_term_swb <= '1';
              fmc_dio_term_swb_delay <= '1';
            end if;
            rddata_reg(4 downto 0) <= fmc_dio_term_int;
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0100" => 
            if (wb_we_i = '1') then
              fmc_dio_sopr_wr_int <= '1';
              fmc_dio_sopr_wr_int_delay <= '1';
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0101" => 
            if (wb_we_i = '1') then
              fmc_dio_copr_wr_int <= '1';
              fmc_dio_copr_wr_int_delay <= '1';
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "1000" => 
            if (wb_we_i = '1') then
              fmc_dio_leds_bot_int <= wrdata_reg(0);
              fmc_dio_leds_top_int <= wrdata_reg(1);
            end if;
            rddata_reg(0) <= fmc_dio_leds_bot_int;
            rddata_reg(1) <= fmc_dio_leds_top_int;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- Pin directions
-- asynchronous std_logic_vector register : Pin directions (type RW/RO, fmc_dio_async_clk_i <-> clk_sys_i)
  process (fmc_dio_async_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_dio_ddr_swb_s0 <= '0';
      fmc_dio_ddr_swb_s1 <= '0';
      fmc_dio_ddr_swb_s2 <= '0';
      fmc_dio_ddr_o <= "00000";
    elsif rising_edge(fmc_dio_async_clk_i) then
      fmc_dio_ddr_swb_s0 <= fmc_dio_ddr_swb;
      fmc_dio_ddr_swb_s1 <= fmc_dio_ddr_swb_s0;
      fmc_dio_ddr_swb_s2 <= fmc_dio_ddr_swb_s1;
      if ((fmc_dio_ddr_swb_s2 = '0') and (fmc_dio_ddr_swb_s1 = '1')) then
        fmc_dio_ddr_o <= fmc_dio_ddr_int;
      end if;
    end if;
  end process;
  
  
-- Pin input state
-- asynchronous std_logic_vector register : Pin input state (type RO/WO, fmc_dio_async_clk_i <-> clk_sys_i)
  process (fmc_dio_async_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_dio_psr_lwb_s0 <= '0';
      fmc_dio_psr_lwb_s1 <= '0';
      fmc_dio_psr_lwb_s2 <= '0';
      fmc_dio_psr_int <= "00000";
    elsif rising_edge(fmc_dio_async_clk_i) then
      fmc_dio_psr_lwb_s0 <= fmc_dio_psr_lwb;
      fmc_dio_psr_lwb_s1 <= fmc_dio_psr_lwb_s0;
      fmc_dio_psr_lwb_s2 <= fmc_dio_psr_lwb_s1;
      if ((fmc_dio_psr_lwb_s1 = '1') and (fmc_dio_psr_lwb_s2 = '0')) then
        fmc_dio_psr_int <= fmc_dio_psr_i;
      end if;
    end if;
  end process;
  
  
-- Pin output value
-- pass-through field: Pin output value in register: Pin output register
  fmc_dio_pdr_o <= wrdata_reg(4 downto 0);
  process (fmc_dio_async_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_dio_pdr_wr_sync0 <= '0';
      fmc_dio_pdr_wr_sync1 <= '0';
      fmc_dio_pdr_wr_sync2 <= '0';
    elsif rising_edge(fmc_dio_async_clk_i) then
      fmc_dio_pdr_wr_sync0 <= fmc_dio_pdr_wr_int;
      fmc_dio_pdr_wr_sync1 <= fmc_dio_pdr_wr_sync0;
      fmc_dio_pdr_wr_sync2 <= fmc_dio_pdr_wr_sync1;
      fmc_dio_pdr_wr_o <= fmc_dio_pdr_wr_sync1 and (not fmc_dio_pdr_wr_sync2);
    end if;
  end process;
  
  
-- Pin terminations
-- asynchronous std_logic_vector register : Pin terminations (type RW/RO, fmc_dio_async_clk_i <-> clk_sys_i)
  process (fmc_dio_async_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_dio_term_swb_s0 <= '0';
      fmc_dio_term_swb_s1 <= '0';
      fmc_dio_term_swb_s2 <= '0';
      fmc_dio_term_o <= "00000";
    elsif rising_edge(fmc_dio_async_clk_i) then
      fmc_dio_term_swb_s0 <= fmc_dio_term_swb;
      fmc_dio_term_swb_s1 <= fmc_dio_term_swb_s0;
      fmc_dio_term_swb_s2 <= fmc_dio_term_swb_s1;
      if ((fmc_dio_term_swb_s2 = '0') and (fmc_dio_term_swb_s1 = '1')) then
        fmc_dio_term_o <= fmc_dio_term_int;
      end if;
    end if;
  end process;
  
  
-- Set output pin register
-- pass-through field: Set output pin register in register: Set output pin register
  fmc_dio_sopr_o <= wrdata_reg(4 downto 0);
  process (fmc_dio_async_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_dio_sopr_wr_sync0 <= '0';
      fmc_dio_sopr_wr_sync1 <= '0';
      fmc_dio_sopr_wr_sync2 <= '0';
    elsif rising_edge(fmc_dio_async_clk_i) then
      fmc_dio_sopr_wr_sync0 <= fmc_dio_sopr_wr_int;
      fmc_dio_sopr_wr_sync1 <= fmc_dio_sopr_wr_sync0;
      fmc_dio_sopr_wr_sync2 <= fmc_dio_sopr_wr_sync1;
      fmc_dio_sopr_wr_o <= fmc_dio_sopr_wr_sync1 and (not fmc_dio_sopr_wr_sync2);
    end if;
  end process;
  
  
-- Clear output pin register
-- pass-through field: Clear output pin register in register: Clear output pin register
  fmc_dio_copr_o <= wrdata_reg(4 downto 0);
  process (fmc_dio_async_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_dio_copr_wr_sync0 <= '0';
      fmc_dio_copr_wr_sync1 <= '0';
      fmc_dio_copr_wr_sync2 <= '0';
    elsif rising_edge(fmc_dio_async_clk_i) then
      fmc_dio_copr_wr_sync0 <= fmc_dio_copr_wr_int;
      fmc_dio_copr_wr_sync1 <= fmc_dio_copr_wr_sync0;
      fmc_dio_copr_wr_sync2 <= fmc_dio_copr_wr_sync1;
      fmc_dio_copr_wr_o <= fmc_dio_copr_wr_sync1 and (not fmc_dio_copr_wr_sync2);
    end if;
  end process;
  
  
-- FMC DIO Bottom LED
-- synchronizer chain for field : FMC DIO Bottom LED (type RW/RO, clk_sys_i <-> fmc_dio_async_clk_i)
  process (fmc_dio_async_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_dio_leds_bot_o <= '0';
      fmc_dio_leds_bot_sync0 <= '0';
      fmc_dio_leds_bot_sync1 <= '0';
    elsif rising_edge(fmc_dio_async_clk_i) then
      fmc_dio_leds_bot_sync0 <= fmc_dio_leds_bot_int;
      fmc_dio_leds_bot_sync1 <= fmc_dio_leds_bot_sync0;
      fmc_dio_leds_bot_o <= fmc_dio_leds_bot_sync1;
    end if;
  end process;
  
  
-- FMC DIO Top LED
-- synchronizer chain for field : FMC DIO Top LED (type RW/RO, clk_sys_i <-> fmc_dio_async_clk_i)
  process (fmc_dio_async_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_dio_leds_top_o <= '0';
      fmc_dio_leds_top_sync0 <= '0';
      fmc_dio_leds_top_sync1 <= '0';
    elsif rising_edge(fmc_dio_async_clk_i) then
      fmc_dio_leds_top_sync0 <= fmc_dio_leds_top_int;
      fmc_dio_leds_top_sync1 <= fmc_dio_leds_top_sync0;
      fmc_dio_leds_top_o <= fmc_dio_leds_top_sync1;
    end if;
  end process;
  
  
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
