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-- Title          : Wishbone slave core for SPEC User Interface
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-- File           : spec_user_interface.vhd
-- Author         : auto-generated by wbgen2 from spec_user_interface.wb
-- Created        : Mon Feb 24 01:47:14 2014
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spec_user_interface.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity wb_slave_spec_user is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(0 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    spec_user_clk_i                          : in     std_logic;
-- Port for asynchronous (clock: spec_user_clk_i) std_logic_vector field: 'PCB Version' in reg: 'Control register'
    spec_user_ctrl_ver_i                     : in     std_logic_vector(3 downto 0);
-- Port for asynchronous (clock: spec_user_clk_i) BIT field: 'Front panel green LED' in reg: 'Control register'
    spec_user_ctrl_led_green_o               : out    std_logic;
-- Port for asynchronous (clock: spec_user_clk_i) BIT field: 'Front panel red LED' in reg: 'Control register'
    spec_user_ctrl_led_red_o                 : out    std_logic;
-- Port for asynchronous (clock: spec_user_clk_i) BIT field: 'User Push-button 1' in reg: 'Auxiliar interface'
    spec_user_aux_button1_i                  : in     std_logic;
-- Port for asynchronous (clock: spec_user_clk_i) BIT field: 'User Push-button 2' in reg: 'Auxiliar interface'
    spec_user_aux_button2_i                  : in     std_logic;
-- Port for asynchronous (clock: spec_user_clk_i) std_logic_vector field: 'User Leds' in reg: 'Auxiliar interface'
    spec_user_aux_leds_o                     : out    std_logic_vector(3 downto 0)
  );
end wb_slave_spec_user;

architecture syn of wb_slave_spec_user is

signal spec_user_ctrl_ver_int                   : std_logic_vector(3 downto 0);
signal spec_user_ctrl_ver_lwb                   : std_logic      ;
signal spec_user_ctrl_ver_lwb_delay             : std_logic      ;
signal spec_user_ctrl_ver_lwb_in_progress       : std_logic      ;
signal spec_user_ctrl_ver_lwb_s0                : std_logic      ;
signal spec_user_ctrl_ver_lwb_s1                : std_logic      ;
signal spec_user_ctrl_ver_lwb_s2                : std_logic      ;
signal spec_user_ctrl_led_green_int             : std_logic      ;
signal spec_user_ctrl_led_green_sync0           : std_logic      ;
signal spec_user_ctrl_led_green_sync1           : std_logic      ;
signal spec_user_ctrl_led_red_int               : std_logic      ;
signal spec_user_ctrl_led_red_sync0             : std_logic      ;
signal spec_user_ctrl_led_red_sync1             : std_logic      ;
signal spec_user_aux_button1_sync0              : std_logic      ;
signal spec_user_aux_button1_sync1              : std_logic      ;
signal spec_user_aux_button2_sync0              : std_logic      ;
signal spec_user_aux_button2_sync1              : std_logic      ;
signal spec_user_aux_leds_int                   : std_logic_vector(3 downto 0);
signal spec_user_aux_leds_swb                   : std_logic      ;
signal spec_user_aux_leds_swb_delay             : std_logic      ;
signal spec_user_aux_leds_swb_s0                : std_logic      ;
signal spec_user_aux_leds_swb_s1                : std_logic      ;
signal spec_user_aux_leds_swb_s2                : std_logic      ;
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(0 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      spec_user_ctrl_ver_lwb <= '0';
      spec_user_ctrl_ver_lwb_delay <= '0';
      spec_user_ctrl_ver_lwb_in_progress <= '0';
      spec_user_ctrl_led_green_int <= '0';
      spec_user_ctrl_led_red_int <= '0';
      spec_user_aux_leds_int <= "0000";
      spec_user_aux_leds_swb <= '0';
      spec_user_aux_leds_swb_delay <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          ack_in_progress <= '0';
        else
          spec_user_ctrl_ver_lwb <= spec_user_ctrl_ver_lwb_delay;
          spec_user_ctrl_ver_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (spec_user_ctrl_ver_lwb_in_progress = '1')) then
            rddata_reg(3 downto 0) <= spec_user_ctrl_ver_int;
            spec_user_ctrl_ver_lwb_in_progress <= '0';
          end if;
          spec_user_aux_leds_swb <= spec_user_aux_leds_swb_delay;
          spec_user_aux_leds_swb_delay <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(0) is
          when '0' => 
            if (wb_we_i = '1') then
              spec_user_ctrl_led_green_int <= wrdata_reg(4);
              spec_user_ctrl_led_red_int <= wrdata_reg(5);
            end if;
            if (wb_we_i = '0') then
              spec_user_ctrl_ver_lwb <= '1';
              spec_user_ctrl_ver_lwb_delay <= '1';
              spec_user_ctrl_ver_lwb_in_progress <= '1';
            end if;
            rddata_reg(4) <= spec_user_ctrl_led_green_int;
            rddata_reg(5) <= spec_user_ctrl_led_red_int;
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when '1' => 
            if (wb_we_i = '1') then
              spec_user_aux_leds_int <= wrdata_reg(5 downto 2);
              spec_user_aux_leds_swb <= '1';
              spec_user_aux_leds_swb_delay <= '1';
            end if;
            rddata_reg(0) <= spec_user_aux_button1_sync1;
            rddata_reg(1) <= spec_user_aux_button2_sync1;
            rddata_reg(5 downto 2) <= spec_user_aux_leds_int;
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- PCB Version
-- asynchronous std_logic_vector register : PCB Version (type RO/WO, spec_user_clk_i <-> clk_sys_i)
  process (spec_user_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      spec_user_ctrl_ver_lwb_s0 <= '0';
      spec_user_ctrl_ver_lwb_s1 <= '0';
      spec_user_ctrl_ver_lwb_s2 <= '0';
      spec_user_ctrl_ver_int <= "0000";
    elsif rising_edge(spec_user_clk_i) then
      spec_user_ctrl_ver_lwb_s0 <= spec_user_ctrl_ver_lwb;
      spec_user_ctrl_ver_lwb_s1 <= spec_user_ctrl_ver_lwb_s0;
      spec_user_ctrl_ver_lwb_s2 <= spec_user_ctrl_ver_lwb_s1;
      if ((spec_user_ctrl_ver_lwb_s1 = '1') and (spec_user_ctrl_ver_lwb_s2 = '0')) then
        spec_user_ctrl_ver_int <= spec_user_ctrl_ver_i;
      end if;
    end if;
  end process;
  
  
-- Front panel green LED
-- synchronizer chain for field : Front panel green LED (type RW/RO, clk_sys_i <-> spec_user_clk_i)
  process (spec_user_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      spec_user_ctrl_led_green_o <= '0';
      spec_user_ctrl_led_green_sync0 <= '0';
      spec_user_ctrl_led_green_sync1 <= '0';
    elsif rising_edge(spec_user_clk_i) then
      spec_user_ctrl_led_green_sync0 <= spec_user_ctrl_led_green_int;
      spec_user_ctrl_led_green_sync1 <= spec_user_ctrl_led_green_sync0;
      spec_user_ctrl_led_green_o <= spec_user_ctrl_led_green_sync1;
    end if;
  end process;
  
  
-- Front panel red LED
-- synchronizer chain for field : Front panel red LED (type RW/RO, clk_sys_i <-> spec_user_clk_i)
  process (spec_user_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      spec_user_ctrl_led_red_o <= '0';
      spec_user_ctrl_led_red_sync0 <= '0';
      spec_user_ctrl_led_red_sync1 <= '0';
    elsif rising_edge(spec_user_clk_i) then
      spec_user_ctrl_led_red_sync0 <= spec_user_ctrl_led_red_int;
      spec_user_ctrl_led_red_sync1 <= spec_user_ctrl_led_red_sync0;
      spec_user_ctrl_led_red_o <= spec_user_ctrl_led_red_sync1;
    end if;
  end process;
  
  
-- User Push-button 1
-- synchronizer chain for field : User Push-button 1 (type RO/WO, spec_user_clk_i -> clk_sys_i)
  process (spec_user_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      spec_user_aux_button1_sync0 <= '0';
      spec_user_aux_button1_sync1 <= '0';
    elsif rising_edge(spec_user_clk_i) then
      spec_user_aux_button1_sync0 <= spec_user_aux_button1_i;
      spec_user_aux_button1_sync1 <= spec_user_aux_button1_sync0;
    end if;
  end process;
  
  
-- User Push-button 2
-- synchronizer chain for field : User Push-button 2 (type RO/WO, spec_user_clk_i -> clk_sys_i)
  process (spec_user_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      spec_user_aux_button2_sync0 <= '0';
      spec_user_aux_button2_sync1 <= '0';
    elsif rising_edge(spec_user_clk_i) then
      spec_user_aux_button2_sync0 <= spec_user_aux_button2_i;
      spec_user_aux_button2_sync1 <= spec_user_aux_button2_sync0;
    end if;
  end process;
  
  
-- User Leds
-- asynchronous std_logic_vector register : User Leds (type RW/RO, spec_user_clk_i <-> clk_sys_i)
  process (spec_user_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      spec_user_aux_leds_swb_s0 <= '0';
      spec_user_aux_leds_swb_s1 <= '0';
      spec_user_aux_leds_swb_s2 <= '0';
      spec_user_aux_leds_o <= "0000";
    elsif rising_edge(spec_user_clk_i) then
      spec_user_aux_leds_swb_s0 <= spec_user_aux_leds_swb;
      spec_user_aux_leds_swb_s1 <= spec_user_aux_leds_swb_s0;
      spec_user_aux_leds_swb_s2 <= spec_user_aux_leds_swb_s1;
      if ((spec_user_aux_leds_swb_s2 = '0') and (spec_user_aux_leds_swb_s1 = '1')) then
        spec_user_aux_leds_o <= spec_user_aux_leds_int;
      end if;
    end if;
  end process;
  
  
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
