RHINO
Reconfigurable Hardware Interface for Computing and Radio*
Version 1.1 of the Rhino Platform running Linux 3.1 RC 1 with Borph
Project Description
The RHINO Project is an Open Source effort born out of the radar remote sensing group at the University of Cape Town in South Africa, motivated by CASPER and the SKA Africa project. The goal of the project is to provide a hardware platform and software toolchain for Software Defined Radio (SDR) which is both easy to use, easy to learn and affordable to a broad audience. It is hoped that this effort will consolidate and enhance the teaching and research resources available for Software Defined Radio (SDR).
Hardware Architecture
RHINO Hardware follows the same fundamental computer architecture as the
current ROACH-based CASPER hardware,
namely a single FPGA element with memory, high speed communication, and
IO expansion slots, all controlled via a processor running the BORPH
operating system. Below is an overview of the RHINO
architecture.
Key Features
- FPGA Subsystem
- Spartan6 FPGA, XC6SLX150T-2FGG676C
- 676-pin package, 150K logic cells, 180 DSP48A1 slices, 8 GTP transceivers, 4 integrated DDR3 Memory Controllers
- Dual DDR3 x 16 memory
- Micron DDR3-1066, upto 512MB, upto 25.6Gbps total bandwidth
- Dual FMC-LPC Vita 57.1 IO expansion
- Dual CX4 10Gbps IO
- Supports 10Ge,Infiniband, XUAI, copper-to-fibre adaptors
- Spartan6 FPGA, XC6SLX150T-2FGG676C
- Processor Subsystem
- Texas Instrument Sitara AM3517ZCN ARM Cortex A8 processor (600MHz)
- Dual DDR2 upto 256MB, 10Gbps bandwdith
- Upto 256MB NAND flash memory
- USB Host, USB on the go, SD Card, HDMI, Audio (in/out)
- Support booting off USB drive, flash memory or SD card
- JTAG openocd debugger support through FDTI device
- Dual serial port via USB
- 100Mbs Ethernet with IEEE 1588 PTP support (sync to within 10ns)
- FPGA/Processor Link
- 16 bit bus, upto 1.3 Gbps
- Select Map Configuration( device configuration within 1s)
- Support FPGA ICAP interface via processor bus
Detailed Project Information
(Need to add Requirements Specification)
Layout
We needed a 16 layer stack-up to accomodate all the high speed signals;
it is quite tough length and impedance matching most of the signals from
the FPGA. Altium
Status
Date | Event |
---|---|
01-02-2010 | Start of Rhino Project |
01-03-2010 | High Level Design Complete, Block Diagram's released for review |
01-06-2010 | First Draft of Schematics Complete |
15-06-2010 | Second Draft of Schematics Released fro Review |
01-07-2010 | Components Database complete |
01-08-2010 | Layout Begins |
01-09-2010 | Initial Placement complete and ready for review |
010-11-2010 | Layout complete and ready for review Layout |
15-12-2010 | Proposed date for receiving first Rhino prototypes |
22-12-2010 | First 4 Rhino prototypes received |
27-12-2010 | Processor is booting from SD Flash; we have a uboot prompt |
5-01-2011 | FPGA up and running |
10-01-2011 | Both DDR3 memories up and running! |
10-02-2011 | Almost all peripherals have been tested |
29-03-2011 | Borph/Linux is ported |
10-04-2011 | CAD files updated to Version 1.1 - fixed all the minor bugs |
30-04-2011 | 6 new Rhino V1.1 PCB's fab'd and sent to Digicom |
15-05-2011 | 2 new Rhino V1.1 fab'd |
15-06-2011 | Simon gets S/N 1100001 working and solves weird boot up issue (beware of 4mil spacing!) |
15-07-2011 | Receive and set to work 3 more Rhino's, one sent back to Digicom for some repair. |
30-07-2011 | Linux ecosystem gathering tools at www.borph.org |
16-08-2011 | Brandon updates Borph to Linux 3.1 RC 1! |
Where to get it
Production is managed by Mo at Digicom (www.digicom.org). Send production-related inquiries to mo at digicom dot org. Production is grouped into batches, so lead times are variable.