User Documentation - 2016-04-06 11:31:05.480023
All the images on the wiki
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FCILayout-big.png - Big image of the FCI connectors layout
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FCILayout-small.png - Small image of the FCI connectors layout
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AnalInpLayout-big.png - Big image of the analog inputs layout
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ClkSplitterLayout-big.png - Big image of the clock splitter layout
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ClkSplitterLayout-small.png - Small image of the clock splitter layout
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boardLayout3D-small.png - Small image of the 3D PCB
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boardLayout3D-big.png - Big image of the 3D PCB
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boardLayout3DBottom-big.png - Big image of the bottom of the 3D PCB
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BoardSpec-small.png - Small image of the PCB specs
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BoardSpec-big.png - Big image of the PCB specs
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apod.png - Effect of windowing
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result_1.png - Results of the interpolation algorithm simulation
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result_2.png - Results of the fitting algorithm simulation
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zerro1.png - Sine without zero padding
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zerro2.png - Sine with zero padding
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ADCLayout-big.png - Big image ADC layout
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AnalInpLayout-small.png - Small image of the analog inputs layout
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PowerSupplyLayout-big.png - Big image of the power supply layout
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PowerSupplyLayout-small.png - Small image of the power supply layout
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PCBLayout-big.png - Big image of the PCB layout
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ADCLayout-small.png - Small image of the ADC layout
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adc_board_3D_bot_big.png - Big image ADC Board 3D model bottom
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adc_board_3D_bot_small.png - Small image ADC Board 3D model bottom
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adc_board_3D_top_big.png - Big image ADC Board 3D model top
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adc_board_3D_top_small.png - Small image ADC Board 3D model top
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filterBoardZoom-small.png - Small image of the filter prototyping board
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filterBoard_big.png - Big image of the filter prototyping board
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fitting_big.png - big figure of the fitting on the samples
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topo.png - Small schematics of the experimental setup
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PCBLayout-small.png - Small image of the PCB layout
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PowerSupplySepLayout-small.png - Small image of the power separation
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PowerSupplySepLayout-big.png - Big image of the power separation
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explanations.png - Small explanations picture
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plot_model.png - Plot of the model example for the pulse shape
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fitting.PNG - Fitting algorithm
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interpolation.PNG - Interpolation algorithm
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MicrozedTopo.PNG - Topology for the MicroZed Design
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filterBoard_big.png - Big image of the filter prototyping board
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filterBoard_small.png - Small image of the filter prototyping board
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bitslip.PNG - Figure coming from the AD9253 datasheet
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ADCoutput.PNG - Figure coming from the AD9253 datasheet
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pulseBeginning.PNG - Picture of the distortion at the beginning of the pulse
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gauss.png - Results of the delay measurements
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fitting.png - Small figure of the fitting on the samples
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filter.png - small figure of the filter schematics
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filter3.PNG - Other example of filter 2
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pulse.PNG - Pulse shape
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transfer.PNG - Transfer function of an LC tank filter with serial resistor
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model.PNG - Model example for the pulse shape
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pulsezoom.PNG - Zoom on the pulse shape
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enob_without_filter.PNG - SINAD measurement without the filter
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enob_with_filter.PNG - SINAD measurement with a filter
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filter2.PNG - Other example of filter 1
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FCI-Small.jpg - Small image of the MicroZed connectors schematics
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PowerSupply-big.jpg - Big image of the Power Supply schematics
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PowerSupply-small.jpg - Small image of the Power Supply schematics
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WholeBoard-big.jpg - Big image of the Whole Board schematics
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ADC1-big.jpg - Big image of the ADC1 schematics
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ADC2-big.jpg - Big image of the ADC2 schematics
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ClockSplitter-big.jpg - Big image of the Clock Splitter schematics
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ClockSplitter-small.jpg - Small image of the Clock Splitter schematics
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WholeBoard-small.jpg - Small image of the Whole Board schematics
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FCI-big.jpg - Big image of the MicroZed connectors schematics
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ADC1-small.jpg - Small image of the ADC1 schematics
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adcBoard_top_big.jpg - Big image of the top of the ADC board
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adcBoard_bot_big.jpg - Big image of the bottom of the ADC board
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adcBoard_top_small.jpg - Small image of the top of the ADC Board
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adcBoard_bot_small.jpg - Small image of the bottom of the ADC Board
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adcBoard_expl.jpg - explanations of the ADC board
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connections1_small.jpg - Small image of the connections 1 part of the schematics
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connections2_big.jpg - Big image of the connections 2 part of the schematics
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connections2_small.jpg - Small image of the connections 2 part of the schematics
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input_big.jpg - Big image of one of the inputs in the schematics
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adc_big.jpg - Big image of the ADC part of the schematics
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adc_small.jpg - Small image of the ADC part of the schematics
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clock_big.jpg - Big image of the clock part of the schematics
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clock_small.jpg - Small image of the clock part of the schematics
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input_small.jpg - Small image of one of the inputs in the schematics
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connections1_big.jpg - Big image of the connections 1 part of the schematics
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misc_big.jpg - Big image of the miscellaneous part of the schematics
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misc_small.jpg - Small image of the miscellaneous part of the schematics
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top_big.jpg - Big image of the top of the schematics
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top_small.jpg - Small image of the top of the schematics
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power1_big.jpg - Big image of the power supply part 1 of the schematics
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power1_small.jpg - Small image of the power supply part 1 of the schematics
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power2_big.jpg - Big image of the power supply part 2 of the schematics
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power2_small.jpg - Small image of the power supply part 2 of the schematics
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gateware_topo.jpg - Gateware topology
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trigger.jpg - Trigger explanation
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topo_small.jpg - Small picture of the TDC experimental setup