Commit f980ad4e authored by Nicolas Boucquey's avatar Nicolas Boucquey

Gateware and software added

parent ad063dfb
*.*\#
\#*
.\#*
*.*~
work
*.wlf
*.vstf
*.patch
modelsim.ini
*.html
*.h
*.o
*.bin
*.elf
\ No newline at end of file
[submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
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-- This VHDL was converted from Verilog using the
-- Icarus Verilog VHDL Code Generator 0.9.7 (v0_9_7)
library ieee;
use ieee.std_logic_1164.all;
use work.axi4_pkg.all;
entity xprocessing_system_zedboard is
port (
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_CAS_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_DRSTB : inout std_logic;
DDR_ODT : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
DDR_WEB : inout std_logic;
FCLK_CLK0 : out std_logic;
FCLK_RESET0_N : out std_logic;
MIO : inout std_logic_vector(53 downto 0);
m_axi_gp0_aclk_i : in std_logic;
m_axi_gp0_o : out t_axi4_lite_master_out_32;
m_axi_gp0_i : in t_axi4_lite_master_in_32;
PS_CLK : inout std_logic;
PS_PORB : inout std_logic;
PS_SRSTB : inout std_logic;
TTC0_WAVE0_OUT : out std_logic;
TTC0_WAVE1_OUT : out std_logic;
TTC0_WAVE2_OUT : out std_logic;
USB0_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB0_VBUS_PWRFAULT : in std_logic;
USB0_VBUS_PWRSELECT : out std_logic);
end entity xprocessing_system_zedboard;
architecture wrapper of xprocessing_system_zedboard is
component processing_system_zedboard is
port (
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_CAS_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_DRSTB : inout std_logic;
DDR_ODT : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
DDR_WEB : inout std_logic;
FCLK_CLK0 : out std_logic;
FCLK_RESET0_N : out std_logic;
MIO : inout std_logic_vector(53 downto 0);
M_AXI_GP0_ACLK : in std_logic;
M_AXI_GP0_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP0_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARREADY : in std_logic;
M_AXI_GP0_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARVALID : out std_logic;
M_AXI_GP0_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP0_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWREADY : in std_logic;
M_AXI_GP0_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWVALID : out std_logic;
M_AXI_GP0_BID : in std_logic_vector(11 downto 0);
M_AXI_GP0_BREADY : out std_logic;
M_AXI_GP0_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_BVALID : in std_logic;
M_AXI_GP0_RDATA : in std_logic_vector(31 downto 0);
M_AXI_GP0_RID : in std_logic_vector(11 downto 0);
M_AXI_GP0_RLAST : in std_logic;
M_AXI_GP0_RREADY : out std_logic;
M_AXI_GP0_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RVALID : in std_logic;
M_AXI_GP0_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP0_WID : out std_logic_vector(11 downto 0);
M_AXI_GP0_WLAST : out std_logic;
M_AXI_GP0_WREADY : in std_logic;
M_AXI_GP0_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP0_WVALID : out std_logic;
PS_CLK : inout std_logic;
PS_PORB : inout std_logic;
PS_SRSTB : inout std_logic;
TTC0_WAVE0_OUT : out std_logic;
TTC0_WAVE1_OUT : out std_logic;
TTC0_WAVE2_OUT : out std_logic;
USB0_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB0_VBUS_PWRFAULT : in std_logic;
USB0_VBUS_PWRSELECT : out std_logic);
end component processing_system_zedboard;
signal arid, awid, BID, RID : std_logic_vector(11 downto 0);
signal ARVALID, AWVALID : std_logic;
begin
U_Wrapped_PS : processing_system_zedboard
port map (
DDR_Addr => DDR_Addr,
DDR_BankAddr => DDR_BankAddr,
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS => DDR_DQS,
DDR_DQS_n => DDR_DQS_n,
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
FCLK_CLK0 => FCLK_CLK0,
FCLK_RESET0_N => FCLK_RESET0_N,
MIO => MIO,
M_AXI_GP0_ACLK => m_axi_gp0_aclk_i,
M_AXI_GP0_ARADDR => m_axi_gp0_o.ARADDR,
M_AXI_GP0_ARBURST => open,
M_AXI_GP0_ARCACHE => open,
M_AXI_GP0_ARID => ARID,
M_AXI_GP0_ARLEN => open,
M_AXI_GP0_ARLOCK => open,
M_AXI_GP0_ARPROT => open,
M_AXI_GP0_ARQOS => open,
M_AXI_GP0_ARREADY => m_axi_gp0_i.ARREADY,
M_AXI_GP0_ARSIZE => open,
M_AXI_GP0_ARVALID => ARVALID,
M_AXI_GP0_AWADDR => m_axi_gp0_o.AWADDR,
M_AXI_GP0_AWBURST => open,
M_AXI_GP0_AWCACHE => open,
M_AXI_GP0_AWID => AWID,
M_AXI_GP0_AWLEN => open,
M_AXI_GP0_AWLOCK => open,
M_AXI_GP0_AWPROT => open,
M_AXI_GP0_AWQOS => open,
M_AXI_GP0_AWREADY => m_axi_gp0_i.AWREADY,
M_AXI_GP0_AWSIZE => open,
M_AXI_GP0_AWVALID => AWVALID,
M_AXI_GP0_BID => BID,
M_AXI_GP0_BREADY => m_axi_gp0_o.BREADY,
M_AXI_GP0_BRESP => m_axi_gp0_i.BRESP,
M_AXI_GP0_BVALID => m_axi_gp0_i.BVALID,
M_AXI_GP0_RDATA => m_axi_gp0_i.RDATA,
M_AXI_GP0_RID => RID,
M_AXI_GP0_RLAST => m_axi_gp0_i.RLAST,
M_AXI_GP0_RREADY => m_axi_gp0_o.RREADY,
M_AXI_GP0_RRESP => m_axi_gp0_i.RRESP,
M_AXI_GP0_RVALID => m_axi_gp0_i.RVALID,
M_AXI_GP0_WDATA => m_axi_gp0_o.WDATA,
M_AXI_GP0_WID => open,
M_AXI_GP0_WLAST => m_axi_gp0_o.WLAST,
M_AXI_GP0_WREADY => m_axi_gp0_i.WREADY,
M_AXI_GP0_WSTRB => m_axi_gp0_o.WSTRB,
M_AXI_GP0_WVALID => m_axi_gp0_o.WVALID,
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
USB0_PORT_INDCTL => USB0_PORT_INDCTL,
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT);
-- forward transaction IDs to convert to AXI4-Lite
m_axi_gp0_o.ARVALID <= ARVALID;
m_axi_gp0_o.AWVALID <= AWVALID;
process(m_axi_gp0_aclk_i)
begin
if rising_edge(m_axi_gp0_aclk_i) then
if ARVALID = '1' then
rid <= ARID;
end if;
if AWVALID = '1' then
BID <= AWID;
end if;
end if;
end process;
end wrapper;
files = [ "ad9263_serdes.v",
"ad9263_serdes_selectio_wiz.v",
"adc_core.vhd",
"axi4_pkg.vhd",
"xwb_axi4lite_bridge.vhd",
"bitUnpackAndAlign.vhd",
#bitUnpackAndAlign.vhd~
#Manifest.py
"d3s_acq_buffer.vhd",
"d3s_acq_buffer_wbgen2_pkg.vhd",
"d3s_acq_buffer_wb.vhd",
"trigger_generator.vhd",
"trigger_generator_wbgen2_pkg.vhd",
"trigger_generator_wb.vhd"
];
// file: ad9263_serdes.v
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//----------------------------------------------------------------------------
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ad9263_serdes,selectio_wiz_v5_1_7,{component_name=ad9263_serdes,bus_dir=INPUTS,bus_sig_type=DIFF,bus_io_std=LVDS_25,use_serialization=true,use_phase_detector=false,serialization_factor=8,enable_bitslip=false,enable_train=false,system_data_width=9,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=SINGLE,clk_io_std=LVCMOS18,clk_buf=BUFIO2,active_edge=RISING,clk_delay=NONE,selio_bus_in_delay=NONE,selio_bus_out_delay=NONE,selio_clk_buf=BUFIO,selio_active_edge=DDR,selio_ddr_alignment=SAME_EDGE_PIPELINED,selio_oddr_alignment=SAME_EDGE,ddr_alignment=C0,selio_interface_type=NETWORKING,interface_type=NETWORKING,selio_bus_in_tap=0,selio_bus_out_tap=0,selio_clk_io_std=LVDS_25,selio_clk_sig_type=DIFF}" *)
module ad9263_serdes
// width of the data for the system
#(parameter SYS_W = 9,
// width of the data for the device
parameter DEV_W = 72)
(
// From the system into the device
input [SYS_W-1:0] data_in_from_pins_p,
input [SYS_W-1:0] data_in_from_pins_n,
output [DEV_W-1:0] data_in_to_device,
input [SYS_W -1:0] bitslip, // Bitslip module is enabled in NETWORKING mode
// User should tie it to '0' if not needed
input clk_in_p, // Differential clock from IOB
input clk_in_n,
output clk_div_out, // Slow clock output
input clk_reset,
input io_reset);
ad9263_serdes_selectio_wiz
#(
.SYS_W(SYS_W),
.DEV_W(DEV_W)
)
inst
(
.data_in_from_pins_p(data_in_from_pins_p),
.data_in_from_pins_n(data_in_from_pins_n),
.data_in_to_device(data_in_to_device),
.bitslip(bitslip),
.clk_in_p(clk_in_p),
.clk_in_n(clk_in_n),
.clk_div_out(clk_div_out),
.clk_reset(clk_reset),
.io_reset(io_reset)
);
endmodule
// file: ad9263_serdes_selectio_wiz.v
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module ad9263_serdes_selectio_wiz
// width of the data for the system
#(parameter SYS_W = 9,
// width of the data for the device
parameter DEV_W = 72)
(
// From the system into the device
input [SYS_W-1:0] data_in_from_pins_p,
input [SYS_W-1:0] data_in_from_pins_n,
output [DEV_W-1:0] data_in_to_device,
input [SYS_W-1:0] bitslip, // Bitslip module is enabled in NETWORKING mode
// User should tie it to '0' if not needed
input clk_in_p, // Differential clock from IOB
input clk_in_n,
output clk_div_out, // Slow clock output
input clk_reset,
input io_reset);
localparam num_serial_bits = DEV_W/SYS_W;
wire clock_enable = 1'b1;
// Signal declarations
////------------------------------
// After the buffer
wire [SYS_W-1:0] data_in_from_pins_int;
// Between the delay and serdes
wire [SYS_W-1:0] data_in_from_pins_delay;
// Array to use intermediately from the serdes to the internal
// devices. bus "0" is the leftmost bus
wire [SYS_W-1:0] iserdes_q[0:13]; // fills in starting with 0
// Create the clock logic
IBUFDS
#(.IOSTANDARD ("LVDS_25"),
.DIFF_TERM ("TRUE"))
ibufds_clk_inst
(.I (clk_in_p),
.IB (clk_in_n),
.O (clk_in_int));
// High Speed BUFIO clock buffer
BUFIO bufio_inst
(.O(clk_in_int_buf),
.I(clk_in_int));
// BUFR generates the slow clock
BUFR
#(.SIM_DEVICE("7SERIES"),
.BUFR_DIVIDE("4"))
clkout_buf_inst
(.O (clk_div),
.CE(1'b1),
.CLR(clk_reset),
.I (clk_in_int));
assign clk_div_out = clk_div; // This is regional clock
// We have multiple bits- step over every bit, instantiating the required elements
genvar pin_count;
genvar slice_count;
generate for (pin_count = 0; pin_count < SYS_W; pin_count = pin_count + 1) begin: pins
// Instantiate the buffers
////------------------------------
// Instantiate a buffer for every bit of the data bus
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD ("LVDS_25"))
ibufds_inst
(.I (data_in_from_pins_p [pin_count]),
.IB (data_in_from_pins_n [pin_count]),
.O (data_in_from_pins_int[pin_count]));
// Pass through the delay
////-------------------------------
assign data_in_from_pins_delay[pin_count] = data_in_from_pins_int[pin_count];
// Instantiate the serdes primitive
////------------------------------
// local wire only for use in this generate loop
wire cascade_shift;
wire [SYS_W-1:0] icascade1;
wire [SYS_W-1:0] icascade2;
wire clk_in_int_inv;
assign clk_in_int_inv = ~ (clk_in_int_buf);
// declare the iserdes
ISERDESE2
# (
.DATA_RATE ("DDR"),
.DATA_WIDTH (8),
.INTERFACE_TYPE ("NETWORKING"),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.NUM_CE (2),
.OFB_USED ("FALSE"),
.IOBDELAY ("NONE"), // Use input at D to output the data on Q
.SERDES_MODE ("MASTER"))
iserdese2_master (
.Q1 (iserdes_q[0][pin_count]),
.Q2 (iserdes_q[1][pin_count]),
.Q3 (iserdes_q[2][pin_count]),
.Q4 (iserdes_q[3][pin_count]),
.Q5 (iserdes_q[4][pin_count]),
.Q6 (iserdes_q[5][pin_count]),
.Q7 (iserdes_q[6][pin_count]),
.Q8 (iserdes_q[7][pin_count]),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (bitslip[pin_count]), // 1-bit Invoke Bitslip. This can be used with any DATA_WIDTH, cascaded or not.
// The amount of BITSLIP is fixed by the DATA_WIDTH selection.
.CE1 (clock_enable), // 1-bit Clock enable input
.CE2 (clock_enable), // 1-bit Clock enable input
.CLK (clk_in_int_buf), // Fast source synchronous clock driven by BUFIO
.CLKB (clk_in_int_inv), // Locally inverted fast
.CLKDIV (clk_div), // Slow clock from BUFR.
.CLKDIVP (1'b0),
.D (data_in_from_pins_delay[pin_count]), // 1-bit Input signal from IOB
.DDLY (1'b0), // 1-bit Input from Input Delay component
.RST (io_reset), // 1-bit Asynchronous reset only.
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
// unused connections
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.OFB (1'b0),
.OCLK (1'b0),
.OCLKB (1'b0),
.O ()); // unregistered output of ISERDESE1
// Concatenate the serdes outputs together. Keep the timesliced
// bits together, and placing the earliest bits on the right
// ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
// the output will be 3210, 7654, ...
////---------------------------------------------------------
for (slice_count = 0; slice_count < num_serial_bits; slice_count = slice_count + 1) begin: in_slices
// This places the first data in time on the right
assign data_in_to_device[slice_count*SYS_W+:SYS_W] =
iserdes_q[num_serial_bits-slice_count-1];
// To place the first data in time on the left, use the
// following code, instead
// assign data_in_to_device[slice_count*SYS_W+:SYS_W] =
// iserdes_q[slice_count];
end
end
endgenerate
endmodule
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.axi4_pkg.all;
entity adc_core is
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
adc_dco_p_i : in std_logic;
adc_dco_n_i : in std_logic;
adc_fco_p_i : in std_logic;
adc_fco_n_i : in std_logic;
adc_d_p_i : in std_logic_vector(7 downto 0);
adc_d_n_i : in std_logic_vector(7 downto 0);
slave_i : in t_axi4_lite_slave_in_32;
slave_o : out t_axi4_lite_slave_out_32;
led0_o : out std_logic;
led1_o : out std_logic;
temp_b : inout std_logic;
adc_cs_o : out std_logic;
adc_sclk_o : out std_logic;
adc_sdata_b : inout std_logic
);
end adc_core;
architecture rtl of adc_core is
component ad9263_serdes is
generic (
SYS_W : integer := 9;
DEV_W : integer := 72
);
port (
data_in_from_pins_p : in std_logic_vector(sys_w-1 downto 0);
data_in_from_pins_n : in std_logic_vector(sys_w-1 downto 0);
DATA_IN_TO_DEVICE : out std_logic_vector(dev_w -1 downto 0);
bitslip : in std_logic_vector(sys_w -1 downto 0) := (others => '0');
clk_in_p : in std_logic;
clk_in_n : in std_logic;
clk_div_out : out std_logic;
clk_reset : in std_logic;
io_reset : in std_logic);
end component;
component bitUnpackAndAlign is
port (
rst_n_i : in std_logic;
clk_adc_i : in std_logic;
serdes_data_raw_i : in std_logic_vector(71 downto 0);
ch_a_data_o : out std_logic_vector(15 downto 0);
ch_b_data_o : out std_logic_vector(15 downto 0);
ch_c_data_o : out std_logic_vector(15 downto 0);
ch_d_data_o : out std_logic_vector(15 downto 0);
bitslip_o : out std_logic);
end component bitUnpackAndAlign;
component xwb_axi4lite_bridge is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
axi4_slave_i : in t_axi4_lite_slave_in_32;
axi4_slave_o : out t_axi4_lite_slave_out_32;
wb_master_o : out t_wishbone_master_out;
wb_master_i : in t_wishbone_master_in);
end component xwb_axi4lite_bridge;
component d3s_acq_buffer is
generic (
g_data_width : integer;
g_size : integer);
port (
rst_n_sys_i : in std_logic;
rst_n_acq_i : in std_logic;
clk_sys_i : in std_logic;
clk_acq_i : in std_logic;
trigger_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end component d3s_acq_buffer;
component trigger_generator is
port (
clk_adc_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_n_adc_i : in std_logic;
samples_i : in std_logic_vector(15 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
trig_bus_o : out std_logic_vector(3 downto 0));
end component trigger_generator;
-- Number of slave port(s) on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 9;
constant c_SLAVE_GPIO : integer := 0;
constant c_SLAVE_TRIG0 : integer := 1;
constant c_SLAVE_BUF0 : integer := 2;
constant c_SLAVE_TRIG1 : integer := 3;
constant c_SLAVE_BUF1 : integer := 4;
constant c_SLAVE_TRIG2 : integer := 5;
constant c_SLAVE_BUF2 : integer := 6;
constant c_SLAVE_TRIG3 : integer := 7;
constant c_SLAVE_BUF3 : integer := 8;
constant c_slave_addr : t_wishbone_address_array(0 to c_NUM_WB_SLAVES-1) :=
(c_SLAVE_GPIO => x"00000000",
c_SLAVE_TRIG0 => x"00001000",
c_SLAVE_BUF0 => x"00002000",
c_SLAVE_TRIG1 => x"00003000",
c_SLAVE_BUF1 => x"00004000",
c_SLAVE_TRIG2 => x"00005000",
c_SLAVE_BUF2 => x"00006000",
c_SLAVE_TRIG3 => x"00007000",
c_SLAVE_BUF3 => x"00008000"
);
constant c_slave_mask : t_wishbone_address_array(0 to c_NUM_WB_SLAVES-1) :=
(c_SLAVE_GPIO => x"0000f000",
c_SLAVE_TRIG0 => x"0000f000",
c_SLAVE_BUF0 => x"0000f000",
c_SLAVE_TRIG1 => x"0000f000",
c_SLAVE_BUF1 => x"0000f000",
c_SLAVE_TRIG2 => x"0000f000",
c_SLAVE_BUF2 => x"0000f000",
c_SLAVE_TRIG3 => x"0000f000",
c_SLAVE_BUF3 => x"0000f000"
);
type t_data_array is array(0 to 3) of std_logic_vector(15 downto 0);
type t_trigger_array is array(0 to 3) of std_logic_vector(3 downto 0);
signal ch_data : t_data_array;
signal ch_triggers : t_trigger_array;
signal ch_trigger_ored : std_logic_vector(3 downto 0);
signal serdes_data_raw : std_logic_vector(71 downto 0);
signal clk_adc, rst_adc, rst_n_adc : std_logic;
signal wb_slave_in : t_wishbone_slave_in;
signal wb_slave_out : t_wishbone_slave_out;
signal cnx_master_out : t_wishbone_master_out_array(0 to c_NUM_WB_SLAVES-1);
signal cnx_master_in : t_wishbone_master_in_array(0 to c_NUM_WB_SLAVES-1);
signal gpio_out, gpio_in, gpio_oen : std_logic_vector(31 downto 0);
signal serdes_bitslip : std_logic;
signal serdes_bitslip_slv : std_logic_vector(8 downto 0);
function f_gen_trigger(channel : integer; triggers : t_trigger_array) return std_logic is
begin
return triggers(0)(channel) or triggers(1)(channel) or triggers(2)(channel) or triggers(3)(channel);
end f_gen_trigger;
signal rst_adc_serdes, rst_adc_clock : std_logic;
signal rst_adc_sys : std_logic;
begin
xwb_axi4lite_bridge_1 : xwb_axi4lite_bridge
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
axi4_slave_i => slave_i,
axi4_slave_o => slave_o,
wb_master_o => wb_slave_in,
wb_master_i => wb_slave_out);
U_crossbar : xwb_crossbar
generic map (
g_num_masters => 1,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => true,
g_address => c_slave_addr,
g_mask => c_slave_mask)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i(0) => wb_slave_in,
slave_o(0) => wb_slave_out,
master_o => cnx_master_out,
master_i => cnx_master_in
);
rst_adc_serdes <= not gpio_out(10);
rst_adc_clock <= not gpio_out(11);
rst_adc_sys <= not rst_n_i or gpio_out(12);
gc_sync_ffs_1: gc_sync_ffs
port map (
clk_i => clk_adc,
rst_n_i => rst_n_i,
data_i => rst_adc_sys,
synced_o => rst_adc);
rst_n_adc <= not rst_adc;
U_Serdes : ad9263_serdes
port map (
data_in_from_pins_p(8) => adc_fco_p_i,
data_in_from_pins_p(7 downto 0) => adc_d_p_i,
data_in_from_pins_n(8) => adc_fco_n_i,
data_in_from_pins_n(7 downto 0) => adc_d_n_i,
DATA_IN_TO_DEVICE => serdes_data_raw,
clk_in_p => adc_dco_p_i,
clk_in_n => adc_dco_n_i,
clk_div_out => clk_adc,
clk_reset => rst_adc_clock,
io_reset => rst_adc_serdes,
bitslip => serdes_bitslip_slv);
serdes_bitslip_slv <= (others => serdes_bitslip);
U_UnpackAndAlign : bitUnpackAndAlign
port map (
rst_n_i => rst_n_adc,
clk_adc_i => clk_adc,
serdes_data_raw_i => serdes_data_raw,
ch_a_data_o => ch_data(0),
ch_b_data_o => ch_data(1),
ch_c_data_o => ch_data(2),
ch_d_data_o => ch_data(3),
bitslip_o => serdes_bitslip);
gen_triggers_and_buffers : for channel in 0 to 3 generate
U_trigger_generator_CHx : trigger_generator
port map (
clk_adc_i => clk_adc,
clk_sys_i => clk_sys_i,
rst_n_sys_i => rst_n_i,
rst_n_adc_i => rst_n_adc,
samples_i => ch_data(channel),
slave_i => cnx_master_out(c_SLAVE_TRIG0 + 2 * channel),
slave_o => cnx_master_in(c_SLAVE_TRIG0 + 2 * channel),
trig_bus_o => ch_triggers(channel));
ch_trigger_ored(channel) <= f_gen_trigger(channel, ch_triggers);
U_Buf_CHx : d3s_acq_buffer
generic map (
g_data_width => 16,
g_size => 1024)
port map (
rst_n_sys_i => rst_n_i,
rst_n_acq_i => rst_n_adc,
clk_sys_i => clk_sys_i,
clk_acq_i => clk_adc,
data_i => ch_data(channel),
trigger_i => ch_trigger_ored(channel),
slave_i => cnx_master_out(c_SLAVE_BUF0 + 2 * channel),
slave_o => cnx_master_in(c_SLAVE_BUF0 + 2 * channel));
end generate gen_triggers_and_buffers;
xwb_gpio_port_1 : xwb_gpio_port
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_pins => 32,
g_with_builtin_tristates => false)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cnx_master_out(c_SLAVE_GPIO),
slave_o => cnx_master_in(c_SLAVE_GPIO),
gpio_out_o => gpio_out,
gpio_in_i => gpio_in,
gpio_oen_o => gpio_oen);
led0_o <= gpio_out(0);
led1_o <= gpio_out(4);
adc_cs_o <= gpio_out(5);
adc_sclk_o <= gpio_out(6);
adc_sdata_b <=gpio_out(7) when gpio_oen(7) = '0' else 'Z';
gpio_in(7) <= adc_sdata_b;
temp_b <= gpio_out(8) when gpio_oen(8) = '0' else 'Z';
gpio_in(8) <= temp_b;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
package axi4_pkg is
-- AXI4-Full interface, master output ports, 32 bits
type t_axi4_full_master_out_32 is record
ARVALID : std_logic;
AWVALID : std_logic;
BREADY : std_logic;
RREADY : std_logic;
WLAST : std_logic;
WVALID : std_logic;
ARID : std_logic_vector (11 downto 0);
AWID : std_logic_vector (11 downto 0);
WID : std_logic_vector (11 downto 0);
ARBURST : std_logic_vector (1 downto 0);
ARLOCK : std_logic_vector (1 downto 0);
ARSIZE : std_logic_vector (2 downto 0);
AWBURST : std_logic_vector (1 downto 0);
AWLOCK : std_logic_vector (1 downto 0);
AWSIZE : std_logic_vector (2 downto 0);
ARPROT : std_logic_vector (2 downto 0);
AWPROT : std_logic_vector (2 downto 0);
ARADDR : std_logic_vector (31 downto 0);
AWADDR : std_logic_vector (31 downto 0);
WDATA : std_logic_vector (31 downto 0);
ARCACHE : std_logic_vector (3 downto 0);
ARLEN : std_logic_vector (3 downto 0);
ARQOS : std_logic_vector (3 downto 0);
AWCACHE : std_logic_vector (3 downto 0);
AWLEN : std_logic_vector (3 downto 0);
AWQOS : std_logic_vector (3 downto 0);
WSTRB : std_logic_vector (3 downto 0);
end record;
-- AXI4-Full interface, master input ports, 32 bits
type t_axi4_full_master_in_32 is record
ARREADY : std_logic;
AWREADY : std_logic;
BVALID : std_logic;
RLAST : std_logic;
RVALID : std_logic;
WREADY : std_logic;
BID : std_logic_vector (11 downto 0);
RID : std_logic_vector (11 downto 0);
BRESP : std_logic_vector (1 downto 0);
RRESP : std_logic_vector (1 downto 0);
RDATA : std_logic_vector (31 downto 0);
end record;
-- AXI4-Lite interface, master output ports, 32 bits
type t_axi4_lite_master_out_32 is record
ARVALID : std_logic;
AWVALID : std_logic;
BREADY : std_logic;
RREADY : std_logic;
WLAST : std_logic;
WVALID : std_logic;
ARADDR : std_logic_vector (31 downto 0);
AWADDR : std_logic_vector (31 downto 0);
WDATA : std_logic_vector (31 downto 0);
WSTRB : std_logic_vector (3 downto 0);
end record;
-- AXI4-Lite interface, master input ports, 32 bits
type t_axi4_lite_master_in_32 is record
ARREADY : std_logic;
AWREADY : std_logic;
BVALID : std_logic;
RLAST : std_logic;
RVALID : std_logic;
WREADY : std_logic;
BRESP : std_logic_vector (1 downto 0);
RRESP : std_logic_vector (1 downto 0);
RDATA : std_logic_vector (31 downto 0);
end record;
constant c_axi4_lite_default_master_in_32 : t_axi4_lite_master_in_32 :=
(
AWREADY => '0',
ARREADY => '0',
BVALID => '0',
RLAST => '0',
RVALID => '0',
WREADY => '0',
BRESP => "00",
RRESP => "00",
RDATA => (others => '0')
);
constant c_axi4_lite_default_master_out_32 : t_axi4_lite_master_out_32 :=
(
ARVALID => '0',
AWVALID => '0',
BREADY => '0',
RREADY => '0',
WLAST => '0',
WVALID => '0',
ARADDR => (others => '0'),
AWADDR => (others => '0'),
WDATA => (others => '0'),
WSTRB => (others => '0')
);
subtype t_axi4_lite_slave_in_32 is t_axi4_lite_master_out_32;
subtype t_axi4_lite_slave_out_32 is t_axi4_lite_master_in_32;
constant c_AXI4_RESP_OKAY : std_logic_vector(1 downto 0) := "00";
constant c_AXI4_RESP_EXOKAY : std_logic_vector(1 downto 0) := "01";
constant c_AXI4_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
constant c_AXI4_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
function f_axi4_full_to_lite (
f : t_axi4_full_master_out_32
) return t_axi4_lite_master_out_32;
function f_axi4_lite_to_full (
l : t_axi4_lite_master_in_32
) return t_axi4_full_master_in_32;
end package;
package body axi4_pkg is
function f_axi4_full_to_lite (
f : t_axi4_full_master_out_32
) return t_axi4_lite_master_out_32 is
variable l : t_axi4_lite_master_out_32;
begin
l.ARVALID := f.ARVALID;
l.AWVALID := f.AWVALID;
l.BREADY := f.BREADY;
l.RREADY := f.RREADY;
l.WLAST := f.WLAST;
l.WVALID := f.WVALID;
l.ARADDR := f.ARADDR;
l.AWADDR := f.AWADDR;
l.WDATA := f.WDATA;
l.WSTRB := f.WSTRB;
return l;
end f_axi4_full_to_lite;
function f_axi4_lite_to_full (
l : t_axi4_lite_master_in_32
) return t_axi4_full_master_in_32 is
variable f : t_axi4_full_master_in_32;
begin
f.ARREADY := l.ARREADY;
f.AWREADY := l.AWREADY;
f.BVALID := l.BVALID;
f.RLAST := l.RLAST;
f.RVALID := l.RVALID;
f.WREADY := l.WREADY;
f.BID := (others => '0');
f.RID := (others => '0');
f.BRESP := l.BRESP;
f.RRESP := l.RRESP;
f.RDATA := l.RDATA;
return f;
end f_axi4_lite_to_full;
end package body;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity bitUnpackAndAlign is
port(
rst_n_i : in std_logic;
-- ADC sampling clock (fDCO / 8)
clk_adc_i : in std_logic;
-- Raw ADC data including the FCO line (used for bit alignment)
serdes_data_raw_i : in std_logic_vector(71 downto 0);
-- ADC data output
ch_a_data_o : out std_logic_vector(15 downto 0);
ch_b_data_o : out std_logic_vector(15 downto 0);
ch_c_data_o : out std_logic_vector(15 downto 0);
ch_d_data_o : out std_logic_vector(15 downto 0);
-- Bitslip trigger
bitslip_o : out std_logic
);
end bitUnpackAndAlign;
architecture Behavioral of bitUnpackAndAlign is
signal serdes_out_data : std_logic_vector(63 downto 0);
signal serdes_out_fr : std_logic_vector(7 downto 0);
signal serdes_synced : std_logic;
signal serdes_bitslip : std_logic := '0';
signal count : std_logic_vector(1 downto 0);
signal test : std_logic_vector(7 downto 0);
signal data: std_logic_vector(63 downto 0);
signal fr : std_logic_vector(7 downto 0);
signal cnt : unsigned(5 downto 0);
--
signal data_a : std_logic_vector(15 downto 0);
signal data_b : std_logic_vector(15 downto 0);
signal data_c : std_logic_vector(15 downto 0);
signal data_d : std_logic_vector(15 downto 0);
--
component ila_1 is
port(
clk : in std_logic;
probe0 : in std_logic_vector(7 downto 0);
probe1 : in std_logic_vector(0 downto 0);
probe2 : in std_logic_vector(0 downto 0);
probe3 : in std_logic_vector(63 downto 0);
--
probe4 : in std_logic_vector(15 downto 0);
probe5 : in std_logic_vector(15 downto 0);
probe6 : in std_logic_vector(15 downto 0);
probe7 : in std_logic_vector(15 downto 0)
);
end component;
begin
-- Sort all the raw data from the SERDES.
-- out_data(15:0) = CH1
-- out_data(31:16) = CH2
-- out_data(47:32) = CH3
-- out_data(63:48) = CH4
gen_serdes_dout_reorder : for I in 0 to 7 generate
serdes_out_data(15 - 2*i) <= not serdes_data_raw_i(1 + i*9);
serdes_out_data(15 - 2*i-1) <= not serdes_data_raw_i(0 + i*9);
serdes_out_data(31 - 2*i) <= not serdes_data_raw_i(3 + i*9);
serdes_out_data(31 - 2*i-1) <= not serdes_data_raw_i(2 + i*9);
serdes_out_data(47 - 2*i) <= not serdes_data_raw_i(5 + i*9);
serdes_out_data(47 - 2*i-1) <= not serdes_data_raw_i(4 + i*9);
serdes_out_data(63 - 2*i) <= not serdes_data_raw_i(7 + i*9);
serdes_out_data(63 - 2*i-1) <= not serdes_data_raw_i(6 + i*9);
serdes_out_fr(i) <= not serdes_data_raw_i(8 + i*9); -- FR
end generate gen_serdes_dout_reorder;
process(clk_adc_i)
begin
if rising_edge(clk_adc_i) then
if rst_n_i = '0' then -- Synchronous reset
ch_a_data_o <= (others => '0');
ch_b_data_o <= (others => '0');
ch_c_data_o <= (others => '0');
ch_d_data_o <= (others => '0');
else -- Data spread on different buses and sign conserved
ch_a_data_o <= serdes_out_data(15) & serdes_out_data(15) & serdes_out_data(15 downto 2);
ch_b_data_o <= serdes_out_data(31) & serdes_out_data(31) & serdes_out_data(31 downto 18);
ch_c_data_o <= serdes_out_data(47) & serdes_out_data(47) & serdes_out_data(47 downto 34);
ch_d_data_o <= serdes_out_data(63) & serdes_out_data(63) & serdes_out_data(63 downto 50);
end if;
end if;
end process;
-- SERDES bitslip generation
-- All the bits are shifted together if the frame clock is not
-- well reconstructed. The bitslip signal cannot be continuous,
-- each time we have to wait for new incoming data to check if
-- the frame clock is correct.
bitslip_gen : process(clk_adc_i, rst_n_i)
begin
if rising_edge(clk_adc_i) then
if rst_n_i = '0' then
serdes_bitslip <= '0';
serdes_synced <= '0';
cnt <= (others => '0');
else
cnt <= cnt + 1;
if cnt = 0 and serdes_out_fr /= X"0f" then -- Attention to the polarity
serdes_synced <= '0';
serdes_bitslip <= '1';
elsif cnt = 20 and serdes_out_fr = X"0f" then
serdes_synced <= '1';
serdes_bitslip <= '0';
else
serdes_bitslip <= '0';
end if;
end if;
end if;
end process;
process(clk_adc_i, rst_n_i)
begin
if rising_edge(clk_adc_i) then
data <= serdes_out_data;
fr <= serdes_out_fr;
data_a <= serdes_out_data(15) & serdes_out_data(15) & serdes_out_data(15 downto 2);
data_b <= serdes_out_data(31) & serdes_out_data(31) & serdes_out_data(31 downto 18);
data_c <= serdes_out_data(47) & serdes_out_data(47) & serdes_out_data(47 downto 34);
data_d <= serdes_out_data(63) & serdes_out_data(63) & serdes_out_data(63 downto 50);
end if;
end process;
ila_1_1: ila_1
port map (
clk => clk_adc_i,
probe0 => fr,
probe1(0) => serdes_bitslip,
probe2(0) => serdes_synced,
probe3 => data,
--
probe4 => data_a,
probe5 => data_b,
probe6 => data_c,
probe7 => data_d
);
bitslip_o <= serdes_bitslip;
end Behavioral;
#!/bin/bash
wbgen2 -V d3s_acq_buffer_wb.vhd -H record -p d3s_acq_buffer_wbgen2_pkg.vhd -K d3s_acq_buffer_wb.vh -s defines -C d3s_acq_buffer_wb.h -D d3s_acq_buffer_wb.html d3s_acq_buffer_wb.wb
wbgen2 -V trigger_generator_wb.vhd -H record -p trigger_generator_wbgen2_pkg.vhd -K trigger_generator_wb.vh -s defines -C trigger_generator_wb.h -D trigger_generator_wb.html trigger_generator_wb.wb
mv *_wb.vh ../../testbench/include
\ No newline at end of file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.acq_wbgen2_pkg.all;
entity d3s_acq_buffer is
generic (
g_data_width : integer;
g_size : integer);
port (
rst_n_sys_i : in std_logic;
rst_n_acq_i : in std_logic;
clk_sys_i : in std_logic;
clk_acq_i : in std_logic;
trigger_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
);
end d3s_acq_buffer;
architecture rtl of d3s_acq_buffer is
component d3s_acq_buffer_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_acq_i : in std_logic;
regs_i : in t_acq_in_registers;
regs_o : out t_acq_out_registers);
end component d3s_acq_buffer_wb;
constant c_addr_bits : integer := f_log2_size(g_size);
signal wr_addr : unsigned(c_addr_bits-1 downto 0);
signal wr_addr_last : unsigned(c_addr_bits-1 downto 0);
signal done : std_logic;
signal regs_in : t_acq_in_registers;
signal regs_out : t_acq_out_registers;
signal acq_in_progress : std_logic;
signal triggered : std_logic;
begin
U_Wb : d3s_acq_buffer_wb
port map (
rst_n_i => rst_n_sys_i,
clk_sys_i => clk_sys_i,
wb_adr_i => slave_i.adr(4 downto 2),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
clk_acq_i => clk_acq_i,
regs_i => regs_in,
regs_o => regs_out);
slave_o.err <= '0';
slave_o.rty <= '0';
U_Buffer : generic_dpram
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => false,
g_dual_clock => true)
port map (
rst_n_i => rst_n_sys_i,
clka_i => clk_acq_i,
wea_i => acq_in_progress,
aa_i => std_logic_vector(wr_addr),
da_i => data_i,
clkb_i => clk_sys_i,
web_i => '0',
ab_i => regs_out.addr_o(c_addr_bits-1 downto 0),
qb_o => regs_in.data_i(g_data_width-1 downto 0));
regs_in.data_i(31 downto g_data_width) <= (others => '0');
regs_in.size_i <= std_logic_vector(to_unsigned(g_size, 32));
p_counter : process(clk_acq_i)
begin
if rising_edge(clk_acq_i) then
if rst_n_acq_i = '0' then
acq_in_progress <= '0';
wr_addr <= (others => '0');
else
if(regs_out.csr_start_o = '1') then
wr_addr <= (others => '0');
acq_in_progress <= '1';
triggered <= '0';
elsif (acq_in_progress = '1')then
if (trigger_i = '1') then
triggered <= '1';
wr_addr_last <= wr_addr - resize(unsigned(regs_out.pretrigger_o), wr_addr'length);
regs_in.trig_pos_i <= std_logic_vector(resize(wr_addr, 32));
end if;
if (triggered = '1' and wr_addr = wr_addr_last) then
acq_in_progress <= '0';
triggered <= '0';
end if;
wr_addr <= wr_addr + 1;
end if;
end if;
end if;
end process;
regs_in.csr_ready_i <= not acq_in_progress;
end rtl;
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "D3S Acquisition buffer";
prefix = "acq";
hdl_entity = "d3s_acq_buffer_wb";
reg {
name = "Control Reg";
prefix = "CSR";
field {
name = "Start sampling";
type = MONOSTABLE;
clock = "clk_acq_i";
prefix = "START";
};
field {
name = "Ready";
type = BIT;
clock = "clk_acq_i";
prefix = "READY";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Size";
prefix = "SIZE";
field {
name = "Buffer size";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Pretrigger samples";
prefix = "PRETRIGGER";
field {
name = "Samples count";
size = 32;
clock = "clk_acq_i";
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Trigger Position";
prefix = "TRIG_POS";
field {
name = "Position";
size = 32;
clock = "clk_acq_i";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Buffer address";
prefix = "ADDR";
field {
name = "Address";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Buffer data";
prefix = "DATA";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for D3S Acquisition buffer
---------------------------------------------------------------------------------------
-- File : d3s_acq_buffer_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from d3s_acq_buffer_wb.wb
-- Created : Thu Sep 15 18:33:44 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE d3s_acq_buffer_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package acq_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_acq_in_registers is record
csr_ready_i : std_logic;
size_i : std_logic_vector(31 downto 0);
trig_pos_i : std_logic_vector(31 downto 0);
data_i : std_logic_vector(31 downto 0);
end record;
constant c_acq_in_registers_init_value: t_acq_in_registers := (
csr_ready_i => '0',
size_i => (others => '0'),
trig_pos_i => (others => '0'),
data_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_acq_out_registers is record
csr_start_o : std_logic;
pretrigger_o : std_logic_vector(31 downto 0);
addr_o : std_logic_vector(31 downto 0);
end record;
constant c_acq_out_registers_init_value: t_acq_out_registers := (
csr_start_o => '0',
pretrigger_o => (others => '0'),
addr_o => (others => '0')
);
function "or" (left, right: t_acq_in_registers) return t_acq_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body acq_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_acq_in_registers) return t_acq_in_registers is
variable tmp: t_acq_in_registers;
begin
tmp.csr_ready_i := f_x_to_zero(left.csr_ready_i) or f_x_to_zero(right.csr_ready_i);
tmp.size_i := f_x_to_zero(left.size_i) or f_x_to_zero(right.size_i);
tmp.trig_pos_i := f_x_to_zero(left.trig_pos_i) or f_x_to_zero(right.trig_pos_i);
tmp.data_i := f_x_to_zero(left.data_i) or f_x_to_zero(right.data_i);
return tmp;
end function;
end package body;
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.tg_wbgen2_pkg.all;
entity trigger_generator is
port (
clk_adc_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_n_adc_i : in std_logic;
samples_i : in std_logic_vector(15 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- bus trigger output to all 4 channels of the ADC
trig_bus_o : out std_logic_vector(3 downto 0)
);
end trigger_generator;
architecture rtl of trigger_generator is
component trigger_generator_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_acq_i : in std_logic;
regs_i : in t_tg_in_registers;
regs_o : out t_tg_out_registers);
end component trigger_generator_wb;
signal x, thr_lo, thr_hi : signed(15 downto 0);
signal regs_out : t_tg_out_registers;
signal regs_in : t_tg_in_registers;
type t_state is (IDLE, ARMED, WAIT_THR_LO, THR_LO_HIT);
signal state : t_state;
begin
x <= signed(samples_i);
thr_lo <= signed(regs_out.thr_lo_o);
thr_hi <= signed(regs_out.thr_hi_o);
trigger_generator_wb_1: trigger_generator_wb
port map (
rst_n_i => rst_n_sys_i,
clk_sys_i => clk_sys_i,
wb_adr_i => slave_i.adr(3 downto 2),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
clk_acq_i => clk_adc_i,
regs_i => regs_in,
regs_o => regs_out);
p_fsm : process(clk_adc_i)
begin
if rising_edge(clk_adc_i) then
if rst_n_adc_i = '0' or regs_out.csr_enable_o = '0' then
trig_bus_o <= (others => '0');
regs_in.csr_triggered_i <= '0';
state <= IDLE;
else
case state is
when IDLE =>
trig_bus_o <= (others => '0');
if(regs_out.csr_arm_o = '1') then
regs_in.csr_triggered_i <= '0';
state <= ARMED;
elsif (regs_out.csr_force_o = '1') then
trig_bus_o <= regs_out.csr_mask_o;
regs_in.csr_triggered_i <= '1';
state <= IDLE;
end if;
when ARMED =>
if (regs_out.csr_polarity_o = '0' and x <= thr_lo) or (regs_out.csr_polarity_o = '1' and x >= thr_lo) then
state <= WAIT_THR_LO;
end if;
when WAIT_THR_LO =>
if (regs_out.csr_polarity_o = '0' and x > thr_lo) or (regs_out.csr_polarity_o = '1' and x < thr_lo) then
state <= THR_LO_HIT;
end if;
when THR_LO_HIT =>
if (regs_out.csr_polarity_o = '0' and x <= thr_lo) or (regs_out.csr_polarity_o = '1' and x >= thr_lo) then
state <= ARMED;
elsif (regs_out.csr_polarity_o = '0' and x > thr_hi) or (regs_out.csr_polarity_o = '1' and x < thr_hi) then
trig_bus_o <= regs_out.csr_mask_o;
regs_in.csr_triggered_i <= '1';
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
end rtl;
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Trigger Generator Block";
prefix = "tg";
hdl_entity = "trigger_generator_wb";
reg {
name = "Control/Status Reg";
prefix = "CSR";
field {
name = "Enable";
type = BIT;
clock = "clk_acq_i";
prefix = "ENABLE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Polarity";
type = BIT;
clock = "clk_acq_i";
prefix = "POLARITY";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Channel Mask";
type = SLV;
size = 4;
clock = "clk_acq_i";
prefix = "MASK";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Arm";
type = MONOSTABLE;
clock = "clk_acq_i";
prefix = "ARM";
};
field {
name = "Force Manual Trigger";
type = MONOSTABLE;
clock = "clk_acq_i";
prefix = "FORCE";
};
field {
name = "Triggered";
type = BIT;
clock = "clk_acq_i";
prefix = "TRIGGERED";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Threshold (low)";
prefix = "THR_LO";
field {
name = "Threshold";
size = 16;
clock = "clk_acq_i";
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Threshold (high)";
prefix = "THR_HI";
field {
name = "Threshold";
size = 16;
clock = "clk_acq_i";
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Trigger Generator Block
---------------------------------------------------------------------------------------
-- File : trigger_generator_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from trigger_generator_wb.wb
-- Created : Thu Sep 15 18:33:44 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE trigger_generator_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tg_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_tg_in_registers is record
csr_triggered_i : std_logic;
end record;
constant c_tg_in_registers_init_value: t_tg_in_registers := (
csr_triggered_i => '0'
);
-- Output registers (WB slave -> user design)
type t_tg_out_registers is record
csr_enable_o : std_logic;
csr_polarity_o : std_logic;
csr_mask_o : std_logic_vector(3 downto 0);
csr_arm_o : std_logic;
csr_force_o : std_logic;
thr_lo_o : std_logic_vector(15 downto 0);
thr_hi_o : std_logic_vector(15 downto 0);
end record;
constant c_tg_out_registers_init_value: t_tg_out_registers := (
csr_enable_o => '0',
csr_polarity_o => '0',
csr_mask_o => (others => '0'),
csr_arm_o => '0',
csr_force_o => '0',
thr_lo_o => (others => '0'),
thr_hi_o => (others => '0')
);
function "or" (left, right: t_tg_in_registers) return t_tg_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body tg_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_tg_in_registers) return t_tg_in_registers is
variable tmp: t_tg_in_registers;
begin
tmp.csr_triggered_i := f_x_to_zero(left.csr_triggered_i) or f_x_to_zero(right.csr_triggered_i);
return tmp;
end function;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi4_pkg.all;
use work.wishbone_pkg.all;
entity xwb_axi4lite_bridge is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
axi4_slave_i : in t_axi4_lite_slave_in_32;
axi4_slave_o : out t_axi4_lite_slave_out_32;
wb_master_o : out t_wishbone_master_out;
wb_master_i : in t_wishbone_master_in
);
end xwb_axi4lite_bridge;
architecture rtl of xwb_axi4lite_bridge is
constant c_timeout : integer := 256;
type t_state is
(IDLE, ISSUE_WRITE, ISSUE_READ, COMPLETE_WRITE, COMPLETE_READ, WAIT_ACK_READ, WAIT_ACK_WRITE, RESPONSE_READ, RESPONSE_WRITE);
signal state : t_state;
signal count : unsigned(10 downto 0);
begin
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
axi4_slave_o <= c_axi4_lite_default_master_in_32;
wb_master_o.cyc <= '0';
state <= IDLE;
else
case state is
when IDLE =>
wb_master_o.cyc <= '0';
axi4_slave_o.ARREADY <= '1';
axi4_slave_o.AWREADY <= '1';
axi4_slave_o.WREADY <= '0';
axi4_slave_o.BVALID <= '0';
axi4_slave_o.BRESP <= (others => 'X');
axi4_slave_o.RDATA <= (others => 'X');
axi4_slave_o.RRESP <= (others => 'X');
axi4_slave_o.RVALID <= '0';
axi4_slave_o.RLAST <= '0';
if(axi4_slave_i.AWVALID = '1') then
state <= ISSUE_WRITE;
wb_master_o.adr <= axi4_slave_i.AWADDR;
elsif (axi4_slave_i.ARVALID = '1') then
state <= ISSUE_READ;
wb_master_o.adr <= axi4_slave_i.ARADDR;
end if;
when ISSUE_WRITE =>
axi4_slave_o.WREADY <= '1';
wb_master_o.cyc <= '1';
wb_master_o.we <= '1';
if(axi4_slave_i.WVALID = '1' and axi4_slave_i.WLAST = '1') then
wb_master_o.stb <= '1';
wb_master_o.sel <= axi4_slave_i.WSTRB;
wb_master_o.dat <= axi4_slave_i.WDATA;
state <= COMPLETE_WRITE;
end if;
when ISSUE_READ =>
wb_master_o.cyc <= '1';
wb_master_o.stb <= '1';
wb_master_o.we <= '0';
axi4_slave_o.RVALID <= '0';
axi4_slave_o.RLAST <= '0';
state <= COMPLETE_READ;
when COMPLETE_READ =>
if(wb_master_i.stall = '0') then
wb_master_o.stb <= '0';
if(wb_master_i.ack = '1') then
state <= IDLE;
axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
axi4_slave_o.RDATA <= wb_master_i.dat;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
wb_master_o.cyc <= '0';
else
state <= WAIT_ACK_READ;
count <= (others => '0');
end if;
end if;
when COMPLETE_WRITE =>
if(wb_master_i.stall = '0') then
wb_master_o.stb <= '0';
if(wb_master_i.ack = '1') then
state <= RESPONSE_WRITE;
axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
wb_master_o.cyc <= '0';
else
state <= WAIT_ACK_WRITE;
count <= (others => '0');
end if;
end if;
when WAIT_ACK_WRITE =>
if(wb_master_i.ack = '1') then
state <= RESPONSE_WRITE;
axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
wb_master_o.cyc <= '0';
elsif count = c_timeout then
state <= RESPONSE_WRITE;
axi4_slave_o.BRESP <= c_AXI4_RESP_SLVERR;
wb_master_o.cyc <= '0';
end if;
count <= count + 1;
when WAIT_ACK_READ =>
if(wb_master_i.ack = '1') then
state <= IDLE;
axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
axi4_slave_o.RDATA <= wb_master_i.dat;
wb_master_o.cyc <= '0';
elsif count = c_timeout then
state <= IDLE;
axi4_slave_o.RRESP <= c_AXI4_RESP_SLVERR;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
axi4_slave_o.RDATA <= (others => 'X');
wb_master_o.cyc <= '0';
end if;
count <= count + 1;
when RESPONSE_WRITE =>
if (axi4_slave_i.BREADY = '1') then
axi4_slave_o.BVALID <= '1';
state <= IDLE;
end if;
when RESPONSE_READ => null;
end case;
end if;
end if;
end process;
end rtl;
`define ADDR_MDIO_MCR 7'h0
`define MDIO_MCR_RESV_OFFSET 0
`define MDIO_MCR_RESV 32'h0000001f
`define MDIO_MCR_UNI_EN_OFFSET 5
`define MDIO_MCR_UNI_EN 32'h00000020
`define MDIO_MCR_SPEED1000_OFFSET 6
`define MDIO_MCR_SPEED1000 32'h00000040
`define MDIO_MCR_CTST_OFFSET 7
`define MDIO_MCR_CTST 32'h00000080
`define MDIO_MCR_FULLDPLX_OFFSET 8
`define MDIO_MCR_FULLDPLX 32'h00000100
`define MDIO_MCR_ANRESTART_OFFSET 9
`define MDIO_MCR_ANRESTART 32'h00000200
`define MDIO_MCR_ISOLATE_OFFSET 10
`define MDIO_MCR_ISOLATE 32'h00000400
`define MDIO_MCR_PDOWN_OFFSET 11
`define MDIO_MCR_PDOWN 32'h00000800
`define MDIO_MCR_ANENABLE_OFFSET 12
`define MDIO_MCR_ANENABLE 32'h00001000
`define MDIO_MCR_SPEED100_OFFSET 13
`define MDIO_MCR_SPEED100 32'h00002000
`define MDIO_MCR_LOOPBACK_OFFSET 14
`define MDIO_MCR_LOOPBACK 32'h00004000
`define MDIO_MCR_RESET_OFFSET 15
`define MDIO_MCR_RESET 32'h00008000
`define ADDR_MDIO_MSR 7'h4
`define MDIO_MSR_ERCAP_OFFSET 0
`define MDIO_MSR_ERCAP 32'h00000001
`define MDIO_MSR_JCD_OFFSET 1
`define MDIO_MSR_JCD 32'h00000002
`define MDIO_MSR_LSTATUS_OFFSET 2
`define MDIO_MSR_LSTATUS 32'h00000004
`define MDIO_MSR_ANEGCAPABLE_OFFSET 3
`define MDIO_MSR_ANEGCAPABLE 32'h00000008
`define MDIO_MSR_RFAULT_OFFSET 4
`define MDIO_MSR_RFAULT 32'h00000010
`define MDIO_MSR_ANEGCOMPLETE_OFFSET 5
`define MDIO_MSR_ANEGCOMPLETE 32'h00000020
`define MDIO_MSR_MFSUPPRESS_OFFSET 6
`define MDIO_MSR_MFSUPPRESS 32'h00000040
`define MDIO_MSR_UNIDIRABLE_OFFSET 7
`define MDIO_MSR_UNIDIRABLE 32'h00000080
`define MDIO_MSR_ESTATEN_OFFSET 8
`define MDIO_MSR_ESTATEN 32'h00000100
`define MDIO_MSR_100HALF2_OFFSET 9
`define MDIO_MSR_100HALF2 32'h00000200
`define MDIO_MSR_100FULL2_OFFSET 10
`define MDIO_MSR_100FULL2 32'h00000400
`define MDIO_MSR_10HALF_OFFSET 11
`define MDIO_MSR_10HALF 32'h00000800
`define MDIO_MSR_10FULL_OFFSET 12
`define MDIO_MSR_10FULL 32'h00001000
`define MDIO_MSR_100HALF_OFFSET 13
`define MDIO_MSR_100HALF 32'h00002000
`define MDIO_MSR_100FULL_OFFSET 14
`define MDIO_MSR_100FULL 32'h00004000
`define MDIO_MSR_100BASE4_OFFSET 15
`define MDIO_MSR_100BASE4 32'h00008000
`define ADDR_MDIO_PHYSID1 7'h8
`define MDIO_PHYSID1_OUI_OFFSET 0
`define MDIO_PHYSID1_OUI 32'h0000ffff
`define ADDR_MDIO_PHYSID2 7'hc
`define MDIO_PHYSID2_REV_NUM_OFFSET 0
`define MDIO_PHYSID2_REV_NUM 32'h0000000f
`define MDIO_PHYSID2_MMNUM_OFFSET 4
`define MDIO_PHYSID2_MMNUM 32'h000003f0
`define MDIO_PHYSID2_OUI_OFFSET 10
`define MDIO_PHYSID2_OUI 32'h0000fc00
`define ADDR_MDIO_ADVERTISE 7'h10
`define MDIO_ADVERTISE_RSVD3_OFFSET 0
`define MDIO_ADVERTISE_RSVD3 32'h0000001f
`define MDIO_ADVERTISE_FULL_OFFSET 5
`define MDIO_ADVERTISE_FULL 32'h00000020
`define MDIO_ADVERTISE_HALF_OFFSET 6
`define MDIO_ADVERTISE_HALF 32'h00000040
`define MDIO_ADVERTISE_PAUSE_OFFSET 7
`define MDIO_ADVERTISE_PAUSE 32'h00000180
`define MDIO_ADVERTISE_RSVD2_OFFSET 9
`define MDIO_ADVERTISE_RSVD2 32'h00000e00
`define MDIO_ADVERTISE_RFAULT_OFFSET 12
`define MDIO_ADVERTISE_RFAULT 32'h00003000
`define MDIO_ADVERTISE_RSVD1_OFFSET 14
`define MDIO_ADVERTISE_RSVD1 32'h00004000
`define MDIO_ADVERTISE_NPAGE_OFFSET 15
`define MDIO_ADVERTISE_NPAGE 32'h00008000
`define ADDR_MDIO_LPA 7'h14
`define MDIO_LPA_RSVD3_OFFSET 0
`define MDIO_LPA_RSVD3 32'h0000001f
`define MDIO_LPA_FULL_OFFSET 5
`define MDIO_LPA_FULL 32'h00000020
`define MDIO_LPA_HALF_OFFSET 6
`define MDIO_LPA_HALF 32'h00000040
`define MDIO_LPA_PAUSE_OFFSET 7
`define MDIO_LPA_PAUSE 32'h00000180
`define MDIO_LPA_RSVD2_OFFSET 9
`define MDIO_LPA_RSVD2 32'h00000e00
`define MDIO_LPA_RFAULT_OFFSET 12
`define MDIO_LPA_RFAULT 32'h00003000
`define MDIO_LPA_LPACK_OFFSET 14
`define MDIO_LPA_LPACK 32'h00004000
`define MDIO_LPA_NPAGE_OFFSET 15
`define MDIO_LPA_NPAGE 32'h00008000
`define ADDR_MDIO_EXPANSION 7'h18
`define MDIO_EXPANSION_RSVD1_OFFSET 0
`define MDIO_EXPANSION_RSVD1 32'h00000001
`define MDIO_EXPANSION_LWCP_OFFSET 1
`define MDIO_EXPANSION_LWCP 32'h00000002
`define MDIO_EXPANSION_ENABLENPAGE_OFFSET 2
`define MDIO_EXPANSION_ENABLENPAGE 32'h00000004
`define MDIO_EXPANSION_RSVD2_OFFSET 3
`define MDIO_EXPANSION_RSVD2 32'h0000fff8
`define ADDR_MDIO_ESTATUS 7'h3c
`define MDIO_ESTATUS_RSVD1_OFFSET 0
`define MDIO_ESTATUS_RSVD1 32'h00000fff
`define MDIO_ESTATUS_1000_THALF_OFFSET 12
`define MDIO_ESTATUS_1000_THALF 32'h00001000
`define MDIO_ESTATUS_1000_TFULL_OFFSET 13
`define MDIO_ESTATUS_1000_TFULL 32'h00002000
`define MDIO_ESTATUS_1000_XHALF_OFFSET 14
`define MDIO_ESTATUS_1000_XHALF 32'h00004000
`define MDIO_ESTATUS_1000_XFULL_OFFSET 15
`define MDIO_ESTATUS_1000_XFULL 32'h00008000
`define ADDR_MDIO_WR_SPEC 7'h40
`define MDIO_WR_SPEC_TX_CAL_OFFSET 0
`define MDIO_WR_SPEC_TX_CAL 32'h00000001
`define MDIO_WR_SPEC_RX_CAL_STAT_OFFSET 1
`define MDIO_WR_SPEC_RX_CAL_STAT 32'h00000002
`define MDIO_WR_SPEC_CAL_CRST_OFFSET 2
`define MDIO_WR_SPEC_CAL_CRST 32'h00000004
`define MDIO_WR_SPEC_BSLIDE_OFFSET 4
`define MDIO_WR_SPEC_BSLIDE 32'h000001f0
`define ADDR_MDIO_ECTRL 7'h44
`define MDIO_ECTRL_LPBCK_VEC_OFFSET 0
`define MDIO_ECTRL_LPBCK_VEC 32'h00000007
`define MDIO_ECTRL_SFP_TX_FAULT_OFFSET 3
`define MDIO_ECTRL_SFP_TX_FAULT 32'h00000008
`define MDIO_ECTRL_SFP_LOSS_OFFSET 4
`define MDIO_ECTRL_SFP_LOSS 32'h00000010
`define MDIO_ECTRL_SFP_TX_DISABLE_OFFSET 5
`define MDIO_ECTRL_SFP_TX_DISABLE 32'h00000020
`define MDIO_ECTRL_TX_PRBS_SEL_OFFSET 8
`define MDIO_ECTRL_TX_PRBS_SEL 32'h00000700
`define ADDR_EP_ECR 7'h0
`define EP_ECR_PORTID_OFFSET 0
`define EP_ECR_PORTID 32'h0000001f
`define EP_ECR_RST_CNT_OFFSET 5
`define EP_ECR_RST_CNT 32'h00000020
`define EP_ECR_TX_EN_OFFSET 6
`define EP_ECR_TX_EN 32'h00000040
`define EP_ECR_RX_EN_OFFSET 7
`define EP_ECR_RX_EN 32'h00000080
`define EP_ECR_FEAT_VLAN_OFFSET 24
`define EP_ECR_FEAT_VLAN 32'h01000000
`define EP_ECR_FEAT_DMTD_OFFSET 25
`define EP_ECR_FEAT_DMTD 32'h02000000
`define EP_ECR_FEAT_PTP_OFFSET 26
`define EP_ECR_FEAT_PTP 32'h04000000
`define EP_ECR_FEAT_DPI_OFFSET 27
`define EP_ECR_FEAT_DPI 32'h08000000
`define ADDR_EP_TSCR 7'h4
`define EP_TSCR_EN_TXTS_OFFSET 0
`define EP_TSCR_EN_TXTS 32'h00000001
`define EP_TSCR_EN_RXTS_OFFSET 1
`define EP_TSCR_EN_RXTS 32'h00000002
`define EP_TSCR_CS_START_OFFSET 2
`define EP_TSCR_CS_START 32'h00000004
`define EP_TSCR_CS_DONE_OFFSET 3
`define EP_TSCR_CS_DONE 32'h00000008
`define EP_TSCR_RX_CAL_START_OFFSET 4
`define EP_TSCR_RX_CAL_START 32'h00000010
`define EP_TSCR_RX_CAL_RESULT_OFFSET 5
`define EP_TSCR_RX_CAL_RESULT 32'h00000020
`define ADDR_EP_RFCR 7'h8
`define EP_RFCR_A_RUNT_OFFSET 0
`define EP_RFCR_A_RUNT 32'h00000001
`define EP_RFCR_A_GIANT_OFFSET 1
`define EP_RFCR_A_GIANT 32'h00000002
`define EP_RFCR_A_HP_OFFSET 2
`define EP_RFCR_A_HP 32'h00000004
`define EP_RFCR_KEEP_CRC_OFFSET 3
`define EP_RFCR_KEEP_CRC 32'h00000008
`define EP_RFCR_HPAP_OFFSET 4
`define EP_RFCR_HPAP 32'h00000ff0
`define EP_RFCR_MRU_OFFSET 12
`define EP_RFCR_MRU 32'h03fff000
`define ADDR_EP_VCR0 7'hc
`define EP_VCR0_QMODE_OFFSET 0
`define EP_VCR0_QMODE 32'h00000003
`define EP_VCR0_FIX_PRIO_OFFSET 2
`define EP_VCR0_FIX_PRIO 32'h00000004
`define EP_VCR0_PRIO_VAL_OFFSET 4
`define EP_VCR0_PRIO_VAL 32'h00000070
`define EP_VCR0_PVID_OFFSET 16
`define EP_VCR0_PVID 32'h0fff0000
`define ADDR_EP_VCR1 7'h10
`define EP_VCR1_OFFSET_OFFSET 0
`define EP_VCR1_OFFSET 32'h000003ff
`define EP_VCR1_DATA_OFFSET 10
`define EP_VCR1_DATA 32'h0ffffc00
`define ADDR_EP_PFCR0 7'h14
`define EP_PFCR0_MM_ADDR_OFFSET 0
`define EP_PFCR0_MM_ADDR 32'h0000003f
`define EP_PFCR0_MM_WRITE_OFFSET 6
`define EP_PFCR0_MM_WRITE 32'h00000040
`define EP_PFCR0_ENABLE_OFFSET 7
`define EP_PFCR0_ENABLE 32'h00000080
`define EP_PFCR0_MM_DATA_MSB_OFFSET 8
`define EP_PFCR0_MM_DATA_MSB 32'hffffff00
`define ADDR_EP_PFCR1 7'h18
`define EP_PFCR1_MM_DATA_LSB_OFFSET 0
`define EP_PFCR1_MM_DATA_LSB 32'h00000fff
`define ADDR_EP_TCAR 7'h1c
`define EP_TCAR_PCP_MAP_OFFSET 0
`define EP_TCAR_PCP_MAP 32'h00ffffff
`define ADDR_EP_FCR 7'h20
`define EP_FCR_RXPAUSE_OFFSET 0
`define EP_FCR_RXPAUSE 32'h00000001
`define EP_FCR_TXPAUSE_OFFSET 1
`define EP_FCR_TXPAUSE 32'h00000002
`define EP_FCR_RXPAUSE_802_1Q_OFFSET 2
`define EP_FCR_RXPAUSE_802_1Q 32'h00000004
`define EP_FCR_TXPAUSE_802_1Q_OFFSET 3
`define EP_FCR_TXPAUSE_802_1Q 32'h00000008
`define EP_FCR_TX_THR_OFFSET 8
`define EP_FCR_TX_THR 32'h0000ff00
`define EP_FCR_TX_QUANTA_OFFSET 16
`define EP_FCR_TX_QUANTA 32'hffff0000
`define ADDR_EP_MACH 7'h24
`define ADDR_EP_MACL 7'h28
`define ADDR_EP_MDIO_CR 7'h2c
`define EP_MDIO_CR_DATA_OFFSET 0
`define EP_MDIO_CR_DATA 32'h0000ffff
`define EP_MDIO_CR_ADDR_OFFSET 16
`define EP_MDIO_CR_ADDR 32'h00ff0000
`define EP_MDIO_CR_RW_OFFSET 31
`define EP_MDIO_CR_RW 32'h80000000
`define ADDR_EP_MDIO_ASR 7'h30
`define EP_MDIO_ASR_RDATA_OFFSET 0
`define EP_MDIO_ASR_RDATA 32'h0000ffff
`define EP_MDIO_ASR_PHYAD_OFFSET 16
`define EP_MDIO_ASR_PHYAD 32'h00ff0000
`define EP_MDIO_ASR_READY_OFFSET 31
`define EP_MDIO_ASR_READY 32'h80000000
`define ADDR_EP_IDCODE 7'h34
`define ADDR_EP_DSR 7'h38
`define EP_DSR_LSTATUS_OFFSET 0
`define EP_DSR_LSTATUS 32'h00000001
`define EP_DSR_LACT_OFFSET 1
`define EP_DSR_LACT 32'h00000002
`define ADDR_EP_DMCR 7'h3c
`define EP_DMCR_EN_OFFSET 0
`define EP_DMCR_EN 32'h00000001
`define EP_DMCR_N_AVG_OFFSET 16
`define EP_DMCR_N_AVG 32'h0fff0000
`define ADDR_EP_DMSR 7'h40
`define EP_DMSR_PS_VAL_OFFSET 0
`define EP_DMSR_PS_VAL 32'h00ffffff
`define EP_DMSR_PS_RDY_OFFSET 24
`define EP_DMSR_PS_RDY 32'h01000000
`define ADDR_EP_INJ_CTRL 7'h44
`define EP_INJ_CTRL_PIC_CONF_IFG_OFFSET 0
`define EP_INJ_CTRL_PIC_CONF_IFG 32'h0000ffff
`define EP_INJ_CTRL_PIC_CONF_SEL_OFFSET 16
`define EP_INJ_CTRL_PIC_CONF_SEL 32'h00070000
`define EP_INJ_CTRL_PIC_CONF_VALID_OFFSET 19
`define EP_INJ_CTRL_PIC_CONF_VALID 32'h00080000
`define EP_INJ_CTRL_PIC_MODE_ID_OFFSET 20
`define EP_INJ_CTRL_PIC_MODE_ID 32'h00700000
`define EP_INJ_CTRL_PIC_MODE_VALID_OFFSET 23
`define EP_INJ_CTRL_PIC_MODE_VALID 32'h00800000
`define EP_INJ_CTRL_PIC_ENA_OFFSET 24
`define EP_INJ_CTRL_PIC_ENA 32'h01000000
`ifndef __ETH_PACKET_SVH
`define __ETH_PACKET_SVH
`include "simdrv_defs.svh"
typedef byte mac_addr_t[6];
typedef bit[11:0] vid_t;
typedef bit[2:0] pcp_t;
typedef enum
{
NONE = 0,
TX_FID,
RX_TIMESTAMP
} oob_type_t;
typedef struct {
bit [27:0] ts_r;
bit [3:0] ts_f;
bit [5:0] port_id;
bit [15:0] frame_id;
} wr_timestamp_t;
class EthPacket;
static const mac_addr_t dummy_mac = '{0,0,0,0,0,0} ;
static int _zero = 0;
static const int CMP_OOB = 1;
static const int CMP_STATUS = 2;
byte payload[];
int size;
mac_addr_t src, dst;
oob_type_t oob_type;
bit is_q;
bit is_hp;
bit has_smac;
bit has_crc;
bit error;
bit [15:0] ethertype;
bit [7:0] pclass;
vid_t vid;
pcp_t pcp;
oob_type_t oob;
wr_timestamp_t ts;
task set_size(int size);
payload = new[size](payload);
endtask
function new(int size = _zero);
// size = 0;
src = dummy_mac;
dst = dummy_mac;
is_q = 0;
is_hp = 0;
has_crc = 0;
oob_type = NONE;
payload = new[size](payload);
endfunction // new
task deserialize(byte data[]);
int i, hsize, psize;
if(data.size < 14)
begin
error = 1;
return;
end
for(i=0; i<6;i++)
begin
dst[i] = data[i];
src[i] = data [i+6];
end
has_crc = 0;
if(data[12] == 'h81 && data[13] == 'h00)
begin
is_q = 1;
hsize = 18;
ethertype = {data[16], data[17]};
vid = ((int'(data[14]) << 8) | data[15]) & 12'hfff;
pcp = data[14] >> 5;
end else begin
is_q = 0;
hsize = 14;
ethertype = {data[12], data[13]};
end
psize = data.size() - hsize;
if(psize <= 0)
begin
error = 1;
return;
end
payload = new[psize];
for(i=0;i<data.size() - hsize;i++)
payload[i] = data[hsize + i];
size = data.size;
// error = 0;
endtask
task automatic serialize(ref byte data[]);
int i, hsize;
hsize = is_q ? 18 : 14;
data = new[payload.size() + hsize](data);
for(i=0; i<6;i++)
begin
data[i] = dst[i];
data[i + 6] = src[i];
end
if(is_q)
begin
data [12] = 8'h81;
data [13] = 8'h00;
data [14] = {pcp, 1'b0, vid[11:8]};
data [15] = vid[7:0];
data [16] = ethertype[15:8];
data [17] = ethertype[7:0];
end else begin
data[12] = ethertype [15:8];
data[13] = ethertype [7:0];
end
for (i=0; i<payload.size(); i++)
data[i + hsize] = payload[i];
endtask // serialize
function bit equal(ref EthPacket b, input int flags = 0);
if(src != b.src || dst != b.dst || ethertype != b.ethertype)
begin
$display("notequal: hdr");
return 0;
end
if(is_q ^ b.is_q)
begin
$display("notequal: q");
return 0;
end
if(is_q && (vid != b.vid || pcp != b.pcp))
return 0;
if(payload != b.payload)
begin
$display("notequal: payload");
return 0;
end
// return 0;
if(flags & CMP_STATUS)
if(error ^ b.error)
return 0;
if(flags & CMP_OOB) begin
if (b.oob_type != oob_type)
return 0;
if(oob_type == TX_FID && (b.ts.frame_id != ts.frame_id))
return 0;
end
return 1;
endfunction // equal
task copy(ref EthPacket b);
endtask // copy
task hexdump(byte buffer []);
string str;
int size ;
int i;
int offset = 0;
const int per_row = 16;
size = buffer.size();
while(size > 0)
begin
int n;
n = (size > per_row ? per_row : size);
$sformat(str,"+%03x: ", offset);
for(i=0;i<n;i++) $sformat(str,"%s%s%02x", str, (i==(per_row/2)?"-":" "), buffer[offset + i]);
$display(str);
offset = offset + n;
size = size - n;
end
endtask // hexdump
task dump(int full = _zero);
string str, tmp;
int t;
if(is_q)
$sformat(str, "802.1q [VID %5d/PCP %d] ", vid, pcp);
else
str = "802.1 ";
$sformat(str, "%s DST [%02x:%02x:%02x:%02x:%02x:%02x] SRC: [%02x:%02x:%02x:%02x:%02x:%02x] Type = 0x%04x size = %d F:(%s%s)", str, dst[0],dst[1],dst[2],dst[3],dst[4],dst[5], src[0],src[1],src[2],src[3],src[4], src[5], ethertype, (is_q ? 18 : 14) + payload.size(),
is_hp ? "H" : " ", has_crc ? "C" : " ");
if(oob_type == TX_FID)
begin
$sformat(tmp, "TxOOB: %x", ts.frame_id);
str = {str, tmp};
end
$display(str);
hexdump(payload);
endtask // dump
endclass // EthPacket
class EthPacketGenerator;
protected EthPacket template;
protected int min_size, max_size;
protected int seed;
static const int SMAC = (1<<0);
static const int DMAC = (1<<1);
static const int ETHERTYPE = (1<<2);
static const int VID = (1<<3);
static const int PCP = (1<<4);
static const int PAYLOAD = (1<<5);
static const int SEQ_PAYLOAD = (1<<7);
static const int SEQ_ID = (1<<10);
static const int TX_OOB = (1<<6);
static const int EVEN_LENGTH = (1<<8);
static const int RX_OOB = (1<<9);
static const int ALL = SMAC | DMAC | VID | ETHERTYPE | PCP | PAYLOAD ;
protected int r_flags;
protected int m_current_frame_id;
protected int cur_seq_id;
function new();
r_flags =ALL;
min_size = 64;
max_size = 128;
m_current_frame_id = 0;
template = new;
cur_seq_id = 0;
endfunction // new
task set_randomization(int flags);
r_flags = flags;
endtask // randomize
typedef byte dyn_array[];
protected function dyn_array random_bvec(int size);
byte v[];
int i;
// $display("RandomBVEC %d", size);
v = new[size](v);
for(i=0;i<size;i++)
v[i] = $dist_uniform(seed, 0, 256);
return v;
endfunction // random_bvec
task set_seed(int seed_);
seed = seed_;
endtask // set_seed
function int get_seed();
return seed;
endfunction // get_seed
protected function dyn_array seq_payload(int size);
byte v[];
int i;
v = new[size](v);
for(i=0;i<size;i++)
v[i] = i;
return v;
endfunction // random_bvec
function automatic EthPacket gen(int set_len = 0);
EthPacket pkt;
int len;
pkt = new;
if (r_flags & SMAC) pkt.src = random_bvec(6); else pkt.src = template.src;
if (r_flags & DMAC) pkt.dst = random_bvec(6); else pkt.dst = template.dst;
pkt.ethertype = (r_flags & ETHERTYPE ? $dist_uniform(seed, 0, 1<<16) : template.ethertype);
pkt.is_q = template.is_q;
pkt.vid = template.vid;
pkt.pcp = template.pcp;
pkt.has_smac = template.has_smac;
if(set_len > 0) len = set_len;
else len = $dist_uniform(seed, min_size, max_size);
if((len & 1) && (r_flags & EVEN_LENGTH))
len++;
if(r_flags & PAYLOAD) pkt.payload = random_bvec(len);
else if(r_flags & SEQ_PAYLOAD) pkt.payload = seq_payload(len);
else pkt.payload = template.payload;
if(r_flags & SEQ_ID)
begin
pkt.payload[0] = cur_seq_id & 'hff;
pkt.payload[1] = (cur_seq_id>>8) & 'hff;
pkt.payload[2] = (cur_seq_id>>16) & 'hff;
pkt.payload[3] = (cur_seq_id>>24) & 'hff;
cur_seq_id++;
end
if(r_flags & TX_OOB)
begin
pkt.ts.frame_id = m_current_frame_id++;
pkt.oob_type = TX_FID;
end
pkt.size = len + 14; //payload + header
return pkt;
endfunction
task set_template(EthPacket pkt);
template = pkt;
endtask // set_template
task set_size(int smin, int smax);
min_size = smin;
max_size = smax;
endtask // set_size
endclass // EthPacketGenerator
virtual class EthPacketSink;
static int _null = 0;
pure virtual function int poll();
virtual function int permanent_stall_enable(); endfunction
virtual function int permanent_stall_disable(); endfunction
pure virtual task recv(ref EthPacket pkt, ref int result = _null);
endclass // EthPacketSink
virtual class EthPacketSource;
static int _null = 0;
pure virtual task send(ref EthPacket pkt, ref int result = _null);
endclass // PacketSource
`endif
//
// Title : Software Wishbone master unit for testbenches
//
// File : if_wishbone.sv
// Author : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
// Created : Tue Mar 23 12:19:36 2010
// Standard : SystemVerilog
//
// Default values of certain WB parameters.
`include "simdrv_defs.sv"
interface IWishboneClassicMaster
(
input clk_i,
input rst_n_i
);
parameter g_data_width = 32;
parameter g_addr_width = 32;
/* Interface signals */
logic [g_addr_width - 1 : 0] adr;
logic [g_data_width - 1 : 0] dat_o;
logic [3 : 0] sel; // FIXME: 32-bit only
wire [g_data_width - 1 : 0] dat_i;
wire ack;
logic cyc;
logic stb;
logic we;
wire stall;
initial begin
adr = 0;
dat_o = 0;
sel = 0;
cyc = 0;
stb = 0;
we = 0;
end
time last_access_t = 0;
reg [g_data_width-1:0] dummy;
// enables/disables displaying information about each read/write operation.
int tb_verbose = 0;
task verbose(int onoff);
tb_verbose = onoff;
endtask // wb_verbose
task classic_single_rw_generic;
input [g_addr_width - 1 : 0] trans_addr;
input [g_data_width - 1 : 0] trans_wdata;
output [g_data_width - 1 : 0] trans_rdata;
input rw;
input [3:0] size;
begin : rw_generic_main
if(tb_verbose && rw)
$display("WB write %s: addr %x, data %x",
(size==1?"byte":((size==2)?"short":"int")),
trans_addr, trans_wdata);
if($time != last_access_t) begin
@(posedge clk_i);
end
stb<=1;
cyc<=1;
adr <= {2'b00, trans_addr[31:2]};
we <= rw;
if(rw) begin
case(size)
4: begin dat_o<=trans_wdata; sel <= 4'b1111; end
2: begin
if(adr[1]) begin
dat_o[31:16] <= trans_wdata[15:0];
sel <= 4'b1100;
end else begin
dat_o[15:0] <= trans_wdata[15:0];
sel <= 4'b0011;
end
end
1: begin
case(adr[1:0])
0: begin dat_o[31:24] <= trans_wdata[7:0]; sel <= 4'b1000; end
1: begin dat_o[23:16] <= trans_wdata[7:0]; sel <= 4'b0100; end
2: begin dat_o[15:8] <= trans_wdata[7:0]; sel <= 4'b0010; end
3: begin dat_o[7:0] <= trans_wdata[7:0]; sel <= 4'b0001; end
endcase // case(addr[1:0])
end
endcase // case(size)
end // if (rw)
@(posedge clk_i);
if(ack == 0) begin
while(ack == 0) begin @(posedge clk_i); end
end
trans_rdata = dat_i;
cyc <= 0;
we<=0;
stb<=0;
if(tb_verbose && !rw)
$display("WB read %s: addr %x, data %x",
(size==1?"byte":((size==2)?"short":"int")),
trans_addr, trans_rdata);
last_access_t = $time;
end
endtask // rw_generic
task write32;
input [g_addr_width - 1 : 0] addr;
input [31 : 0] data_i;
begin
classic_single_rw_generic(addr, data_i, dummy, 1, 4);
end
endtask // write32
task read32;
input [g_addr_width - 1 : 0] addr;
output [31 : 0] data_o;
begin : read32_body
reg [g_data_width - 1 : 0] rval;
classic_single_rw_generic(addr, 0, rval, 0, 4);
data_o = rval[31:0];
end
endtask // write32
modport master
(
output adr,
output dat_o,
output sel,
output cyc,
output stb,
output we,
input ack,
input dat_i,
input stall);
endinterface // IWishbone
interface IWishboneLink;
parameter g_data_width = 32;
parameter g_addr_width = 32;
wire [g_addr_width - 1 : 0] adr;
wire [g_data_width - 1 : 0] dat_o;
wire [g_data_width - 1 : 0] dat_i;
wire [(g_data_width/8)-1 : 0] sel;
wire ack;
wire stall;
wire err;
wire rty;
wire cyc;
wire stb;
wire we;
modport slave
(
output adr,
output dat_o,
input dat_i,
output sel,
output cyc,
output stb,
output we,
input ack,
input stall,
input err,
input rty
);
modport master
(
input adr,
input dat_o,
output dat_i,
input sel,
input cyc,
input stb,
input we,
output ack,
output stall,
output err,
output rty
);
endinterface // IWishboneLink
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`define ADDR_LBK_MCR 5'h0
`define LBK_MCR_ENA_OFFSET 0
`define LBK_MCR_ENA 32'h00000001
`define LBK_MCR_CLR_OFFSET 1
`define LBK_MCR_CLR 32'h00000002
`define LBK_MCR_FDMAC_OFFSET 2
`define LBK_MCR_FDMAC 32'h00000004
`define ADDR_LBK_DMAC_L 5'h4
`define ADDR_LBK_DMAC_H 5'h8
`define ADDR_LBK_RCV_CNT 5'hc
`define ADDR_LBK_DRP_CNT 5'h10
`define ADDR_LBK_FWD_CNT 5'h14
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`define ADDR_SI570_RFREQL 4'h0
`define ADDR_SI570_RFREQH 4'h4
`define ADDR_SI570_GPSR 4'h8
`define SI570_GPSR_SCL_OFFSET 0
`define SI570_GPSR_SCL 32'h00000001
`define SI570_GPSR_SDA_OFFSET 1
`define SI570_GPSR_SDA 32'h00000002
`define ADDR_SI570_GPCR 4'hc
`define SI570_GPCR_SCL_OFFSET 0
`define SI570_GPCR_SCL 32'h00000001
`define SI570_GPCR_SDA_OFFSET 1
`define SI570_GPCR_SDA 32'h00000002
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version:1
57656254616c6b5472616e736d697373696f6e417474656d70746564:8
6d6f64655f636f756e7465727c4755494d6f6465:15
eof:
version:1
73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
eof:2511430288
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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