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Multi-channel Time Interval Counter and fine delay generator
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Multi-channel Time Interval Counter and fine delay generator
Commits
f980ad4e
Commit
f980ad4e
authored
Oct 18, 2016
by
Nicolas Boucquey
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...ard_test.sim/sim_1/behav/xsim.dir/xil_defaultlib/glbl.sdb
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-0
ila_1.sdb
...rd_test.sim/sim_1/behav/xsim.dir/xil_defaultlib/ila_1.sdb
+0
-0
memory_loader_pkg.vdb
...sim_1/behav/xsim.dir/xil_defaultlib/memory_loader_pkg.vdb
+0
-0
processing_system7_v5_5_processing_system7.sdb
...defaultlib/processing_system7_v5_5_processing_system7.sdb
+0
-0
processing_system_zedboard.sdb
...av/xsim.dir/xil_defaultlib/processing_system_zedboard.sdb
+0
-0
tg_wbgen2_pkg.vdb
...sim/sim_1/behav/xsim.dir/xil_defaultlib/tg_wbgen2_pkg.vdb
+0
-0
trigger_generator.vdb
...sim_1/behav/xsim.dir/xil_defaultlib/trigger_generator.vdb
+0
-0
trigger_generator_wb.vdb
..._1/behav/xsim.dir/xil_defaultlib/trigger_generator_wb.vdb
+0
-0
wb_gpio_port.vdb
....sim/sim_1/behav/xsim.dir/xil_defaultlib/wb_gpio_port.vdb
+0
-0
wb_slave_adapter.vdb
.../sim_1/behav/xsim.dir/xil_defaultlib/wb_slave_adapter.vdb
+0
-0
wishbone_pkg.vdb
....sim/sim_1/behav/xsim.dir/xil_defaultlib/wishbone_pkg.vdb
+0
-0
xil_defaultlib.rlx
...im/sim_1/behav/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
+40
-0
xpm_memory_base.sdb
...m/sim_1/behav/xsim.dir/xil_defaultlib/xpm_memory_base.sdb
+0
-0
xpm_memory_dpdistram.sdb
..._1/behav/xsim.dir/xil_defaultlib/xpm_memory_dpdistram.sdb
+0
-0
xpm_memory_dprom.sdb
.../sim_1/behav/xsim.dir/xil_defaultlib/xpm_memory_dprom.sdb
+0
-0
xpm_memory_sdpram.sdb
...sim_1/behav/xsim.dir/xil_defaultlib/xpm_memory_sdpram.sdb
+0
-0
xpm_memory_spram.sdb
.../sim_1/behav/xsim.dir/xil_defaultlib/xpm_memory_spram.sdb
+0
-0
xpm_memory_sprom.sdb
.../sim_1/behav/xsim.dir/xil_defaultlib/xpm_memory_sprom.sdb
+0
-0
xpm_memory_tdpram.sdb
...sim_1/behav/xsim.dir/xil_defaultlib/xpm_memory_tdpram.sdb
+0
-0
xprocessing_system_zedboard.vdb
...v/xsim.dir/xil_defaultlib/xprocessing_system_zedboard.vdb
+0
-0
xwb_axi4lite_bridge.vdb
...m_1/behav/xsim.dir/xil_defaultlib/xwb_axi4lite_bridge.vdb
+0
-0
xwb_crossbar.vdb
....sim/sim_1/behav/xsim.dir/xil_defaultlib/xwb_crossbar.vdb
+0
-0
xwb_gpio_port.vdb
...sim/sim_1/behav/xsim.dir/xil_defaultlib/xwb_gpio_port.vdb
+0
-0
zboard_top.vdb
...st.sim/sim_1/behav/xsim.dir/xil_defaultlib/zboard_top.vdb
+0
-0
vcomponents.vdb
...edboard_test.sim/sim_1/behav/xsim.dir/xpm/vcomponents.vdb
+0
-0
xpm.rlx
...d_test/zedboard_test.sim/sim_1/behav/xsim.dir/xpm/xpm.rlx
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-0
xsim.svtype
...d_test/zedboard_test.sim/sim_1/behav/xsim.dir/xsim.svtype
+0
-0
xsim.ini
.../syn/zedboard_test/zedboard_test.sim/sim_1/behav/xsim.ini
+2
-0
xvhdl.log
...syn/zedboard_test/zedboard_test.sim/sim_1/behav/xvhdl.log
+50
-0
xvhdl.pb
.../syn/zedboard_test/zedboard_test.sim/sim_1/behav/xvhdl.pb
+0
-0
xvlog.log
...syn/zedboard_test/zedboard_test.sim/sim_1/behav/xvlog.log
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-0
xvlog.pb
.../syn/zedboard_test/zedboard_test.sim/sim_1/behav/xvlog.pb
+0
-0
.processing_system7_0.xcix.lock
...st.srcs/sources_1/ip/.Xil/.processing_system7_0.xcix.lock
+0
-0
blk_mem_gen_v8_3.vhd
...es_1/ip/ila_1/blk_mem_gen_v8_3_3/hdl/blk_mem_gen_v8_3.vhd
+297
-0
blk_mem_gen_v8_3_vhsyn_rfs.vhd
...a_1/blk_mem_gen_v8_3_3/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
+192617
-0
ila_v6_1_changelog.txt
...d_test.srcs/sources_1/ip/ila_1/doc/ila_v6_1_changelog.txt
+132
-0
fifo_generator_v13_0.vhd
...ila_1/fifo_generator_v13_0_3/hdl/fifo_generator_v13_0.vhd
+1200
-0
fifo_generator_v13_0_vhsyn_rfs.vhd
..._generator_v13_0_3/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd
+29144
-0
ila_1.dcp
...oard_test/zedboard_test.srcs/sources_1/ip/ila_1/ila_1.dcp
+0
-0
ila_1.veo
...oard_test/zedboard_test.srcs/sources_1/ip/ila_1/ila_1.veo
+76
-0
ila_1.xci
...oard_test/zedboard_test.srcs/sources_1/ip/ila_1/ila_1.xci
+3181
-0
ila_1.xml
...oard_test/zedboard_test.srcs/sources_1/ip/ila_1/ila_1.xml
+74481
-0
ila_1_ooc.xdc
..._test/zedboard_test.srcs/sources_1/ip/ila_1/ila_1_ooc.xdc
+57
-0
ila_1_sim_netlist.v
...zedboard_test.srcs/sources_1/ip/ila_1/ila_1_sim_netlist.v
+47719
-0
ila_1_sim_netlist.vhdl
...board_test.srcs/sources_1/ip/ila_1/ila_1_sim_netlist.vhdl
+68780
-0
ila_1_stub.v
...d_test/zedboard_test.srcs/sources_1/ip/ila_1/ila_1_stub.v
+28
-0
ila_1_stub.vhdl
...est/zedboard_test.srcs/sources_1/ip/ila_1/ila_1_stub.vhdl
+38
-0
ila.xdc
...test.srcs/sources_1/ip/ila_1/ila_v6_1/constraints/ila.xdc
+79
-0
ila_v6_1_syn_rfs.v
...srcs/sources_1/ip/ila_1/ila_v6_1_1/hdl/ila_v6_1_syn_rfs.v
+3496
-0
ila_v6_1_1_ila_in_ports_inc.v
...la_1/ila_v6_1_1/hdl/verilog/ila_v6_1_1_ila_in_ports_inc.v
+800
-0
ila_v6_1_1_ila_lib_function.v
...la_1/ila_v6_1_1/hdl/verilog/ila_v6_1_1_ila_lib_function.v
+118
-0
ila_v6_1_1_ila_localparam_inc.v
..._1/ila_v6_1_1/hdl/verilog/ila_v6_1_1_ila_localparam_inc.v
+12417
-0
ila_v6_1_1_ila_param_inc.v
...p/ila_1/ila_v6_1_1/hdl/verilog/ila_v6_1_1_ila_param_inc.v
+1931
-0
ila_v6_1_1_ila_ver_inc.v
.../ip/ila_1/ila_v6_1_1/hdl/verilog/ila_v6_1_1_ila_ver_inc.v
+159
-0
ltlib_v1_0_vl_rfs.v
...s/sources_1/ip/ila_1/ltlib_v1_0_0/hdl/ltlib_v1_0_vl_rfs.v
+1181
-0
ltlib_v1_0_0_lib_function.v
...la_1/ltlib_v1_0_0/hdl/verilog/ltlib_v1_0_0_lib_function.v
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-0
ltlib_v1_0_0_ver_inc.v
.../ip/ila_1/ltlib_v1_0_0/hdl/verilog/ltlib_v1_0_0_ver_inc.v
+113
-0
ila_1.v
...rd_test/zedboard_test.srcs/sources_1/ip/ila_1/sim/ila_1.v
+76
-0
ila_1.v
..._test/zedboard_test.srcs/sources_1/ip/ila_1/synth/ila_1.v
+4251
-0
xsdbm_v1_1_3_icon2xsdb_inc.v
...a_1/xsdbm_v1_1_3/hdl/verilog/xsdbm_v1_1_3_icon2xsdb_inc.v
+93
-0
xsdbm_v1_1_3_icon_inc.v
...ip/ila_1/xsdbm_v1_1_3/hdl/verilog/xsdbm_v1_1_3_icon_inc.v
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-0
xsdbm_v1_1_3_inc.v
...es_1/ip/ila_1/xsdbm_v1_1_3/hdl/verilog/xsdbm_v1_1_3_inc.v
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-0
xsdbm_v1_1_xsdbm.v
...es_1/ip/ila_1/xsdbm_v1_1_3/hdl/verilog/xsdbm_v1_1_xsdbm.v
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-0
xsdbm_v1_1_vl_rfs.v
...s/sources_1/ip/ila_1/xsdbm_v1_1_3/hdl/xsdbm_v1_1_vl_rfs.v
+2235
-0
xsdbs_v1_0_2_icon2xsdb_inc.v
...a_1/xsdbs_v1_0_2/hdl/verilog/xsdbs_v1_0_2_icon2xsdb_inc.v
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-0
xsdbs_v1_0_2_inc.v
...es_1/ip/ila_1/xsdbs_v1_0_2/hdl/verilog/xsdbs_v1_0_2_inc.v
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-0
xsdbs_v1_0_vl_rfs.v
...s/sources_1/ip/ila_1/xsdbs_v1_0_2/hdl/xsdbs_v1_0_vl_rfs.v
+498
-0
blk_mem_gen_v8_3.vhd
..._1/ip/ila_1_1/blk_mem_gen_v8_3_3/hdl/blk_mem_gen_v8_3.vhd
+297
-0
blk_mem_gen_v8_3_vhsyn_rfs.vhd
...1_1/blk_mem_gen_v8_3_3/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
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-0
fifo_generator_v13_0.vhd
...a_1_1/fifo_generator_v13_0_3/hdl/fifo_generator_v13_0.vhd
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-0
fifo_generator_v13_0_vhsyn_rfs.vhd
..._generator_v13_0_3/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd
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-0
ila_1.xci
...rd_test/zedboard_test.srcs/sources_1/ip/ila_1_1/ila_1.xci
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-0
ila_1.xml
...rd_test/zedboard_test.srcs/sources_1/ip/ila_1_1/ila_1.xml
+74359
-0
ila_1_ooc.xdc
...est/zedboard_test.srcs/sources_1/ip/ila_1_1/ila_1_ooc.xdc
+57
-0
ila.xdc
...st.srcs/sources_1/ip/ila_1_1/ila_v6_1/constraints/ila.xdc
+79
-0
ila_v6_1_syn_rfs.v
...cs/sources_1/ip/ila_1_1/ila_v6_1_1/hdl/ila_v6_1_syn_rfs.v
+3496
-0
ila_v6_1_1_ila_in_ports_inc.v
..._1_1/ila_v6_1_1/hdl/verilog/ila_v6_1_1_ila_in_ports_inc.v
+800
-0
ila_v6_1_1_ila_lib_function.v
..._1_1/ila_v6_1_1/hdl/verilog/ila_v6_1_1_ila_lib_function.v
+118
-0
ila_v6_1_1_ila_localparam_inc.v
..._1/ila_v6_1_1/hdl/verilog/ila_v6_1_1_ila_localparam_inc.v
+12417
-0
ila_v6_1_1_ila_param_inc.v
...ila_1_1/ila_v6_1_1/hdl/verilog/ila_v6_1_1_ila_param_inc.v
+1931
-0
ila_v6_1_1_ila_ver_inc.v
...p/ila_1_1/ila_v6_1_1/hdl/verilog/ila_v6_1_1_ila_ver_inc.v
+159
-0
ltlib_v1_0_vl_rfs.v
...sources_1/ip/ila_1_1/ltlib_v1_0_0/hdl/ltlib_v1_0_vl_rfs.v
+1181
-0
ltlib_v1_0_0_lib_function.v
..._1_1/ltlib_v1_0_0/hdl/verilog/ltlib_v1_0_0_lib_function.v
+116
-0
ltlib_v1_0_0_ver_inc.v
...p/ila_1_1/ltlib_v1_0_0/hdl/verilog/ltlib_v1_0_0_ver_inc.v
+113
-0
ila_1.v
...est/zedboard_test.srcs/sources_1/ip/ila_1_1/synth/ila_1.v
+4241
-0
xsdbm_v1_1_3_icon2xsdb_inc.v
...1_1/xsdbm_v1_1_3/hdl/verilog/xsdbm_v1_1_3_icon2xsdb_inc.v
+93
-0
xsdbm_v1_1_3_icon_inc.v
.../ila_1_1/xsdbm_v1_1_3/hdl/verilog/xsdbm_v1_1_3_icon_inc.v
+82
-0
xsdbm_v1_1_3_inc.v
..._1/ip/ila_1_1/xsdbm_v1_1_3/hdl/verilog/xsdbm_v1_1_3_inc.v
+114
-0
xsdbm_v1_1_xsdbm.v
..._1/ip/ila_1_1/xsdbm_v1_1_3/hdl/verilog/xsdbm_v1_1_xsdbm.v
+2301
-0
xsdbm_v1_1_vl_rfs.v
...sources_1/ip/ila_1_1/xsdbm_v1_1_3/hdl/xsdbm_v1_1_vl_rfs.v
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-0
xsdbs_v1_0_2_icon2xsdb_inc.v
...1_1/xsdbs_v1_0_2/hdl/verilog/xsdbs_v1_0_2_icon2xsdb_inc.v
+93
-0
xsdbs_v1_0_2_inc.v
..._1/ip/ila_1_1/xsdbs_v1_0_2/hdl/verilog/xsdbs_v1_0_2_inc.v
+114
-0
xsdbs_v1_0_vl_rfs.v
...sources_1/ip/ila_1_1/xsdbs_v1_0_2/hdl/xsdbs_v1_0_vl_rfs.v
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-0
processing_system7_0.xcix
...zedboard_test.srcs/sources_1/ip/processing_system7_0.xcix
+0
-0
zedboard_test.xpr
.../zedboard-test-master/syn/zedboard_test/zedboard_test.xpr
+614
-0
Makefile
Gateware/zedboard-test-master/testbench/adc_core/Makefile
+1232
-0
Manifest.py
Gateware/zedboard-test-master/testbench/adc_core/Manifest.py
+14
-0
ad9263_model.sv
...e/zedboard-test-master/testbench/adc_core/ad9263_model.sv
+73
-0
axi4_lite_master.sv
...dboard-test-master/testbench/adc_core/axi4_lite_master.sv
+264
-0
glbl.v
Gateware/zedboard-test-master/testbench/adc_core/glbl.v
+66
-0
main.sv
Gateware/zedboard-test-master/testbench/adc_core/main.sv
+200
-0
run.do
Gateware/zedboard-test-master/testbench/adc_core/run.do
+9
-0
wave.do
Gateware/zedboard-test-master/testbench/adc_core/wave.do
+105
-0
d3s_acq_buffer_wb.vh
...dboard-test-master/testbench/include/d3s_acq_buffer_wb.vh
+10
-0
trigger_generator_wb.vh
...ard-test-master/testbench/include/trigger_generator_wb.vh
+15
-0
zboard_test.xdc
...ware/zedboard-test-master/top/zboard_test/zboard_test.xdc
+40
-0
zboard_top.vhd
Gateware/zedboard-test-master/top/zboard_test/zboard_top.vhd
+212
-0
devmem.py
Scripts/dataAcquisition/devmem.py
+283
-0
tdc_test3.py
Scripts/dataAcquisition/tdc_test3.py
+349
-0
ADCSimuJitter.py
Scripts/simulations/ADCSimuJitter.py
+0
-0
No files found.
Gateware/zedboard-test-master/.gitignore
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*.*\#
\#*
.\#*
*.*~
work
*.wlf
*.vstf
*.patch
modelsim.ini
*.html
*.h
*.o
*.bin
*.elf
\ No newline at end of file
Gateware/zedboard-test-master/.gitmodules
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[submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
Gateware/zedboard-test-master/platform/zynq/processing_system7_v5_5_processing_system7.v
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instead.
Gateware/zedboard-test-master/platform/zynq/processing_system_zedboard.v
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Gateware/zedboard-test-master/platform/zynq/xprocessing_system_zedboard.vhd
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View file @
f980ad4e
-- This VHDL was converted from Verilog using the
-- Icarus Verilog VHDL Code Generator 0.9.7 (v0_9_7)
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
axi4_pkg
.
all
;
entity
xprocessing_system_zedboard
is
port
(
DDR_Addr
:
inout
std_logic_vector
(
14
downto
0
);
DDR_BankAddr
:
inout
std_logic_vector
(
2
downto
0
);
DDR_CAS_n
:
inout
std_logic
;
DDR_CKE
:
inout
std_logic
;
DDR_CS_n
:
inout
std_logic
;
DDR_Clk
:
inout
std_logic
;
DDR_Clk_n
:
inout
std_logic
;
DDR_DM
:
inout
std_logic_vector
(
3
downto
0
);
DDR_DQ
:
inout
std_logic_vector
(
31
downto
0
);
DDR_DQS
:
inout
std_logic_vector
(
3
downto
0
);
DDR_DQS_n
:
inout
std_logic_vector
(
3
downto
0
);
DDR_DRSTB
:
inout
std_logic
;
DDR_ODT
:
inout
std_logic
;
DDR_RAS_n
:
inout
std_logic
;
DDR_VRN
:
inout
std_logic
;
DDR_VRP
:
inout
std_logic
;
DDR_WEB
:
inout
std_logic
;
FCLK_CLK0
:
out
std_logic
;
FCLK_RESET0_N
:
out
std_logic
;
MIO
:
inout
std_logic_vector
(
53
downto
0
);
m_axi_gp0_aclk_i
:
in
std_logic
;
m_axi_gp0_o
:
out
t_axi4_lite_master_out_32
;
m_axi_gp0_i
:
in
t_axi4_lite_master_in_32
;
PS_CLK
:
inout
std_logic
;
PS_PORB
:
inout
std_logic
;
PS_SRSTB
:
inout
std_logic
;
TTC0_WAVE0_OUT
:
out
std_logic
;
TTC0_WAVE1_OUT
:
out
std_logic
;
TTC0_WAVE2_OUT
:
out
std_logic
;
USB0_PORT_INDCTL
:
out
std_logic_vector
(
1
downto
0
);
USB0_VBUS_PWRFAULT
:
in
std_logic
;
USB0_VBUS_PWRSELECT
:
out
std_logic
);
end
entity
xprocessing_system_zedboard
;
architecture
wrapper
of
xprocessing_system_zedboard
is
component
processing_system_zedboard
is
port
(
DDR_Addr
:
inout
std_logic_vector
(
14
downto
0
);
DDR_BankAddr
:
inout
std_logic_vector
(
2
downto
0
);
DDR_CAS_n
:
inout
std_logic
;
DDR_CKE
:
inout
std_logic
;
DDR_CS_n
:
inout
std_logic
;
DDR_Clk
:
inout
std_logic
;
DDR_Clk_n
:
inout
std_logic
;
DDR_DM
:
inout
std_logic_vector
(
3
downto
0
);
DDR_DQ
:
inout
std_logic_vector
(
31
downto
0
);
DDR_DQS
:
inout
std_logic_vector
(
3
downto
0
);
DDR_DQS_n
:
inout
std_logic_vector
(
3
downto
0
);
DDR_DRSTB
:
inout
std_logic
;
DDR_ODT
:
inout
std_logic
;
DDR_RAS_n
:
inout
std_logic
;
DDR_VRN
:
inout
std_logic
;
DDR_VRP
:
inout
std_logic
;
DDR_WEB
:
inout
std_logic
;
FCLK_CLK0
:
out
std_logic
;
FCLK_RESET0_N
:
out
std_logic
;
MIO
:
inout
std_logic_vector
(
53
downto
0
);
M_AXI_GP0_ACLK
:
in
std_logic
;
M_AXI_GP0_ARADDR
:
out
std_logic_vector
(
31
downto
0
);
M_AXI_GP0_ARBURST
:
out
std_logic_vector
(
1
downto
0
);
M_AXI_GP0_ARCACHE
:
out
std_logic_vector
(
3
downto
0
);
M_AXI_GP0_ARID
:
out
std_logic_vector
(
11
downto
0
);
M_AXI_GP0_ARLEN
:
out
std_logic_vector
(
3
downto
0
);
M_AXI_GP0_ARLOCK
:
out
std_logic_vector
(
1
downto
0
);
M_AXI_GP0_ARPROT
:
out
std_logic_vector
(
2
downto
0
);
M_AXI_GP0_ARQOS
:
out
std_logic_vector
(
3
downto
0
);
M_AXI_GP0_ARREADY
:
in
std_logic
;
M_AXI_GP0_ARSIZE
:
out
std_logic_vector
(
2
downto
0
);
M_AXI_GP0_ARVALID
:
out
std_logic
;
M_AXI_GP0_AWADDR
:
out
std_logic_vector
(
31
downto
0
);
M_AXI_GP0_AWBURST
:
out
std_logic_vector
(
1
downto
0
);
M_AXI_GP0_AWCACHE
:
out
std_logic_vector
(
3
downto
0
);
M_AXI_GP0_AWID
:
out
std_logic_vector
(
11
downto
0
);
M_AXI_GP0_AWLEN
:
out
std_logic_vector
(
3
downto
0
);
M_AXI_GP0_AWLOCK
:
out
std_logic_vector
(
1
downto
0
);
M_AXI_GP0_AWPROT
:
out
std_logic_vector
(
2
downto
0
);
M_AXI_GP0_AWQOS
:
out
std_logic_vector
(
3
downto
0
);
M_AXI_GP0_AWREADY
:
in
std_logic
;
M_AXI_GP0_AWSIZE
:
out
std_logic_vector
(
2
downto
0
);
M_AXI_GP0_AWVALID
:
out
std_logic
;
M_AXI_GP0_BID
:
in
std_logic_vector
(
11
downto
0
);
M_AXI_GP0_BREADY
:
out
std_logic
;
M_AXI_GP0_BRESP
:
in
std_logic_vector
(
1
downto
0
);
M_AXI_GP0_BVALID
:
in
std_logic
;
M_AXI_GP0_RDATA
:
in
std_logic_vector
(
31
downto
0
);
M_AXI_GP0_RID
:
in
std_logic_vector
(
11
downto
0
);
M_AXI_GP0_RLAST
:
in
std_logic
;
M_AXI_GP0_RREADY
:
out
std_logic
;
M_AXI_GP0_RRESP
:
in
std_logic_vector
(
1
downto
0
);
M_AXI_GP0_RVALID
:
in
std_logic
;
M_AXI_GP0_WDATA
:
out
std_logic_vector
(
31
downto
0
);
M_AXI_GP0_WID
:
out
std_logic_vector
(
11
downto
0
);
M_AXI_GP0_WLAST
:
out
std_logic
;
M_AXI_GP0_WREADY
:
in
std_logic
;
M_AXI_GP0_WSTRB
:
out
std_logic_vector
(
3
downto
0
);
M_AXI_GP0_WVALID
:
out
std_logic
;
PS_CLK
:
inout
std_logic
;
PS_PORB
:
inout
std_logic
;
PS_SRSTB
:
inout
std_logic
;
TTC0_WAVE0_OUT
:
out
std_logic
;
TTC0_WAVE1_OUT
:
out
std_logic
;
TTC0_WAVE2_OUT
:
out
std_logic
;
USB0_PORT_INDCTL
:
out
std_logic_vector
(
1
downto
0
);
USB0_VBUS_PWRFAULT
:
in
std_logic
;
USB0_VBUS_PWRSELECT
:
out
std_logic
);
end
component
processing_system_zedboard
;
signal
arid
,
awid
,
BID
,
RID
:
std_logic_vector
(
11
downto
0
);
signal
ARVALID
,
AWVALID
:
std_logic
;
begin
U_Wrapped_PS
:
processing_system_zedboard
port
map
(
DDR_Addr
=>
DDR_Addr
,
DDR_BankAddr
=>
DDR_BankAddr
,
DDR_CAS_n
=>
DDR_CAS_n
,
DDR_CKE
=>
DDR_CKE
,
DDR_CS_n
=>
DDR_CS_n
,
DDR_Clk
=>
DDR_Clk
,
DDR_Clk_n
=>
DDR_Clk_n
,
DDR_DM
=>
DDR_DM
,
DDR_DQ
=>
DDR_DQ
,
DDR_DQS
=>
DDR_DQS
,
DDR_DQS_n
=>
DDR_DQS_n
,
DDR_DRSTB
=>
DDR_DRSTB
,
DDR_ODT
=>
DDR_ODT
,
DDR_RAS_n
=>
DDR_RAS_n
,
DDR_VRN
=>
DDR_VRN
,
DDR_VRP
=>
DDR_VRP
,
DDR_WEB
=>
DDR_WEB
,
FCLK_CLK0
=>
FCLK_CLK0
,
FCLK_RESET0_N
=>
FCLK_RESET0_N
,
MIO
=>
MIO
,
M_AXI_GP0_ACLK
=>
m_axi_gp0_aclk_i
,
M_AXI_GP0_ARADDR
=>
m_axi_gp0_o
.
ARADDR
,
M_AXI_GP0_ARBURST
=>
open
,
M_AXI_GP0_ARCACHE
=>
open
,
M_AXI_GP0_ARID
=>
ARID
,
M_AXI_GP0_ARLEN
=>
open
,
M_AXI_GP0_ARLOCK
=>
open
,
M_AXI_GP0_ARPROT
=>
open
,
M_AXI_GP0_ARQOS
=>
open
,
M_AXI_GP0_ARREADY
=>
m_axi_gp0_i
.
ARREADY
,
M_AXI_GP0_ARSIZE
=>
open
,
M_AXI_GP0_ARVALID
=>
ARVALID
,
M_AXI_GP0_AWADDR
=>
m_axi_gp0_o
.
AWADDR
,
M_AXI_GP0_AWBURST
=>
open
,
M_AXI_GP0_AWCACHE
=>
open
,
M_AXI_GP0_AWID
=>
AWID
,
M_AXI_GP0_AWLEN
=>
open
,
M_AXI_GP0_AWLOCK
=>
open
,
M_AXI_GP0_AWPROT
=>
open
,
M_AXI_GP0_AWQOS
=>
open
,
M_AXI_GP0_AWREADY
=>
m_axi_gp0_i
.
AWREADY
,
M_AXI_GP0_AWSIZE
=>
open
,
M_AXI_GP0_AWVALID
=>
AWVALID
,
M_AXI_GP0_BID
=>
BID
,
M_AXI_GP0_BREADY
=>
m_axi_gp0_o
.
BREADY
,
M_AXI_GP0_BRESP
=>
m_axi_gp0_i
.
BRESP
,
M_AXI_GP0_BVALID
=>
m_axi_gp0_i
.
BVALID
,
M_AXI_GP0_RDATA
=>
m_axi_gp0_i
.
RDATA
,
M_AXI_GP0_RID
=>
RID
,
M_AXI_GP0_RLAST
=>
m_axi_gp0_i
.
RLAST
,
M_AXI_GP0_RREADY
=>
m_axi_gp0_o
.
RREADY
,
M_AXI_GP0_RRESP
=>
m_axi_gp0_i
.
RRESP
,
M_AXI_GP0_RVALID
=>
m_axi_gp0_i
.
RVALID
,
M_AXI_GP0_WDATA
=>
m_axi_gp0_o
.
WDATA
,
M_AXI_GP0_WID
=>
open
,
M_AXI_GP0_WLAST
=>
m_axi_gp0_o
.
WLAST
,
M_AXI_GP0_WREADY
=>
m_axi_gp0_i
.
WREADY
,
M_AXI_GP0_WSTRB
=>
m_axi_gp0_o
.
WSTRB
,
M_AXI_GP0_WVALID
=>
m_axi_gp0_o
.
WVALID
,
PS_CLK
=>
PS_CLK
,
PS_PORB
=>
PS_PORB
,
PS_SRSTB
=>
PS_SRSTB
,
TTC0_WAVE0_OUT
=>
TTC0_WAVE0_OUT
,
TTC0_WAVE1_OUT
=>
TTC0_WAVE1_OUT
,
TTC0_WAVE2_OUT
=>
TTC0_WAVE2_OUT
,
USB0_PORT_INDCTL
=>
USB0_PORT_INDCTL
,
USB0_VBUS_PWRFAULT
=>
USB0_VBUS_PWRFAULT
,
USB0_VBUS_PWRSELECT
=>
USB0_VBUS_PWRSELECT
);
-- forward transaction IDs to convert to AXI4-Lite
m_axi_gp0_o
.
ARVALID
<=
ARVALID
;
m_axi_gp0_o
.
AWVALID
<=
AWVALID
;
process
(
m_axi_gp0_aclk_i
)
begin
if
rising_edge
(
m_axi_gp0_aclk_i
)
then
if
ARVALID
=
'1'
then
rid
<=
ARID
;
end
if
;
if
AWVALID
=
'1'
then
BID
<=
AWID
;
end
if
;
end
if
;
end
process
;
end
wrapper
;
Gateware/zedboard-test-master/rtl/adc_core/Manifest.py
0 → 100644
View file @
f980ad4e
files
=
[
"ad9263_serdes.v"
,
"ad9263_serdes_selectio_wiz.v"
,
"adc_core.vhd"
,
"axi4_pkg.vhd"
,
"xwb_axi4lite_bridge.vhd"
,
"bitUnpackAndAlign.vhd"
,
#bitUnpackAndAlign.vhd~
#Manifest.py
"d3s_acq_buffer.vhd"
,
"d3s_acq_buffer_wbgen2_pkg.vhd"
,
"d3s_acq_buffer_wb.vhd"
,
"trigger_generator.vhd"
,
"trigger_generator_wbgen2_pkg.vhd"
,
"trigger_generator_wb.vhd"
];
Gateware/zedboard-test-master/rtl/adc_core/ad9263_serdes.v
0 → 100644
View file @
f980ad4e
// file: ad9263_serdes.v
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//----------------------------------------------------------------------------
`timescale
1
ps
/
1
ps
(
*
CORE_GENERATION_INFO
=
"ad9263_serdes,selectio_wiz_v5_1_7,{component_name=ad9263_serdes,bus_dir=INPUTS,bus_sig_type=DIFF,bus_io_std=LVDS_25,use_serialization=true,use_phase_detector=false,serialization_factor=8,enable_bitslip=false,enable_train=false,system_data_width=9,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=SINGLE,clk_io_std=LVCMOS18,clk_buf=BUFIO2,active_edge=RISING,clk_delay=NONE,selio_bus_in_delay=NONE,selio_bus_out_delay=NONE,selio_clk_buf=BUFIO,selio_active_edge=DDR,selio_ddr_alignment=SAME_EDGE_PIPELINED,selio_oddr_alignment=SAME_EDGE,ddr_alignment=C0,selio_interface_type=NETWORKING,interface_type=NETWORKING,selio_bus_in_tap=0,selio_bus_out_tap=0,selio_clk_io_std=LVDS_25,selio_clk_sig_type=DIFF}"
*
)
module
ad9263_serdes
// width of the data for the system
#(
parameter
SYS_W
=
9
,
// width of the data for the device
parameter
DEV_W
=
72
)
(
// From the system into the device
input
[
SYS_W
-
1
:
0
]
data_in_from_pins_p
,
input
[
SYS_W
-
1
:
0
]
data_in_from_pins_n
,
output
[
DEV_W
-
1
:
0
]
data_in_to_device
,
input
[
SYS_W
-
1
:
0
]
bitslip
,
// Bitslip module is enabled in NETWORKING mode
// User should tie it to '0' if not needed
input
clk_in_p
,
// Differential clock from IOB
input
clk_in_n
,
output
clk_div_out
,
// Slow clock output
input
clk_reset
,
input
io_reset
)
;
ad9263_serdes_selectio_wiz
#(
.
SYS_W
(
SYS_W
)
,
.
DEV_W
(
DEV_W
)
)
inst
(
.
data_in_from_pins_p
(
data_in_from_pins_p
)
,
.
data_in_from_pins_n
(
data_in_from_pins_n
)
,
.
data_in_to_device
(
data_in_to_device
)
,
.
bitslip
(
bitslip
)
,
.
clk_in_p
(
clk_in_p
)
,
.
clk_in_n
(
clk_in_n
)
,
.
clk_div_out
(
clk_div_out
)
,
.
clk_reset
(
clk_reset
)
,
.
io_reset
(
io_reset
)
)
;
endmodule
Gateware/zedboard-test-master/rtl/adc_core/ad9263_serdes_selectio_wiz.v
0 → 100644
View file @
f980ad4e
// file: ad9263_serdes_selectio_wiz.v
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//----------------------------------------------------------------------------
`timescale
1
ps
/
1
ps
module
ad9263_serdes_selectio_wiz
// width of the data for the system
#(
parameter
SYS_W
=
9
,
// width of the data for the device
parameter
DEV_W
=
72
)
(
// From the system into the device
input
[
SYS_W
-
1
:
0
]
data_in_from_pins_p
,
input
[
SYS_W
-
1
:
0
]
data_in_from_pins_n
,
output
[
DEV_W
-
1
:
0
]
data_in_to_device
,
input
[
SYS_W
-
1
:
0
]
bitslip
,
// Bitslip module is enabled in NETWORKING mode
// User should tie it to '0' if not needed
input
clk_in_p
,
// Differential clock from IOB
input
clk_in_n
,
output
clk_div_out
,
// Slow clock output
input
clk_reset
,
input
io_reset
)
;
localparam
num_serial_bits
=
DEV_W
/
SYS_W
;
wire
clock_enable
=
1'b1
;
// Signal declarations
////------------------------------
// After the buffer
wire
[
SYS_W
-
1
:
0
]
data_in_from_pins_int
;
// Between the delay and serdes
wire
[
SYS_W
-
1
:
0
]
data_in_from_pins_delay
;
// Array to use intermediately from the serdes to the internal
// devices. bus "0" is the leftmost bus
wire
[
SYS_W
-
1
:
0
]
iserdes_q
[
0
:
13
]
;
// fills in starting with 0
// Create the clock logic
IBUFDS
#(
.
IOSTANDARD
(
"LVDS_25"
)
,
.
DIFF_TERM
(
"TRUE"
))
ibufds_clk_inst
(
.
I
(
clk_in_p
)
,
.
IB
(
clk_in_n
)
,
.
O
(
clk_in_int
))
;
// High Speed BUFIO clock buffer
BUFIO
bufio_inst
(
.
O
(
clk_in_int_buf
)
,
.
I
(
clk_in_int
))
;