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PXIe controller COM Express based
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PXIe controller COM Express based
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PXI_TRIG7 is connected to multiple FPGA pins, was this intentional?
#40
· opened
Sep 22, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 07, 2020
[L1] X:88mm Y:12mm use wider thermal reliefs to pass required current on P1V rail
#39
· opened
Sep 22, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
[L1] X:80mm Y:84mm fix SMB_CLK track routing
#42
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
USB3.0 (Sheet 3): Use hierarchical sheet
#16
· opened
Apr 17, 2020
by
Dimitris Lampridis
Minor
CLOSED
1
updated
Apr 29, 2020
[L8] P3V3AUX pad barely touching the via
#47
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
COM Express (Sheet 2): Align FPGA_INIT_N port
#13
· opened
Apr 16, 2020
by
Dimitris Lampridis
Cosmetics
CLOSED
1
updated
Apr 29, 2020
PCI Express Clock (Sheet 9): R32-R35, more separation between designator and resistor value
#22
· opened
Apr 17, 2020
by
Dimitris Lampridis
Cosmetics
CLOSED
1
updated
Apr 29, 2020
GbE (Sheet 6): Do we need to handle ESD on GbE?
#19
· opened
Apr 17, 2020
by
Dimitris Lampridis
Question
CLOSED
1
updated
Apr 29, 2020
PCI Express Clock (Sheet 9): fix typos
#23
· opened
Apr 17, 2020
by
Dimitris Lampridis
Cosmetics
CLOSED
1
updated
Apr 29, 2020
Document providing test procedure of the prototype / Functional test of the prototype with a COMe module provided by CERN
#50
· opened
Nov 03, 2020
by
Paul PERONNARD
Question
CLOSED
4
updated
Mar 04, 2022
IC22 traces wider than component pads
#48
· opened
Sep 28, 2020
by
Tomasz Wlostowski
CLOSED
1
updated
Oct 06, 2020
[L1] X:97mm Y:91mm move SER1_RX track further away from M1 mounting hole
#43
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
Possible acid traps in polygons
#46
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
Diff pairs should be deskewed close to source or receiver which is not always the case
#44
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
Add more stitching vias to connect GND planes together
#45
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
3
updated
Oct 08, 2020
Copyright & licensing note should be present on every schematics sheet
#2
· opened
Apr 16, 2020
by
Dimitris Lampridis
Important
CLOSED
1
updated
Nov 03, 2020
USB (Sheets 3, 4 and 5): Circuit to avoiding Back-driving Problems
#15
· opened
Apr 17, 2020
by
Dimitris Lampridis
Important
CLOSED
1
updated
Apr 29, 2020
Add some test points
#5
· opened
Apr 16, 2020
by
Dimitris Lampridis
Minor
CLOSED
1
1
updated
Apr 30, 2020
[L1] IC21 layout could be optimised
#41
· opened
Sep 22, 2020
by
Grzegorz Daniluk
CLOSED
7
updated
Oct 09, 2020
Thermal reliefs not needed for press-fit connectors
#36
· opened
Sep 22, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Sep 29, 2022
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