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P
PXIe controller COM Express based testing support
Commit f94b2e35 authored by René Bakker's avatar René Bakker
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hdl/.gitignore 0 → 100644
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#########################################################################################################
## This is an example .gitignore file for Vivado, please treat it as an example as
## it might not be complete. In addition, XAPP 1165 should be followed.
#########################################################################################################
#########
#Exclude all
#########
*
!*/
!.gitignore
!touch.bat
###########################################################################
## VIVADO
###########################################################################
#########
#Source files:
#########
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
!*.vhd
!*.v
!*.bd
!*.edif
#########
#IP files
#########
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
#.xci + .dcp: implementation possible but not re-synthesis
#*.xci(www.spiritconsortium.org)
!*.xci
#*.dcp(checkpoint files)
!*.dcp
!*.vds
!*.pb
#All bd comments and layout coordinates are stored within .ui
!*.ui
!*.ooc
#########
#System Generator
#########
!*.mdl
!*.slx
!*.bxml
#########
#Simulation logic analyzer
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!*.wcfg
!*.coe
#########
#MIG
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!*.prj
!*.mem
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#Project files
#########
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
#Do NOT ignore *.xpr files
!*.xpr
#Include *.xml files for 2013.4 or earlier version
!*.xml
#########
#Constraint files
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#Do NOT ignore *.xdc files
!*.xdc
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#TCL - files
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!*.tcl
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#Journal - files
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!*.jou
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!*.rpt
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!*.vdi
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#C-files
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!*.c
!*.h
!*.elf
!*.bmm
!*.xmp
hdl/Packages/.repos.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<repositories>
<repository>
<type>CMSIS Pack</type>
<name>Keil</name>
<url>http://www.keil.com/pack/index.idx</url>
</repository>
<repository>
<type>XCDL/CMSIS Pack</type>
<name>GNU ARM Eclipse</name>
<url>http://gnuarmeclipse.sourceforge.net/packages/content.xml</url>
</repository>
</repositories>
hdl/ip_repo/t_gpio_interface/t_gpio_interface.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- t_gpio_interface.vhd
--
-- Copyright CERN, 2021
-- This source describes Open Hardware and is licensed under the
-- CERN-OHL-S v2
-- Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
-- designed by INCAA Computers
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--================================= ENTITY ==================================--
entity t_gpio_interface is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- GPIO interfaces
gpio_i_pxi : out std_logic_vector(13 downto 0);
gpio_o_pxi : in std_logic_vector(13 downto 0);
gpio_t_pxi : in std_logic_vector(13 downto 0);
gpio2_pxi : out std_logic_vector(5 downto 0);
gpio_cex : in std_logic_vector(4 downto 0);
gpio2_cex : out std_logic_vector(3 downto 0);
gpio_pxi_star : out std_logic_vector(31 downto 0);
-- I/O pads
pxi_trig : inout std_logic_vector(7 downto 0);
pxi_trig7aux : inout std_logic_vector(2 downto 0);
pxi_lbr6 : inout std_logic;
pxi_ga : in std_logic_vector(4 downto 0);
pxi_star : in std_logic;
trig_in : in std_logic;
trig_out : out std_logic;
trig_oe : out std_logic;
trig_tsel : out std_logic;
fpga_gpo : out std_logic_vector(1 downto 0);
fpga_gpo_sel_N : out std_logic;
fpga_gpi : in std_logic_vector(3 downto 0);
test : out std_logic_vector(2 downto 1)
);
end t_gpio_interface;
--============================== ARCHITECTURE ===============================--
architecture behaviour of t_gpio_interface is
component IBUF
port(
I: in STD_LOGIC;
O: out STD_LOGIC
);
end component;
component OBUFT
port (
I: in std_logic;
T: in std_logic;
O: out std_logic
);
end component;
-- pxi and front panel trig
alias a_pxi_trig_i : std_logic_vector(6 downto 0) is gpio_i_pxi(6 downto 0);
alias a_pxi_trig7_i : std_logic_vector(3 downto 0) is gpio_i_pxi(10 downto 7);
alias a_pxi_lbr6_i : std_logic is gpio_i_pxi(11);
alias a_trig_i : std_logic is gpio_i_pxi(12);
alias a_trig_tsel_i : std_logic is gpio_i_pxi(13);
alias a_pxi_trig_o : std_logic_vector(6 downto 0) is gpio_o_pxi(6 downto 0);
alias a_pxi_trig7_o : std_logic_vector(3 downto 0) is gpio_o_pxi(10 downto 7);
alias a_pxi_lbr6_o : std_logic is gpio_o_pxi(11);
alias a_trig_o : std_logic is gpio_o_pxi(12);
alias a_trig_tsel_o : std_logic is gpio_o_pxi(13);
alias a_pxi_trig_t : std_logic_vector(7 downto 0) is gpio_t_pxi(7 downto 0);
alias a_pxi_trig7_t : std_logic_vector(3 downto 0) is gpio_t_pxi(10 downto 7);
alias a_pxi_lbr6_t : std_logic is gpio_t_pxi(11);
alias a_trig_t : std_logic is gpio_t_pxi(12);
alias a_trig_tsel_t : std_logic is gpio_t_pxi(13);
signal pxi_trig7_o : std_logic_vector(3 downto 0);
signal pxi_trig7_t : std_logic_vector(3 downto 0);
alias a_pxi_ga : std_logic_vector(4 downto 0) is gpio2_pxi(4 downto 0);
alias a_pxi_star : std_logic is gpio2_pxi(5);
-- alias a_pxi_clk10 : std_logic is gpio2_pxi(6);
signal pxi_star_rec : std_logic_vector(gpio_pxi_star'range);
-- cex
alias a_fpga_gpo : std_logic_vector(1 downto 0) is gpio_cex(1 downto 0);
alias a_fpga_gpo_enable : std_logic is gpio_cex(2);
alias a_test : std_logic_vector(2 downto 1) is gpio_cex(4 downto 3);
alias a_fpga_gpi : std_logic_vector(3 downto 0) is gpio2_cex(3 downto 0);
begin
-- PXI_TRIG[6:0]
GenPxiTrigBuffers : for ch in 0 to 6 generate
OBUFT_pxi_trig : OBUFT port map (I => a_pxi_trig_o(ch), T => a_pxi_trig_t(ch), O => pxi_trig(ch));
IBUF_pxi_trig : IBUF port map (I => pxi_trig(ch), O => a_pxi_trig_i(ch));
end generate;
-- PXI_TRIG[7]
-- PXI_TRIG7 is attached to four FPGA I/O pads of which one is also a MRCC capable input.
-- As an PXI_TRIG7 input only one of these four (the MRCC capable input) is needed.
-- As an PXI_TRIG7 output all four have to switch simultaniously to be able to source a minimum of 75mA.
-- This can be achieved by selecting LVTTL outputs with two outputs driving 24mA and two 16mA.
--
-- For the production test all four I/O pads can be used seperately, but not with different output levels.
PxiTrig7TriState : process (a_pxi_trig7_t, gpio_t_pxi, a_pxi_trig7_o, gpio_o_pxi)
variable v_pxi_trig7_en : std_logic_vector(a_pxi_trig7_t'range);
constant c_all_one : std_logic_vector(a_pxi_trig7_o'range) := "1111";
constant c_all_zero : std_logic_vector(a_pxi_trig7_o'range) := "0000";
begin
v_pxi_trig7_en := not a_pxi_trig7_t;
pxi_trig7_o <= a_pxi_trig7_o;
if (((v_pxi_trig7_en and a_pxi_trig7_o) = (v_pxi_trig7_en and c_all_one)) or
((v_pxi_trig7_en and a_pxi_trig7_o) = (v_pxi_trig7_en and c_all_zero))) then
pxi_trig7_t <= a_pxi_trig7_t;
else
pxi_trig7_t <= "1111";
end if;
end process PxiTrig7TriState;
GenPxiTrig7Buffers : for ch in pxi_trig7_t'range generate
GenTrig7 : if (ch = 0) generate
OBUFT_pxi_trig7 : OBUFT port map (I => pxi_trig7_o(ch), T => pxi_trig7_t(ch), O => pxi_trig(7));
IBUF_pxi_trig7 : IBUF port map (I => pxi_trig(7), O => a_pxi_trig7_i(ch));
end generate;
GenTrig7Aux : if (ch /= 0) generate
OBUFT_pxi_trig7aux : OBUFT port map (I => a_pxi_trig7_o(ch), T => pxi_trig7_t(ch), O => pxi_trig7aux(ch-1));
IBUF_pxi_trig7aux : IBUF port map (I => pxi_trig7aux(ch-1), O => a_pxi_trig7_i(ch));
end generate;
end generate;
-- PXI_LBR6
OBUFT_pxi_lbr6 : OBUFT port map (I => a_pxi_lbr6_o, T => a_pxi_lbr6_t, O => pxi_lbr6);
IBUF_pxi_lbr6 : IBUF port map (I => pxi_lbr6, O => a_pxi_lbr6_i);
-- PXI_GA
a_pxi_ga <= pxi_ga;
-- PXI_STAR
a_pxi_star <= pxi_star;
-- PXI_CLK10
-- a_pxi_clk10 <= '0';
PxiStarRecorder : process (s_axi_aclk)
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
pxi_star_rec <= (others => '0');
else
pxi_star_rec <= pxi_star_rec(pxi_star_rec'left-1 downto pxi_star_rec'right) & pxi_star;
end if;
end if;
end process PxiStarRecorder;
gpio_pxi_star <= pxi_star_rec;
-- Front panel TRIG
a_trig_i <= trig_in;
trig_out <= a_trig_o;
trig_oe <= not a_trig_t;
trig_tsel <= a_trig_tsel_o when (a_trig_tsel_t = '0') else '0';
a_trig_tsel_i <= a_trig_tsel_o;
-- CEX_GPO
fpga_gpo <= a_fpga_gpo;
-- fpga_gpo_sel_N controls the external selection of which signal is passed on to the CEX.
-- cex_gpi0 = fpga_gpo0 when fpga_gpo_sel_N = '0' else pe_sysen_N
-- cex_gpi1 = fpga_gpo1 when fpga_gpo_sel_N = '0' else pe_linkcap
fpga_gpo_sel_N <= not a_fpga_gpo_enable;
-- CEX_GPI
a_fpga_gpi <= fpga_gpi;
-- TEST1 and TEST2
test <= a_test;
end behaviour;
-------------------------------------------------------------------------------
-- EOF -- t_gpio_interface.vhd
-------------------------------------------------------------------------------
hdl/sdk/.metadata/.plugins/com.xilinx.sdk.hw.ui/dialog_settings.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<section name="Workbench">
<item value="design_tFPGA_wrapper_hw_platform_0" key="applicationwizard.hw_platform_key"/>
<item value="design_tFPGA_wrapper_hw_platform_0" key="bspwizard.hw_platform_key"/>
</section>
hdl/sdk/.metadata/.plugins/com.xilinx.sdk.targetmanager.ui/dialog_settings.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<section name="Workbench">
<item value="design_tFPGA_wrapper.bit" key="design_tFPGA_wrapper_hw_platform_0-bitFile"/>
<item value="K:\Work\PLD\UDAT\sdk\tFPGA_app\Release\tFPGA_app.elf" key="design_tFPGA_wrapper_hw_platform_0-microblaze_0-initElf"/>
<item value="design_tFPGA_wrapper_hw_platform_0" key="programfpga.hwplatform"/>
<item value="Local" key="design_tFPGA_wrapper_hw_platform_0-target"/>
<item value="Auto Detect" key="design_tFPGA_wrapper_hw_platform_0-device"/>
<item value="design_tFPGA_wrapper.mmi" key="design_tFPGA_wrapper_hw_platform_0-bmmFile"/>
<item value="false" key="design_tFPGA_wrapper_hw_platform_0-partial_bit"/>
</section>
hdl/sdk/.metadata/.plugins/com.xilinx.sdk.utils/dialog_settings.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<section name="Workbench">
<item value="K:\Work\PLD\UDAT\tFPGA\project_tFPGA.sdk" key="com.xilinx.sdk.hw.ui.hwspec.last"/>