SPEC VHDL files are not in good structure; there should be files missing and others with mistakes.

Some feedback from a company follows:
"..We have developed the SPEXI based on the SPEC design. To also adjust the PTS environment from the SPEC to the SPEXI we need the complete VHDL designs for the SPEC tests to resynthesize these projects.
Erik pointed us to the VHDL zip file on the GIT a few weeks ago. This zip file is however not complete. And At least one project also contains an error.

The first project which I opened was ‘test_ddr’ (test07) of which I found all source files but this resulted in the following error during map:

ERROR:PhysDesignRules:2449 - The computed value for the VCO operating frequency
of PLL_ADV instance cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst is calculated
to be 320.000000 MHz. This falls below the operating range of the PLL VCO
frequency for this device of 400.000000 - 1080.000000 MHz. Please adjust
either the input frequency CLKINx_PERIOD, multiplication factor CLKFBOUT_MULT
or the division factor DIVCLK_DIVIDE, in order to achieve a VCO frequency
within the rated operating range for this device.
ERROR:Pack:1642 - Errors in physical DRC.

We currently use the Xilinx ISE WebPack 14.2, but the projects are created using version 12.2. I do not have this version currently installed, and I also do not know if this error is caused by the change in version. I still need to investigate this.

But I have more problems regarding the set of VHDL source files. I have opened several other projects within this zip file which point to not existing source files. Fortunately many can be found in other sub-directories of other project like ‘test_temp_sensor’, but not all. For example project ‘test_dac_pll’ is missing the file wb_spi_master.vhd. And the project ‘test_sata_dp0’ needs many ip-cores which I can’t seem to find anywhere.

Is it possible to collect and create a complete set of error free Xilinx projects which can be synthesized and used for the tests with the SPEC PTS?"