Commit e941029d authored by Evangelia Gousiou's avatar Evangelia Gousiou

Merge branch 'master' of ohwr.org:misc/pts

parents 8dd5a97e 1c490ed1
fetchto = "ip_cores"
modules = {
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git" ],
"svn" : [ "http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl" ]
}
files = ["fmc_refclk_test.vhd",
"fmc_refclk_test_tile.vhd",
"mgt_usrclk_source_pll.vhd"]
This source diff could not be displayed because it is too large. You can view the blob instead.
# Date: Thu Nov 1 11:26:58 2012
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx150t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: eb716463
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fmc_refclk_test.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_VHO" xil_pn:name="fmc_refclk_test.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
<HTML>
<HEAD>
<TITLE>s6_gtpwizard_v1_11_vinfo</TITLE>
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
</HEAD>
<BODY>
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
Core name: Xilinx LogiCORE Spartan-6 FPGA GTP Transceiver Wizard
Version: 1.11
Release Date: October 19, 2011
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Other Information
8. Core Release History
9. Legal Disclaimer
================================================================================
1. INTRODUCTION
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
This file contains release notes for the Xilinx LogiCORE IP Spartan-6 FPGA
GTP Transceiver Wizard v1.11 solution. For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/intellectual-property/S6_FPGA_GTP_Transceiver_Wizard.htm">www.xilinx.com/products/intellectual-property/S6_FPGA_GTP_Transceiver_Wizard.htm</A>
2. NEW FEATURES
- ISE 13.3 software support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
Spartan-6 XC LX/LXT
Spartan-6 XA LX/LXT
Spartan-6 XQ LX/LXT
4. RESOLVED ISSUES
1. Attribute Updates
Description: The following Attributes were updated :
- PMA_RX_CFG setting for PCIE
- RCV_TERM_VTTRX for SRIO, XAUI, SDI protocols
Version(s) Fixed:
CR 615296, 613303
2. Renamed REFCLKOUT to REFCLKPLL in GUI
Description: In page 4 of GUI, the options to choose TX/RXUSRCLK
source has been modified - REFCLKOUT is renamed to REFCLKPLL
Version(s) Fixed:
CR 620887
5. KNOWN ISSUES
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. OTHER INFORMATION
8. CORE RELEASE HISTORY
Date By Version Description
================================================================================
10/19/2011 Xilinx. Inc. 1.11 ISE 13.3 support
06/22/2011 Xilinx, Inc. 1.10 ISE 13.2 support
03/01/2011 Xilinx, Inc. 1.9 ISE 13.1 support
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
================================================================================
9. LEGAL DISCLAIMER
(c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
</BODY>
</HTML>
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : fmc_refclk_test_top.ucf
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
## Device: xc6slx150t
## Package: fgg900
################################## Clock Constraints ##########################
# User Clock Constraints
NET "tile0_txusrclk0_i" TNM_NET = "tile0_txusrclk0_i";
TIMESPEC "TS_tile0_txusrclk0_i" = PERIOD "tile0_txusrclk0_i" 8.0;
NET "tile0_txusrclk20_i" TNM_NET = "tile0_txusrclk20_i";
TIMESPEC "TS_tile0_txusrclk20_i" = PERIOD "tile0_txusrclk20_i" 32.0;
NET "tile1_txusrclk0_i" TNM_NET = "tile1_txusrclk0_i";
TIMESPEC "TS_tile1_txusrclk0_i" = PERIOD "tile1_txusrclk0_i" 8.0;
NET "tile1_txusrclk20_i" TNM_NET = "tile1_txusrclk20_i";
TIMESPEC "TS_tile1_txusrclk20_i" = PERIOD "tile1_txusrclk20_i" 32.0;
######################## locs for top level ports ######################
######################### mgt clock module constraints ########################
NET TILE0_GTP0_REFCLK_PAD_N_IN LOC=AH18;
NET TILE0_GTP0_REFCLK_PAD_P_IN LOC=AG18;
NET TILE1_GTP0_REFCLK_PAD_N_IN LOC=A13;
NET TILE1_GTP0_REFCLK_PAD_P_IN LOC=B13;
################################# mgt wrapper constraints #####################
##---------- Set placement for tile0_rocketio_wrapper_i/GTPA1_DUAL ------
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i LOC=GTPA1_DUAL_X1Y0;
##---------- Set placement for tile1_rocketio_wrapper_i/GTPA1_DUAL ------
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i LOC=GTPA1_DUAL_X0Y1;
This source diff could not be displayed because it is too large. You can view the blob instead.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : mgt_usrclk_source_pll.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module MGT_USRCLK_SOURCE_PLL (for use with GTP Transceivers)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***********************************Entity Declaration*******************************
entity MGT_USRCLK_SOURCE_PLL is
generic
(
MULT : integer := 2;
DIVIDE : integer := 2;
FEEDBACK : string := "CLKFBOUT";
CLK_PERIOD : real := 8.0;
OUT0_DIVIDE : integer := 2;
OUT1_DIVIDE : integer := 2;
OUT2_DIVIDE : integer := 2;
OUT3_DIVIDE : integer := 2
);
port
(
CLK0_OUT : out std_logic;
CLK1_OUT : out std_logic;
CLK2_OUT : out std_logic;
CLK3_OUT : out std_logic;
CLK_IN : in std_logic;
CLKFB_IN : in std_logic;
CLKFB_OUT : out std_logic;
PLL_LOCKED_OUT : out std_logic;
PLL_RESET_IN : in std_logic
);
end MGT_USRCLK_SOURCE_PLL;
architecture RTL of MGT_USRCLK_SOURCE_PLL is
--*********************************Wire Declarations**********************************
signal tied_to_ground_vec_i : std_logic_vector(15 downto 0);
signal tied_to_ground_i : std_logic;
signal tied_to_vcc_i : std_logic;
signal clkout0_i : std_logic;
signal clkout1_i : std_logic;
signal clkout2_i : std_logic;
signal clkout3_i : std_logic;
begin
--*********************************** Beginning of Code *******************************
-- Static signal Assigments
tied_to_ground_i <= '0';
tied_to_ground_vec_i <= (others=>'0');
tied_to_vcc_i <= '1';
-- Instantiate a PLL module to divide the reference clock. Uses internal feedback
-- for improved jitter performance, and to avoid consuming an additional BUFG
pll_adv_i : PLL_BASE
generic map
(
CLKFBOUT_MULT => MULT,
DIVCLK_DIVIDE => DIVIDE,
CLK_FEEDBACK => FEEDBACK,
CLKFBOUT_PHASE => 0.0,
COMPENSATION => "SYSTEM_SYNCHRONOUS",
CLKIN_PERIOD => CLK_PERIOD,
CLKOUT0_DIVIDE => OUT0_DIVIDE,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => OUT1_DIVIDE,
CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => OUT2_DIVIDE,
CLKOUT2_PHASE => 0.0,
CLKOUT3_DIVIDE => OUT3_DIVIDE,
CLKOUT3_PHASE => 0.0
)
port map
(
CLKIN => CLK_IN,
CLKFBIN => CLKFB_IN,
CLKOUT0 => clkout0_i,
CLKOUT1 => clkout1_i,
CLKOUT2 => clkout2_i,
CLKOUT3 => clkout3_i,
CLKOUT4 => open,
CLKOUT5 => open,
CLKFBOUT => CLKFB_OUT,
LOCKED => PLL_LOCKED_OUT,
RST => PLL_RESET_IN
);
clkout0_bufg_i : BUFG
port map
(
O => CLK0_OUT,
I => clkout0_i
);
clkout1_bufg_i : BUFG
port map
(
O => CLK1_OUT,
I => clkout1_i
);
clkout2_bufg_i : BUFG
port map
(
O => CLK2_OUT,
I => clkout2_i
);
clkout3_bufg_i : BUFG
port map
(
O => CLK3_OUT,
I => clkout3_i
);
end RTL;
description=User generated protocol
gtp0_target_line_rate=1.25
gtp0_pll_rate=1.25
gtp0_tx_line_rate=1.25
gtp0_tx_divider=/2
gtp0_tx_datapath_width=32
gtp0_encoding=8B/10B
gtp0_rx_line_rate=1.25
gtp0_rx_divider=/2
gtp0_rx_datapath_width=32
gtp0_decoding=8B/10B
gtp0_reference_clock=125.00
gtp1_target_line_rate=1.25
gtp1_pll_rate=1.25
gtp1_tx_line_rate=1.25
gtp1_tx_divider=/2
gtp1_tx_datapath_width=32
gtp1_encoding=8B/10B
gtp1_rx_line_rate=1.25
gtp1_rx_divider=/2
gtp1_rx_datapath_width=32
gtp1_decoding=8B/10B
gtp1_reference_clock=125.00
gtp0_use_port_txbypass8b10b=false
gtp0_use_port_txchardispmode=false
gtp0_use_port_txchardispval=false
gtp0_use_port_txkerr=false
gtp0_use_port_txrundisp=false
gtp0_use_port_rxchariscomma=false
gtp0_use_port_rxcharisk=false
gtp0_use_port_rxrundisp=false
gtp1_use_port_txbypass8b10b=false
gtp1_use_port_txchardispmode=false
gtp1_use_port_txchardispval=false
gtp1_use_port_txkerr=false
gtp1_use_port_txrundisp=false
gtp1_use_port_rxchariscomma=false
gtp1_use_port_rxcharisk=false
gtp1_use_port_rxrundisp=false
gtp0_use_txbuffer=true
gtp0_txusrclk_source=TXOUTCLK
gtp0_use_rxbuffer=true
gtp0_rxusrclk_source=TXOUTCLK
gtp0_use_port_rxreset=false
gtp0_use_port_rxrecclk=false
gtp0_use_port_rxbufstatus=false
gtp0_use_port_rxbufreset=false
gtp0_use_port_txoutclk=true
gtp0_use_port_txreset=false
gtp0_use_port_txbufstatus=false
gtp0_use_port_refclkout=false
gtp1_use_txbuffer=true
gtp1_txusrclk_source=TXOUTCLK
gtp1_use_rxbuffer=true
gtp1_rxusrclk_source=TXOUTCLK
gtp1_use_port_rxreset=false
gtp1_use_port_rxrecclk=false
gtp1_use_port_rxbufstatus=false
gtp1_use_port_rxbufreset=false
gtp1_use_port_txoutclk=true
gtp1_use_port_txreset=false
gtp1_use_port_txbufstatus=false
gtp1_use_port_refclkout=false
gtp0_use_comma_detect=true
gtp0_dec_valid_comma_only=false
gtp0_comma_preset=K28.5
gtp0_plus_comma=0101111100
gtp0_minus_comma=1010000011
gtp0_comma_mask=1111111111
gtp0_comma_alignment=Any_Byte_Boundary
gtp0_use_port_enpcommaalign=true
gtp0_use_port_enmcommaalign=true
gtp0_use_port_rxslide=false
gtp0_use_port_rxbyteisaligned=false
gtp0_use_port_rxbyterealign=false
gtp0_use_port_rxcommadet=false
gtp1_use_comma_detect=true
gtp1_dec_valid_comma_only=false
gtp1_comma_preset=K28.5
gtp1_plus_comma=0101111100
gtp1_minus_comma=1010000011
gtp1_comma_mask=1111111111
gtp1_comma_alignment=Any_Byte_Boundary
gtp1_use_port_enpcommaalign=true
gtp1_use_port_enmcommaalign=true
gtp1_use_port_rxslide=false
gtp1_use_port_rxbyteisaligned=false
gtp1_use_port_rxbyterealign=false
gtp1_use_port_rxcommadet=false
gtp0_preemphasis_level=Use_TXPREEMPHASIS_Port
gtp0_driver_swing=Use_TXDIFFCTRL_Port
gtp0_wideband_highpass_mix=Use_RXEQMIX_Port
gtp0_disable_ac_coupling=true
gtp0_rx_termination_voltage=VTTRX
gtp0_use_port_txpolarity=false
gtp0_use_port_txinhibit=false
gtp0_use_port_rxcdrreset=false
gtp0_use_port_rxpolarity=false
gtp1_preemphasis_level=Use_TXPREEMPHASIS_Port
gtp1_driver_swing=Use_TXDIFFCTRL_Port
gtp1_wideband_highpass_mix=Use_RXEQMIX_Port
gtp1_disable_ac_coupling=true
gtp1_rx_termination_voltage=VTTRX
gtp1_use_port_txpolarity=false
gtp1_use_port_txinhibit=false
gtp1_use_port_rxcdrreset=false
gtp1_use_port_rxpolarity=false
gtp0_use_rx_oob=false
gtp0_rx_oob_threshold=110
gtp0_use_prbs_detector=false
gtp0_use_port_txenprbstst=false
gtp0_use_port_txprbsforceerr=false
gtp0_use_port_rxlossofsync=true
gtp0_rxlossofsyncport=true
gtp0_errors_to_lose_sync=128
gtp0_bytes_to_reduce_error=8
gtp1_use_rx_oob=false
gtp1_rx_oob_threshold=110
gtp1_use_prbs_detector=false
gtp1_use_port_txenprbstst=false
gtp1_use_port_txprbsforceerr=false
gtp1_use_port_rxlossofsync=true
gtp1_rxlossofsyncport=true
gtp1_errors_to_lose_sync=128
gtp1_bytes_to_reduce_error=8
gtp0_rx_status_fmt=PCIe
gtp0_pci_express_mode=false
gtp0_sata_tx_burst_val=15
gtp0_sata_rx_burst_val=4
gtp0_sata_rx_idle_val=4
gtp0_trans_time_to_p2=100
gtp0_trans_time_from_p2=60
gtp0_trans_time_non_p2=25
gtp0_use_port_loopback=true
gtp0_use_port_rxpowerdown=false
gtp0_use_port_rxstatus=false
gtp0_use_port_rxvalid=false
gtp0_use_port_txcomstart=false
gtp0_use_port_txcomtype=false
gtp0_use_port_txpowerdown=false
gtp0_use_port_txdetectrx=false
gtp0_use_port_txelecidle=false
gtp0_use_port_phystatus=false
gtp1_rx_status_fmt=PCIe
gtp1_pci_express_mode=false
gtp1_sata_tx_burst_val=15
gtp1_sata_rx_burst_val=4
gtp1_sata_rx_idle_val=4
gtp1_trans_time_to_p2=100
gtp1_trans_time_from_p2=60
gtp1_trans_time_non_p2=25
gtp1_use_port_loopback=true
gtp1_use_port_rxpowerdown=false
gtp1_use_port_rxstatus=false
gtp1_use_port_rxvalid=false
gtp1_use_port_txcomstart=false
gtp1_use_port_txcomtype=false
gtp1_use_port_txpowerdown=false
gtp1_use_port_txdetectrx=false
gtp1_use_port_txelecidle=false
gtp1_use_port_phystatus=false
use_cb=false
use_two_cb_sequences=false
cb_sequence_length=1
cb_sequence_1_max_skew=1
cb_sequence_2_max_skew=1
cb_seq_1_1_mask=true
cb_seq_1_1=00000000
cb_seq_1_1_k=false
cb_seq_1_1_disp=false
cb_seq_1_2_mask=true
cb_seq_1_2=00000000
cb_seq_1_2_k=false
cb_seq_1_2_disp=false
cb_seq_1_3_mask=true
cb_seq_1_3=00000000
cb_seq_1_3_k=false
cb_seq_1_3_disp=false
cb_seq_1_4_mask=true
cb_seq_1_4=00000000
cb_seq_1_4_k=false
cb_seq_1_4_disp=false
cb_seq_2_1_mask=true
cb_seq_2_1=00000000
cb_seq_2_1_k=false
cb_seq_2_1_disp=false
cb_seq_2_2_mask=true
cb_seq_2_2=00000000
cb_seq_2_2_k=false
cb_seq_2_2_disp=false
cb_seq_2_3_mask=true
cb_seq_2_3=00000000
cb_seq_2_3_k=false
cb_seq_2_3_disp=false
cb_seq_2_4_mask=true
cb_seq_2_4=00000000
cb_seq_2_4_k=false
cb_seq_2_4_disp=false
gtp0_use_cc=false
gtp0_cc_sequence_length=1
gtp0_fifo_upper_bounds=18
gtp0_fifo_lower_bounds=16
gtp0_use_two_cc_sequences=false
gtp1_use_cc=false
gtp1_cc_sequence_length=1
gtp1_fifo_upper_bounds=18
gtp1_fifo_lower_bounds=16
gtp1_use_two_cc_sequences=false
gtp0_cc_seq_1_1_mask=true
gtp0_cc_seq_1_1=00000000
gtp0_cc_seq_1_1_k=true
gtp0_cc_seq_1_1_disp=false
gtp0_cc_seq_1_2_mask=true
gtp0_cc_seq_1_2=00000000
gtp0_cc_seq_1_2_k=true
gtp0_cc_seq_1_2_disp=false
gtp0_cc_seq_1_3_mask=true
gtp0_cc_seq_1_3=00000000
gtp0_cc_seq_1_3_k=true
gtp0_cc_seq_1_3_disp=false
gtp0_cc_seq_1_4_mask=true
gtp0_cc_seq_1_4=00000000
gtp0_cc_seq_1_4_k=true
gtp0_cc_seq_1_4_disp=false
gtp0_cc_seq_2_1_mask=true
gtp0_cc_seq_2_1=00000000
gtp0_cc_seq_2_1_k=true
gtp0_cc_seq_2_1_disp=false
gtp0_cc_seq_2_2_mask=true
gtp0_cc_seq_2_2=00000000
gtp0_cc_seq_2_2_k=true
gtp0_cc_seq_2_2_disp=false
gtp0_cc_seq_2_3_mask=true
gtp0_cc_seq_2_3=00000000
gtp0_cc_seq_2_3_k=true
gtp0_cc_seq_2_3_disp=false
gtp0_cc_seq_2_4_mask=true
gtp0_cc_seq_2_4=00000000
gtp0_cc_seq_2_4_k=true
gtp0_cc_seq_2_4_disp=false
gtp1_cc_seq_1_1_mask=true
gtp1_cc_seq_1_1=00000000
gtp1_cc_seq_1_1_k=true
gtp1_cc_seq_1_1_disp=false
gtp1_cc_seq_1_2_mask=true
gtp1_cc_seq_1_2=00000000
gtp1_cc_seq_1_2_k=true
gtp1_cc_seq_1_2_disp=false
gtp1_cc_seq_1_3_mask=true
gtp1_cc_seq_1_3=00000000
gtp1_cc_seq_1_3_k=true
gtp1_cc_seq_1_3_disp=false
gtp1_cc_seq_1_4_mask=true
gtp1_cc_seq_1_4=00000000
gtp1_cc_seq_1_4_k=true
gtp1_cc_seq_1_4_disp=false
gtp1_cc_seq_2_1_mask=true
gtp1_cc_seq_2_1=00000000
gtp1_cc_seq_2_1_k=true
gtp1_cc_seq_2_1_disp=false
gtp1_cc_seq_2_2_mask=true
gtp1_cc_seq_2_2=00000000
gtp1_cc_seq_2_2_k=true
gtp1_cc_seq_2_2_disp=false
gtp1_cc_seq_2_3_mask=true
gtp1_cc_seq_2_3=00000000
gtp1_cc_seq_2_3_k=true
gtp1_cc_seq_2_3_disp=false
gtp1_cc_seq_2_4_mask=true
gtp1_cc_seq_2_4=00000000
gtp1_cc_seq_2_4_k=true
gtp1_cc_seq_2_4_disp=false
gtp0_ppm_offset=0_(Synchronous)
gtp0_txrx_invert=011
gtp0_dec_mcomma_detect=false
gtp0_dec_pcomma_detect=false
gtp0_mcomma_detect=true
gtp0_pcomma_detect=true
gtp0_use_rx_eq=false
gtp0_termination_ctrl=10100
gtp0_termination_ovrd=false
gtp0_highpass_pole_location=Use_RXEQPOLE_Port
gtp0_use_resistor_cal_circuit=false
gtp0_second_order_cdr_loop=false
gtp0_use_port_pllpowerdown=false
gtp0_use_port_refclkpowerdown=false
gtp0_use_port_txpdownasynch=false
gtp0_rx_decode_seq_match=true
gtp0_rx_slide_mode=PCS
gtp0_termination_imp=50
gtp0_cdr_ph_adj_time=01010
gtp0_rx_en_idle_reset_fr=false
gtp0_rx_en_idle_hold_cdr=false
gtp0_rx_en_idle_reset_ph=false
gtp0_rx_en_idle_hold_dfe=false
gtp0_en_idle_reset_buf=false
gtp0_rx_idle_hi_cnt=1000
gtp0_rx_idle_lo_cnt=0000
gtp0_en_mode_reset_buf=false
gtp0_en_rate_reset_buf=false
gtp0_en_realign_reset_buf=false
gtp0_rx_fifo_addr_mode=Fast
gtp0_pma_cdr_scan=false
gtp0_pma_rx_cfg=0DCE089
gtp0_pma_tx_cfg=0DCE089
gtp0_rxprbserr_loopback=false
gtp0_show_realign_comma=false
gtp0_trans_time_rate=65535
gtp0_tx_drive_mode=false
gtp0_chan_bond_keep_align=false
gtp0_cb2_inh_cc_period=8
gtp0_rxrundisp_indicates_cc=false
gtp0_cc_keep_one_idle=false
gtp0_clk_cor_precedence=true
gtp0_clk_cor_repeat_wait=5
gtp1_ppm_offset=0_(Synchronous)
gtp1_txrx_invert=011
gtp1_dec_mcomma_detect=false
gtp1_dec_pcomma_detect=false
gtp1_mcomma_detect=true
gtp1_pcomma_detect=true
gtp1_use_rx_eq=false
gtp1_termination_ctrl=10100
gtp1_termination_ovrd=false
gtp1_highpass_pole_location=Use_RXEQPOLE_Port
gtp1_use_resistor_cal_circuit=false
gtp1_second_order_cdr_loop=false
gtp1_use_port_pllpowerdown=false
gtp1_use_port_refclkpowerdown=false
gtp1_use_port_txpdownasynch=false
gtp1_rx_decode_seq_match=true
gtp1_rx_slide_mode=PCS
gtp1_termination_imp=50
gtp1_cdr_ph_adj_time=01010
gtp1_rx_en_idle_reset_fr=false
gtp1_rx_en_idle_hold_cdr=false
gtp1_rx_en_idle_reset_ph=false
gtp1_rx_en_idle_hold_dfe=false
gtp1_en_idle_reset_buf=false
gtp1_rx_idle_hi_cnt=1000
gtp1_rx_idle_lo_cnt=0000
gtp1_en_mode_reset_buf=false
gtp1_en_rate_reset_buf=false
gtp1_en_realign_reset_buf=false
gtp1_rx_fifo_addr_mode=Fast
gtp1_pma_cdr_scan=false
gtp1_pma_rx_cfg=0DCE089
gtp1_pma_tx_cfg=0DCE089
gtp1_rxprbserr_loopback=false
gtp1_show_realign_comma=false
gtp1_trans_time_rate=65535
gtp1_tx_drive_mode=false
gtp1_chan_bond_keep_align=false
gtp1_cb2_inh_cc_period=8
gtp1_rxrundisp_indicates_cc=false
gtp1_cc_keep_one_idle=false
gtp1_clk_cor_precedence=true
gtp1_clk_cor_repeat_wait=5
This source diff could not be displayed because it is too large. You can view the blob instead.
REM
REM ____ ____
REM / /\/ /
REM /___/ \ / Vendor: Xilinx
REM \ \ \/ Version : 1.11
REM \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
REM / / Filename : implement_sh.ejava
REM /___/ /\
REM \ \ / \
REM \___\/\___\
REM
REM
REM implement.sh script
REM Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
REM
REM Set XST as default synthesizer
REM Read command line arguments
REM Change CWD to results
REM Clean results directory
REM Create results directory
REM Change current directory to results
ECHO WARNING: Removing existing results directory
RMDIR /S /Q results
MKDIR results
COPY xst.prj .\results\
COPY xst.scr .\results\
COPY *.ngc .\results\
REM Run Synthesis
ECHO "### Running Xst - "
xst -ifn xst.scr
COPY fmc_refclk_test_top.ngc .\results
cd .\results
REM Run ngdbuild
ngdbuild -uc ..\..\example_design\fmc_refclk_test_top.ucf -p xc6slx150t-fgg900-3 fmc_refclk_test_top.ngc fmc_refclk_test_top.ngd
REM end run ngdbuild section
REM Run map
ECHO 'Running NGD'
map -register_duplication on -global_opt speed -logic_opt on -retiming on -timing -ol high -p xc6slx150t-fgg900-3 -o mapped.ncd fmc_refclk_test_top.ngd
REM Run par
ECHO 'Running par'
par -ol high mapped.ncd routed.ncd
REM Report par results
ECHO 'Running design through bitgen'
bitgen -w routed.ncd
REM Trace Report
ECHO 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
REM Run netgen
ECHO 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -dir . -tm fmc_refclk_test_top -w routed.ncd routed.vhd
REM Change directory to implement
CD ..
#!/bin/bash
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : implement_sh.ejava
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## implement.sh script
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
#-----------------------------------------------------------------------------
# Script to synthesize and implement the RTL provided for the wizard
#-----------------------------------------------------------------------------
##---------------------Change CWD to results-------------------------------------
#Clean results directory
#Create results directory
#Change current directory to results
echo "WARNING: Removing existing results directory"
rm -rf results
mkdir results
cp xst.prj ./results
cp xst.scr ./results
cp *.ngc ./results
##-----------------------------Run Synthesis-------------------------------------
echo "### Running Xst - "
xst -ifn xst.scr
cp fmc_refclk_test_top.ngc ./results
cd ./results
##-------------------------------Run ngdbuild---------------------------------------
echo 'Running ngdbuild'
ngdbuild -uc ../../example_design/fmc_refclk_test_top.ucf -p xc6slx150t-fgg900-3 fmc_refclk_test_top.ngc fmc_refclk_test_top.ngd
#end run ngdbuild section
##-------------------------------Run map-------------------------------------------
echo 'Running map'
map -register_duplication on -global_opt speed -logic_opt on -retiming on -timing -ol high -p xc6slx150t-fgg900-3 -o mapped.ncd fmc_refclk_test_top.ngd
##-------------------------------Run par-------------------------------------------
echo 'Running par'
par -ol high mapped.ncd routed.ncd
##---------------------------Report par results-------------------------------------
echo 'Running design through bitgen'
bitgen -w routed.ncd
##-------------------------------Trace Report---------------------------------------
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
##-------------------------------Run netgen------------------------------------------
echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -dir . -tm fmc_refclk_test_top -w routed.ncd routed.vhd
#Change directory to implement
cd ..
REM
REM ____ ____
REM / /\/ /
REM /___/ \ / Vendor: Xilinx
REM \ \ \/ Version : 1.11
REM \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
REM / / Filename : implement_synplify_bat.ejava
REM /___/ /\
REM \ \ / \
REM \___\/\___\
REM
REM
REM implement_synplify.bat script
REM Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
REM
REM Set XST as default synthesizer
REM Read command line arguments
REM Change CWD to results
REM Clean results directory
REM Create results directory
REM Change current directory to results
ECHO WARNING: Removing existing results directory
RMDIR /S /Q results
MKDIR results
COPY synplify.prj .\results\
COPY *.ngc .\results\
REM Run Synthesis
ECHO "### Running Synplify Pro - "
synplify_pro -batch synplify.prj
COPY fmc_refclk_test_top.edf .\results
cd .\results
REM Run ngdbuild
ngdbuild -uc ..\..\example_design\fmc_refclk_test_top.ucf -p xc6slx150t-fgg900-3 fmc_refclk_test_top.edf fmc_refclk_test_top.ngd
REM end run ngdbuild section
REM Run map
ECHO 'Running NGD'
map -register_duplication on -global_opt speed -logic_opt on -retiming on -timing -ol high -w -p xc6slx150t-fgg900-3 -o mapped.ncd fmc_refclk_test_top.ngd
REM Run par
ECHO 'Running par'
par -ol high -w mapped.ncd routed.ncd mapped.pcf
REM Report par results
ECHO 'Running design through bitgen'
bitgen -g GWE_cycle:Done -g GTS_cycle:Done -g DriveDone:Yes -g StartupClk:Cclk -w routed.ncd
REM Trace Report
ECHO 'Running trce'
trce -e -l 1000 -s -3 routed -o routed mapped.pcf
REM Run netgen
ECHO 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -dir . -tm fmc_refclk_test_top -w routed.ncd routed.vhd
REM Change directory to implement
CD ..
#!/bin/bash
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : implement_synplify_sh.ejava
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## implement_synplify.sh script
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
#-----------------------------------------------------------------------------
# Script to synthesize and implement the RTL provided for the wizard
#-----------------------------------------------------------------------------
##---------------------Change CWD to results-------------------------------------
#Clean results directory
#Create results directory
#Change current directory to results
echo "WARNING: Removing existing results directory"
rm -rf results
mkdir results
cp synplify.prj ./results
cp *.ngc ./results
##-----------------------------Run Synthesis-------------------------------------
echo "### Running Synplify Pro - "
synplify_pro -batch synplify.prj
cp fmc_refclk_test_top.edf ./results
cd ./results
##-------------------------------Run ngdbuild---------------------------------------
echo 'Running ngdbuild'
ngdbuild -uc ../../example_design/fmc_refclk_test_top.ucf -p xc6slx150t-fgg900-3 fmc_refclk_test_top.edf fmc_refclk_test_top.ngd
#end run ngdbuild section
##-------------------------------Run map-------------------------------------------
echo 'Running map'
map -register_duplication on -global_opt speed -logic_opt on -retiming on -timing -ol high -w -p xc6slx150t-fgg900-3 -o mapped.ncd fmc_refclk_test_top.ngd
##-------------------------------Run par-------------------------------------------
echo 'Running par'
par -ol high -w mapped.ncd routed.ncd mapped.pcf
##---------------------------Report par results-------------------------------------
echo 'Running design through bitgen'
bitgen -g GWE_cycle:Done -g GTS_cycle:Done -g DriveDone:Yes -g StartupClk:Cclk -w routed.ncd
##-------------------------------Trace Report---------------------------------------
echo 'Running trce'
trce -e -l 1000 -s -3 routed -o routed mapped.pcf
##-------------------------------Run netgen------------------------------------------
echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -dir . -tm fmc_refclk_test_top -w routed.ncd routed.vhd
#Change directory to implement
cd ..
This source diff could not be displayed because it is too large. You can view the blob instead.
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : synplify.prj
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## synplify.prj
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
add_file -vhdl "../example_design/mgt_usrclk_source_pll.vhd"
add_file -vhdl "../example_design/frame_gen.vhd"
add_file -vhdl "../example_design/frame_check.vhd"
add_file -vhdl "../../fmc_refclk_test_tile.vhd"
add_file -vhdl "../../fmc_refclk_test.vhd"
add_file -vhdl "../example_design/fmc_refclk_test_top.vhd"
project -result_file "fmc_refclk_test_top.edf"
set_option -top_module fmc_refclk_test_top
set_option -technology spartan6
set_option -part xc6slx150t
set_option -package fgg900
set_option -speed_grade -3
#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
#map options
set_option -frequency 160.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -vlog_std v2001
#Do not generate ncf constraints file
set_option -write_apr_constraint 0
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : xst.prj
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## xst.prj
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
vhdl work "../example_design/mgt_usrclk_source_pll.vhd"
vhdl work "../example_design/frame_gen.vhd"
vhdl work "../example_design/frame_check.vhd"
vhdl work "../../fmc_refclk_test_tile.vhd"
vhdl work "../../fmc_refclk_test.vhd"
vhdl work "../example_design/fmc_refclk_test_top.vhd"
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : xst.scr
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## xst.scr
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
run
-ifn xst.prj
-ifmt mixed
-ofn fmc_refclk_test_top.ngc
-ofmt NGC
-p xc6slx150t-3fgg900
-top fmc_refclk_test_top
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy NO
-glob_opt AllClockNets
-rtlview Yes
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter ()
-case maintain
-slice_utilization_ratio 100
-fsm_extract YES
-fsm_encoding Auto
-ram_extract No
-ram_style Auto
-rom_extract No
-rom_style Auto
-shreg_extract YES
-resource_sharing YES
-mult_style auto
-iobuf YES
-max_fanout 500
-bufg 16
-register_duplication YES
-equivalent_register_removal YES
-register_balancing No
-signal_encoding user
-iob true
-slice_utilization_ratio_maxmargin 5
REM ################################################################################
REM ## ____ ____
REM ## / /\/ /
REM ## /___/ \ / Vendor: Xilinx
REM ## \ \ \/ Version : 1.11
REM ## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
REM ## / / Filename : simulate_isim.bat
REM ## /___/ /\
REM ## \ \ / \
REM ## \___\/\___\
REM ##
REM ##
REM ## Script SIMULATE_ISIM.BAT
REM ## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
REM ***************************** Beginning of Script ***************************
mkdir work
REM MGT Wrapper
vhpcomp -work work ..\..\..\fmc_refclk_test_tile.vhd
vhpcomp -work work ..\..\..\fmc_refclk_test.vhd
vhpcomp -work work ..\..\example_design\mgt_usrclk_source_pll.vhd
REM Example Design modules
vhpcomp -work work ..\..\example_design\frame_gen.vhd
vhpcomp -work work ..\..\example_design\frame_check.vhd
vhpcomp -work work ..\..\example_design\fmc_refclk_test_top.vhd
REM Other modules
vhpcomp -work work ..\sim_reset_mgt_model.vhd
REM Testbench file
vhpcomp -work work ..\demo_tb.vhd
REM Compile and link source files
fuse work.DEMO_TB -L unisim -L secureip -o demo_tb.exe
REM ##--Generate waveform trace--##
.\demo_tb.exe -gui -tclbatch wave_isim.tcl -wdb wave_isim
#!/bin/sh
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : simulate_isim.sh
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## Script SIMULATE_ISIM.SH
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##***************************** Beginning of Script ***************************
mkdir work
##MGT Wrapper
vhpcomp -work work ../../../fmc_refclk_test_tile.vhd;
vhpcomp -work work ../../../fmc_refclk_test.vhd;
vhpcomp -work work ../../example_design/mgt_usrclk_source_pll.vhd;
##Example Design modules
vhpcomp -work work ../../example_design/frame_gen.vhd;
vhpcomp -work work ../../example_design/frame_check.vhd;
vhpcomp -work work ../../example_design/fmc_refclk_test_top.vhd;
##Other modules
vhpcomp -work work ../sim_reset_mgt_model.vhd;
##Testbench file
vhpcomp -work work ../demo_tb.vhd;
#Compile and link source files
fuse work.DEMO_TB -L unisim -L secureip -o demo_tb.exe
##--Generate waveform trace--##
./demo_tb.exe -gui -tclbatch wave_isim.tcl -wdb wave_isim
REM ############################################################################
REM ____ ____
REM / /\/ /
REM /___/ \ / Vendor: Xilinx
REM \ \ \/ Version : 1.11
REM \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
REM / / Filename : simulate_ncsim.bat
REM /___/ /\
REM \ \ / \
REM \___\/\___\
REM
REM
REM Script SIMULATE_NCSIM.BAT
REM Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
REM
REM *************************** Beginning of Script ***************************
REM Ensure the follwoing
REM The library paths for UNISIMS_VER, SIMPRIMS_VER, XILINXCORELIB_VER,
REM UNISIM, SIMPRIM, XILINXCORELIB are set correctly in the cds.lib and hdl.var files.
REM Variables LMC_HOME and XILINX are set
REM Define the mapping for the work library in cds.lib file. DEFINE work ./work
mkdir work
REM MGT Wrapper
ncvhdl -RELAX -V93 -work work ../../../fmc_refclk_test_tile.vhd;
ncvhdl -RELAX -V93 -work work ../../../fmc_refclk_test.vhd;
ncvhdl -RELAX -V93 -work work ../../example_design/mgt_usrclk_source_pll.vhd;
REM Example Design modules
ncvhdl -RELAX -V93 -work work ../../example_design/frame_gen.vhd;
ncvhdl -RELAX -V93 -work work ../../example_design/frame_check.vhd;
ncvhdl -RELAX -V93 -work work ../../example_design/fmc_refclk_test_top.vhd;
ncvhdl -RELAX -V93 -work work ../demo_tb.vhd;
REM Other modules
ncvhdl -RELAX -V93 -work work ../sim_reset_mgt_model.vhd;
REM Elaborate Design
ncelab -relax -TIMESCALE 1ns/1ps -ACCESS +rwc work.DEMO_TB
ncsim +access+rw work.DEMO_TB -input @"simvision -input wave_ncsim.sv"
......@@ -7,6 +7,7 @@ files = [ "VME64xCore_Top.vhd",
"VME_CR_pack.vhd",
"VME_CSR_pack.vhd",
# "VME_DpBlockRam.vhd",
"VME_CRAM.vhd",
"VME_Funct_Match.vhd",
"VME_Init.vhd",
"VME_IRQ_Controller.vhd",
......
......@@ -28,7 +28,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
package VME_CSR_pack is
......
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