Commit ba20a0fe authored by Richard R. Carrillo's avatar Richard R. Carrillo Committed by Benoit Rat

SPEC test07 modified to test all DDR memory address lines

parent 6d7014ac
......@@ -166,6 +166,7 @@ class CGN4124:
# Start DMA transfer
def start_dma(self):
self.wr_reg(0,0x50000 + 2*4, 1) # Enable interrupt
self.dma_item_cnt = 0
self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_START, 1)
# The following two lines should be removed
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