Commit 98f1c44c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

svec cleanup: adding full pts structure with MAC assignment

parent 720b7351

Too many changes to show.

To preserve performance only 1000 of 1000+ files are displayed.

This folder includes the binary files loaded to the ApplicationFPGA during the SVEC PTS tests 01-17 execution.
Note that the same files are in the svec_pts_structure folder under /svec_pts_structure/bins
Here is the correspondance between test numbers, python files and binary files:
bus_test.bin -> test01.bin
bus_test.py -> test01.py
svec_pts_fmcsuppl_sfpeeprom.bin -> test02.bin
fmc_supplies.py -> test02.py
svec_pts_fmcconnect.bin -> test03.bin
fmc_connectors.py -> test03.py
svec_pts_fmcsuppl_sfpeeprom.bin -> test04.bin
sfp_eeprom.py -> test04.py
svec_pts_si570_tempid_eeprom.bin -> test05.bin
eeprom.py -> test05.py
svec_pts_si570_tempid_eeprom.bin -> test06.bin
therm_id.py -> test06.py
svec_pts_si570_tempid_eeprom.bin -> test07.bin
si570_osc.py -> test07.py
svec_pts_dac_vcxo_pll.bin -> test08.bin
dac_vxco_pll.py -> test08.py
svec_pts_usb_vmep2.bin -> test09.bin
dummy_usb_uart.py -> test09.py
svec_pts_leds_lemo.bin -> test10.bin
lemo.py -> test10.py
svec_pts_usb_vmep2.bin -> test11.bin
vmep2.py -> test11.py
svec_pts_sfp_sata_hsfmc.bin -> test12.bin
gtp_test.py -> test12.py
svec_afpga_gtp_clkfmc_top.bin -> test13.bin
gtp_clkfmc_test.py -> test13.py
svec_afpga_ddr_test.bin -> test14.bin
ddr_test.py -> test14.py
svec_pts_pcbvers_pushbutt.bin -> test15.bin
push_button.py -> test15.py
svec_pts_leds_lemo.bin -> test16.bin
leds.py -> test16.py
svec_pts_pcbvers_pushbutt.bin -> test17.bin
pcb_version.py -> test17.py
\ No newline at end of file
#!/bin/bash
xc3sprog -p 0 -c xpc svec_app.bit
xc3sprog -p 1 -c xpc svec_sys.bit
if [ "$1" == "sdbfs" ]; then
echo "Flashing SDBFS, this takes a while..."
xc3sprog -p 0 -c xpc -I sdbfs-svec.bin:W:0:BIN
else
echo "Flashing only bootloader"
xc3sprog -p 0 -c xpc -I svec-bootloader-v3-20140815.bin:W:0:BIN
fi
xc3sprog -p 1 -c xpc svec-bootloader-v3-20140815.bin:w:0:BIN
module top
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
reg TDO1;
reg [47:0] header;
reg [15:0] len;
reg have_header = 0;
assign MOSI = TDI ;
wire SEL1;
wire SHIFT;
wire RESET;
reg CS_GO = 0;
reg CS_GO_PREP = 0;
reg CS_STOP = 0;
reg CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg RAM_WE = 0;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1'b0),
.DIB(RAM_DI),
.ENA(1'b1),
.ENB(1'b1),
.SSRA(1'b0),
.SSRB(1'b0),
.WEA(1'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN6 BSCAN_SPARTAN6_inst
(
.CAPTURE(CAPTURE),
.DRCK(DRCK1),
.RESET(RESET),
.RUNTEST(),
.SEL(SEL1),
.SHIFT(SHIFT),
.TCK(),
.TDI(TDI),
.TMS(),
.UPDATE(UPDATE),
.TDO(TDO1)
);
assign CSB = !(CS_GO && !CS_STOP);
assign RAM_DI = MISO;
always@(posedge DRCK1)
TDO1 <= RAM_DO;
wire rst = CAPTURE || RESET || UPDATE || !SEL1;
always @(negedge DRCK1 or posedge rst)
if (rst)
begin
have_header <= 0;
CS_GO_PREP <= 0;
CS_STOP <= 0;
end
else
begin
CS_STOP <= CS_STOP_PREP;
if (!have_header)
begin
if (header[46:15] == 32'h59a659a6)
begin
len <= {header [14:0],1'b0};
have_header <= 1;
if ({header [14:0],1'b0} != 0)
begin
CS_GO_PREP <= 1;
end
end
end
else if (len != 0)
begin
len <= len -1;
end // if (!have_header)
end // else: !if(CAPTRE || RESET || UPDATE || !SEL1)
always @(posedge DRCK1 or posedge rst)
if (rst)
begin
CS_GO <= 0;
CS_STOP_PREP <= 0;
RAM_WADDR <= 0;
RAM_RADDR <=0;
RAM_WE <= 0;
end