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Production Test Suite
Commit 98a3d58b authored by Evangelia Gousiou's avatar Evangelia Gousiou
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added svec_pts_structure folder with all files from Julian's repo 

added ReadMe files in each folder
added Julian's SetupPTS doc
parent 42fe09ee
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test/svec/VHDL/ReadMe.txt 0 → 100644
View file @ 98a3d58b
This folder includes the vhdl files used for the generation of the binary files loaded to the Application FPGA during the different SVEC PTS tests execution.
The corresponding binaries can be found at the locations /pts/test/svec/firmwares and /pts/test/svec/svec_pts_structure/bins
Note that the vhdl for the System FPGA can be found here: http://www.ohwr.org/projects/svec/repository/revisions/master/show/hdl/top/sfpga_bootloader
\ No newline at end of file
test/svec/firmwares/ReadMe.txt 0 → 100644
View file @ 98a3d58b
This folder includes the binary files loaded to the Application FPGA during the SVEC PTS tests execution.
Note that the same files are in the svec_pts_structure folder under /svec_pts_structure/bins
Note that the binary file for the System FPGA can be found here: http://www.ohwr.org/projects/svec/repository/revisions/master/show/hdl/top/sfpga_bootloader
Here is the correspondance between test numbers, python files and binary files:
bus_test.bin -> test01.bin
bus_test.py -> test01.py
svec_pts_fmcsuppl_sfpeeprom.bin -> test02.bin
fmc_supplies.py -> test02.py
svec_pts_fmcconnect.bin -> test03.bin
fmc_connectors.py -> test03.py
svec_pts_fmcsuppl_sfpeeprom.bin -> test04.bin
sfp_eeprom.py -> test04.py
svec_pts_si570_tempid_eeprom.bin -> test05.bin
eeprom.py -> test05.py
svec_pts_si570_tempid_eeprom.bin -> test06.bin
therm_id.py -> test06.py
svec_pts_si570_tempid_eeprom.bin -> test07.bin
si570_osc.py -> test07.py
svec_pts_dac_vcxo_pll.bin -> test08.bin
dac_vxco_pll.py -> test08.py
svec_pts_usb_vmep2.bin -> test09.bin
dummy_usb_uart.py -> test09.py
svec_pts_leds_lemo.bin -> test10.bin
lemo.py -> test10.py
svec_pts_usb_vmep2.bin -> test11.bin
vmep2.py -> test11.py
svec_pts_sfp_sata_hsfmc.bin -> test12.bin
gtp_test.py -> test12.py
svec_afpga_gtp_clkfmc_top.bin -> test13.bin
gtp_clkfmc_test.py -> test13.py
svec_afpga_ddr_test.bin -> test14.bin
ddr_test.py -> test14.py
svec_pts_pcbvers_pushbutt.bin -> test15.bin
push_button.py -> test15.py
svec_pts_leds_lemo.bin -> test16.bin
leds.py -> test16.py
svec_pts_pcbvers_pushbutt.bin -> test17.bin
pcb_version.py -> test17.py
\ No newline at end of file
test/svec/python/ReadMe.txt 0 → 100644
View file @ 98a3d58b
This folder includes the python files of the 17 SVEC PTS tests.
Note that the same files are in the svec_pts_structure folder under /svec_pts_structure/pyts
Here is the correspondance between test numbers, python files and binary files:
bus_test.bin -> test01.bin
bus_test.py -> test01.py
svec_pts_fmcsuppl_sfpeeprom.bin -> test02.bin
fmc_supplies.py -> test02.py
svec_pts_fmcconnect.bin -> test03.bin
fmc_connectors.py -> test03.py
svec_pts_fmcsuppl_sfpeeprom.bin -> test04.bin
sfp_eeprom.py -> test04.py
svec_pts_si570_tempid_eeprom.bin -> test05.bin
eeprom.py -> test05.py
svec_pts_si570_tempid_eeprom.bin -> test06.bin
therm_id.py -> test06.py
svec_pts_si570_tempid_eeprom.bin -> test07.bin
si570_osc.py -> test07.py
svec_pts_dac_vcxo_pll.bin -> test08.bin
dac_vxco_pll.py -> test08.py
svec_pts_usb_vmep2.bin -> test09.bin
dummy_usb_uart.py -> test09.py
svec_pts_leds_lemo.bin -> test10.bin
lemo.py -> test10.py
svec_pts_usb_vmep2.bin -> test11.bin
vmep2.py -> test11.py
svec_pts_sfp_sata_hsfmc.bin -> test12.bin
gtp_test.py -> test12.py
svec_afpga_gtp_clkfmc_top.bin -> test13.bin
gtp_clkfmc_test.py -> test13.py
svec_afpga_ddr_test.bin -> test14.bin
ddr_test.py -> test14.py
svec_pts_pcbvers_pushbutt.bin -> test15.bin
push_button.py -> test15.py
svec_pts_leds_lemo.bin -> test16.bin
leds.py -> test16.py
svec_pts_pcbvers_pushbutt.bin -> test17.bin
pcb_version.py -> test17.py
test/svec/python/dac_vxco_pll.py
View file @ 98a3d58b
......@@ -333,39 +333,41 @@ def main(bus,tname,log,elg):
for i in range(len(dac_volts)):
grad = vcxo[i] / dac_volts[i]
log.write("VCXO OSC2: Frequency responds to change in DAC IC3 OK. DAC voltage = %3.2fV\n" % (dac_volts[i]))
if i > 0:
diff = grad - ograd
if diff < 0:
log.write("VCXO OSC2: Frequency responds to change in DAC IC3 OK. DAC=%3.2fV\n" % (dac_volts[i]))
else:
msg = "ERROR: VCXO OSC2: Frequency not responding to change in DAC IC3 control value"
pel.set(msg)
ograd = grad
log.write("\n")
for i in range(len(dac_volts)):
grad = pll_ic6[i] / dac_volts[i]
log.write("PLL IC6: Frequency responds to change in DAC IC7 OK. DAC voltage = %3.2fV\n" % (dac_volts[i]))
log.write("\n")
if i > 0:
diff = grad - ograd
if diff < 0:
log.write("PLL IC6: Frequency responds to change in DAC IC7 OK. DAC=%3.2fV\n" % (dac_volts[i]))
else:
msg = "ERROR: PLL IC6: Frequency not responding to change in DAC IC7 control value"
pel.set(msg)
ograd = grad
for i in range(len(dac_volts)):
grad = pll_ic12[i] / dac_volts[i]
log.write("PLL IC12: Frequency responds to change in DAC IC7 OK. DAC voltage = %3.2fV\n" % (dac_volts[i]))
log.write("\n")
ov = 0
for i in range(len(dac_volts)):
if ov < vcxo[i]:
continue
msg = "ERROR: VCXO OSC2: Frequency not responding to change in DAC IC3 control value"
pel.set(msg)
ov = 0
for i in range(len(dac_volts)):
if ov < pll_ic6[i]:
continue
msg = "ERROR: PLL IC6: Frequency not responding to change in DAC IC7 control value"
pel.set(msg)
grad = pll_ic12[i] / dac_volts[i]
if i > 0:
diff = grad - ograd
if diff < 0:
log.write("PLL IC12: Frequency responds to change in DAC IC7 OK. DAC=%3.2fV\n" % (dac_volts[i]))
else:
msg = "ERROR: PLL IC12: Frequency not responding to change in DAC IC7 control value"
pel.set(msg)
ograd = grad
ov = 0
for i in range(len(dac_volts)):
if ov < pll_ic12[i]:
continue
msg = "ERROR: PLL IC12: Frequency not responding to change in DAC IC7 control value"
pel.set(msg)
log.write("\n")
return pel.get()
test/svec/python/gtp_test.py
View file @ 98a3d58b
......@@ -38,7 +38,7 @@
## a miniNIC at offset 0x08000, |
## 16 KB of packet RAM at 0x10000. |
## |
## FW to load svec_pts_sfp_sata_hsfmc.bin (rename of svec_pts_12_sfp_sata_hsfmc.bin) |
## FW to load svec_pts_sfp_sata_hsfmc.bin |
## Authors Julian Lewis (Julian.Lewis@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 19/09/2012 |
......
test/svec/python/leds.py
View file @ 98a3d58b
......@@ -63,7 +63,7 @@ def main(bus,tname,log,elg):
"""
tests the: Front Panel LEDS and transceiver IC29
uses the: leds.py and svec_pts_leds_lemo_pushbutt.bin
uses the: leds.py and svec_pts_leds_lemo.bin
"""
BUTTON_DETECT_REG = 0x100
......
test/svec/python/lemo.py
View file @ 98a3d58b
......@@ -38,7 +38,7 @@
## |
## The VME driver needs to map x1000 bytes of memory. |
## |
## FW to load svec_pts_leds_lemo.bin |
## FW to load svec_pts_leds_lemo.bin |
## Authors Julian Lewis (Julian.Lewis@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 24/07/2012 |
......@@ -140,7 +140,7 @@ def main(bus,tname,log,elg):
"""
tests the: Front Panel LEMOS and transceiver IC16
uses the: lemo.py and svec_pts_leds_lemo_pushbutt.bin
uses the: lemo.py and svec_pts_leds_lemo.bin
"""
BUTTON_DETECT_REG = 0x100
......
test/svec/python/pcb_version.py
View file @ 98a3d58b
......@@ -74,7 +74,7 @@ def main(bus,tname,log,elg):
pel = PTS_ERROR_LOGGER(log,elg)
try:
# Reading the PCB_VERSION_REG register
# Reading the PCB_VERSION_REG register
version = bus.vv_read(PCB_VERSION_REG)
if version == 2:
......
test/svec/python/pts.py
View file @ 98a3d58b
......@@ -131,6 +131,7 @@ if __name__ == '__main__':
ok = raw_input(msg)
if ok.find("ok") != -1:
subprocess.call("grep ERROR /home/pts/ubuntu/pts/log/*.inf", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("grep WARNING /home/pts/ubuntu/pts/log/*.inf", shell=True, stdout=sys.stdout, stderr=sys.stderr)
print ""
print "--> You may now unplug the SVEC board %s-%s\n" % (sn1, sn2)
......
test/svec/python/push_button.py
View file @ 98a3d58b
......@@ -73,58 +73,17 @@ def main(bus,tname,log,elg):
"""
tests the: Front Panel Push-Button
uses the: push_button.py and svec_pts_leds_lemo_pushbutt.bin
uses the: push_button.py and svec_pts_pcbvers_pushbutt.bin
"""
BUTTON_DETECT_REG = 0x100
BUTTON_CLEAR_REG = 0x108
pel = PTS_ERROR_LOGGER(log,elg)
try:
# Resetting the DETECT register
bus.vv_write(BUTTON_CLEAR_REG,1)
bus.vv_write(BUTTON_CLEAR_REG,0)
time.sleep(0.5)
# Reading the DETECT register before pressing the button
button_bf = bus.vv_read(BUTTON_DETECT_REG)
inp = raw_input("--> Please press the front panel Push-Button.\n The LEDs should turn ON in red when pressing!\n Then type 'ok' to continue: ")
while True:
if inp.find("ok") != -1 or inp.find("OK") != -1:
# Reading the DETECT register after having pressed the button
button_af = bus.vv_read(BUTTON_DETECT_REG)
# Evaluating the results
if button_bf == 0 and button_af != 0:
msg = "Push-Button: Press detected OK"
print msg
log.write(msg + '\n')
elif button_bf != 0 and button_af != 0:
msg = "ERROR: Push-Button: Stuck pressed"
pel.set(msg)
else:
msg = "ERROR: Push-Button: Press not detected"
pel.set(msg)
break
else:
inp = raw_input('Please enter "ok" to continue:')
return pel.get()
except BusException, e:
raise PtsError("VME Exception: %s" % (e))
inp = raw_input("--> Please press the front panel Push-Button.\n The LEDs should turn ON in red when pressing!\n Type 'ok' if OK: ")
if inp.find("ok") != -1 or inp.find("OK") != -1:
msg = "Push button works OK"
log.write("%s\n" % msg)
else:
msg = "ERROR: Push button test failed"
pel.set(msg)
except BusWarning, e:
raise PtsError("VME Warning: %s" % (e))
return pel.get()
test/svec/svec_pts_structure/ReadMe.txt 0 → 100644
View file @ 98a3d58b
This folder includes all the files essential to running SVEC PTS.
If you want to create a new PTS system, please refer to the SetupPts.odt documentation.
The folder ubuntu gets copied onto the PTS laptop
The folder src contains sources to build stuff for ubuntu
On the MENA20 ubuntu/pts gets mounted
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