Commit 96dab0a1 authored by Richard R. Carrillo's avatar Richard R. Carrillo Committed by Benoit Rat

SPEC test07 modified to test DDR data lines first

parent ba20a0fe
#!/usr/bin/python #!/usr/bin/python
#coding: utf8
# Copyright CERN, 2012 (Seven Solutions S.L.)
# Author: Samuel Iglesias Gonsálvez?
# Author: Richard Carrillo <rcarrillo(AT)sevensols.com>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Website: http://www.sevensols.com
# Version: 1.1 (Last modifications: 17/01/2013)
import sys import sys
import rr import rr
...@@ -49,6 +58,11 @@ class CGN4124: ...@@ -49,6 +58,11 @@ class CGN4124:
DMA_ATTRIB_LAST = 0 DMA_ATTRIB_LAST = 0
DMA_ATTRIB_DIR = 1 DMA_ATTRIB_DIR = 1
# Mapping of the interrupt controller core (Wishbone address)
BAR0_INT_CTRL_ADDR = 0x50000
INT_CTRL_MASK_OFFSET = 2
INT_CTRL_MASK_DMA_DONE_BIT = 0
def rd_reg(self, bar, addr): def rd_reg(self, bar, addr):
return self.bus.iread(bar, addr, 4) return self.bus.iread(bar, addr, 4)
...@@ -99,15 +113,17 @@ class CGN4124: ...@@ -99,15 +113,17 @@ class CGN4124:
# GN4124 interrupt configuration # GN4124 interrupt configuration
def set_interrupt_config(self): def set_interrupt_config(self):
# Set interrupt line from FPGA (GPIO8) as input # Set interrupt line from FPGA (GPIO8) as input
self.wr_reg(self.GN4124_BAR, self.R_GPIO_DIR_MODE, (1<<self.GPIO_INT_SRC)) self.wr_reg(self.GN4124_BAR, self.R_GPIO_DIR_MODE, 1<<self.GPIO_INT_SRC)
# Set interrupt mask for all GPIO except for GPIO8 # Set interrupt mask for all GPIO except for GPIO8
self.wr_reg(self.GN4124_BAR, self.R_GPIO_INT_MASK_SET, ~(1<<self.GPIO_INT_SRC)) self.wr_reg(self.GN4124_BAR, self.R_GPIO_INT_MASK_SET, ~(1<<self.GPIO_INT_SRC))
# Make sure the interrupt mask is cleared for GPIO8 # Make sure the interrupt mask is cleared for GPIO8
self.wr_reg(self.GN4124_BAR, self.R_GPIO_INT_MASK_CLR, (1<<self.GPIO_INT_SRC)) self.wr_reg(self.GN4124_BAR, self.R_GPIO_INT_MASK_CLR, 1<<self.GPIO_INT_SRC)
# Interrupt on rising edge of GPIO8 # Interrupt on rising edge of GPIO8
self.wr_reg(self.GN4124_BAR, self.R_GPIO_INT_VALUE, (1<<self.GPIO_INT_SRC)) self.wr_reg(self.GN4124_BAR, self.R_GPIO_INT_VALUE, 1<<self.GPIO_INT_SRC)
# GPIO as interrupt 0 source # GPIO as interrupt 0 source
self.wr_reg(self.GN4124_BAR, self.R_INT_CFG0, (1<<self.INT_CFG0_GPIO)) self.wr_reg(self.GN4124_BAR, self.R_INT_CFG0, 1<<self.INT_CFG0_GPIO)
# Enable interrupt in interrupt mask register
self.wr_reg(0,self.BAR0_INT_CTRL_ADDR + self.INT_CTRL_MASK_OFFSET*4, 1 << self.INT_CTRL_MASK_DMA_DONE_BIT)
# Get DMA controller status # Get DMA controller status
def get_dma_status(self): def get_dma_status(self):
...@@ -166,7 +182,6 @@ class CGN4124: ...@@ -166,7 +182,6 @@ class CGN4124:
# Start DMA transfer # Start DMA transfer
def start_dma(self): def start_dma(self):
self.wr_reg(0,0x50000 + 2*4, 1) # Enable interrupt
self.dma_item_cnt = 0 self.dma_item_cnt = 0
self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_START, 1) self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_START, 1)
# The following two lines should be removed # The following two lines should be removed
......
...@@ -3,20 +3,18 @@ ...@@ -3,20 +3,18 @@
# Copyright CERN, 2012 (Seven Solutions S.L.) # Copyright CERN, 2012 (Seven Solutions S.L.)
# Author: Richard Carrillo <rcarrillo(AT)sevensols.com> # Author: Richard Carrillo <rcarrillo(AT)sevensols.com>
# Author: Rafael Rodríguez <rrodriguez(AT)sevensols.com>
# Licence: GPL v2 or later. # Licence: GPL v2 or later.
# Website: http://www.ohwr.org # Website: http://www.ohwr.org
# Website: http://www.sevensols.com # Website: http://www.sevensols.com
# Version: 1.0 (Last modifications: 21/12/2012) # Version: 1.1 (Last modifications: 17/01/2013)
# remove unused libraries?
import sys import sys
import rr import rr
import random
import time import time
import spi
import i2c
import gn4124 import gn4124
import os import os
import math
from ptsexcept import * from ptsexcept import *
...@@ -27,8 +25,8 @@ User intervention required: No ...@@ -27,8 +25,8 @@ User intervention required: No
Procedure details: Procedure details:
- Load FPGA firmware - Load FPGA firmware
- Set local bus frequency - Set local bus frequency
- Test the connectivity of address lines
- Test the connectivity of data lines - Test the connectivity of data lines
- Test the connectivity of address lines
""" """
class test07: class test07:
...@@ -91,6 +89,10 @@ class test07: ...@@ -91,6 +89,10 @@ class test07:
break break
return ret_error return ret_error
def find_different_bit(self,dword0,dword1):
""" Return the number of the most significant bit which is different in the two values """
return int(math.floor(math.log(dword0^dword1,2)))
def test_data_lines(self): def test_data_lines(self):
""" Test the memory-interface data lines """ """ Test the memory-interface data lines """
ret_error=None ret_error=None
...@@ -106,7 +108,7 @@ class test07: ...@@ -106,7 +108,7 @@ class test07:
self.gennum.wait_irq() self.gennum.wait_irq()
page_data = self.gennum.get_memory_page(0) page_data = self.gennum.get_memory_page(0)
if page_data[0] <> value_list[data_line]: if page_data[0] <> value_list[data_line]:
error_str="Value read from memory (0x{:X}) is differnt from what was expected (0x{:X}) at Wishbone address (0x{:X}). DDR-interface data line/s is tied to Vcc or GND, or unconnected.".format(page_data[0],value_list[data_line],test_data_addr) error_str="Value read from memory (0x{:X}) is differnt from what was expected (0x{:X}) at Wishbone address (0x{:X}). At least DDR-interface data line {} is tied to Vcc or GND, or unconnected.".format(page_data[0],value_list[data_line],test_data_addr,self.find_different_bit(page_data[0],value_list[data_line]))
print(error_str) print(error_str)
ret_error="While testing DDR data lines: "+error_str ret_error="While testing DDR data lines: "+error_str
break break
...@@ -121,6 +123,7 @@ def main(default_directory="."): ...@@ -121,6 +123,7 @@ def main(default_directory="."):
bitstream = os.path.join(default_directory, path_firmware) bitstream = os.path.join(default_directory, path_firmware)
print "Loading firmware: %s" % (firmware_loader + ' ' + bitstream) print "Loading firmware: %s" % (firmware_loader + ' ' + bitstream)
os.system( firmware_loader + ' ' + bitstream ) os.system( firmware_loader + ' ' + bitstream )
#time.sleep(2)
# Load board library and open the corresponding device # Load board library and open the corresponding device
print "Loading hardware access library and opening device\n" print "Loading hardware access library and opening device\n"
...@@ -131,11 +134,11 @@ def main(default_directory="."): ...@@ -131,11 +134,11 @@ def main(default_directory="."):
init_test_time = time.time() init_test_time = time.time()
print "Configuring board" print "Configuring board"
test=test07(spec) test=test07(spec)
print "\nChecking DDR address and bank lines" print "\nChecking DDR data lines"
ret_error=test.test_address_and_bank_lines() ret_error=test.test_data_lines()
if ret_error==None: if ret_error==None:
print "Checking DDR data lines" print "Checking DDR address and bank lines"
ret_error=test.test_data_lines() ret_error=test.test_address_and_bank_lines()
end_test_time = time.time() end_test_time = time.time()
print "\nEnd of Test07" print "\nEnd of Test07"
......
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