Commit 674438f3 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Tomasz Wlostowski

fix DDMTD PLL locking issue

parent c3d43480
......@@ -330,13 +330,17 @@ int fdelay_dmtd_calibration(fdelay_device_t *dev, const char *filename, int setp
/* Disable PTP and enter free-running master mode */
if(wrc_shell_exec(dev, "ptp stop", resp) < 0)
return -1;
if(wrc_shell_exec(dev, "mode master", resp) < 0)
return -1;
// if(wrc_shell_exec(dev, "mode master", resp) < 0)
// return -1;
sleep(1);
/* And lock the DMTD oscillator to the FMC clock instead of the SPEC 125 MHz oscillator. Set the FMC VCO DAC to 0
to have some headroom */
if(wrc_shell_exec(dev, "pll sdac 1 0", resp) < 0)
return -1;
// if(wrc_shell_exec(dev, "pll sdac 1 0", resp) < 0)
// return -1;
if(wrc_shell_exec(dev, "pll init 2 1 1", resp) < 0)
return -1;
......
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