Commit 633f6b00 authored by Matthieu Cattin's avatar Matthieu Cattin

Remove unused files from previous fmc reference clock for gtp project.

parent b718a368
fetchto = "ip_cores"
modules = {
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git" ],
"svn" : [ "http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl" ]
}
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-10
-- Last update: 2012-01-10
-- Last update: 2012-08-29
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -66,7 +66,7 @@ architecture rtl of gc_pulse_synchronizer is
constant c_sync_stages : integer := 3;
signal ready : std_logic;
signal ready, d_p_d0 : std_logic;
signal in_ext, out_ext : std_logic;
signal out_feedback : std_logic;
......@@ -104,8 +104,12 @@ begin -- rtl
if rst_n_i = '0' then
ready <= '1';
in_ext <= '0';
d_p_d0 <= '0';
elsif rising_edge(clk_in_i) then
if(ready = '1' and d_p_i = '1') then
d_p_d0 <= d_p_i;
if(ready = '1' and d_p_i = '1' and d_p_d0 = '0') then
in_ext <= '1';
ready <= '0';
elsif(in_ext = '1' and out_feedback = '1') then
......
......@@ -12,7 +12,7 @@ peripheral {
field {
name = "VIC Enable";
description = "1: enables VIC operation\n0: disables VIC operation";
description = "- 1: enables VIC operation\n- 0: disables VIC operation";
prefix = "ENABLE";
type = BIT;
access_dev = READ_ONLY;
......@@ -21,12 +21,31 @@ peripheral {
field {
name = "VIC output polarity";
description = "1: IRQ output is active high\n0: IRQ output is active low";
description = "- 1: IRQ output is active high\n- 0: IRQ output is active low";
prefix = "POL";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Emulate Edge sensitive output";
description = "- 1: Forces a low pulse of <code>EMU_LEN</code> clock cycles at each write to <code>EOIR</code>. Useful for edge-only IRQ controllers such as Gennum.\n- 0: Normal IRQ master line behavior";
prefix = "EMU_EDGE";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Emulated Edge pulse timer";
description = "Length of the delay (in <code>clk_sys_i</code> cycles) between write to <code>EOIR</code> and re-assertion of <code>irq_master_o</code>.";
prefix = "EMU_LEN";
type = SLV;
size = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
......@@ -35,7 +54,7 @@ peripheral {
field {
name = "Raw interrupt status";
description = "Each bit reflects the current state of corresponding IRQ input line.\nread 1: interrupt line is currently active\nread 0: interrupt line is inactive";
description = "Each bit reflects the current state of corresponding IRQ input line.\n- read 1: interrupt line is currently active\n- read 0: interrupt line is inactive";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
......@@ -49,7 +68,7 @@ peripheral {
field {
name = "Enable IRQ";
description = "Write 1: enables interrupt associated with written bit\nWrite 0: no effect";
description = "- write 1: enables interrupt associated with written bit\n- write 0: no effect";
type = PASS_THROUGH;
size = 32;
};
......@@ -61,7 +80,7 @@ peripheral {
field {
name = "Disable IRQ";
description = "Write 1: enables interrupt associated with written bit\nWrite 0: no effect";
description = "- write 1: enables interrupt associated with written bit\n- write 0: no effect";
type = PASS_THROUGH;
size = 32;
};
......@@ -73,7 +92,7 @@ peripheral {
field {
name = "IRQ disabled/enabled";
description = "Read 1: interrupt associated with bitfield is enabled\nRead 0: interrupt is disabled";
description = "- read 1: interrupt associated with read bit is enabled\n- read 0: interrupt is disabled";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -112,7 +131,7 @@ peripheral {
field {
name = "End of Interrupt";
description = "Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s).";
description = "Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.";
type = PASS_THROUGH;
size = 32;
};
......
......@@ -5,7 +5,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2012-01-13
-- Last update: 2012-09-27
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -45,22 +45,22 @@ entity wb_vic is
);
port (
clk_sys_i : in std_logic; -- wishbone clock
rst_n_i : in std_logic; -- reset
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
clk_sys_i : in std_logic; -- wishbone clock
rst_n_i : in std_logic; -- reset
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0); -- IRQ inputs
irq_master_o : out std_logic -- master IRQ output (multiplexed line, to the CPU)
irq_master_o : out std_logic -- master IRQ output (multiplexed line, to the CPU)
);
end wb_vic;
......@@ -73,21 +73,23 @@ architecture syn of wb_vic is
in_i : in std_logic_vector(31 downto 0);
out_o : out std_logic_vector(4 downto 0));
end component;
component wb_slave_vic
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
vic_ctl_enable_o : out std_logic;
vic_ctl_pol_o : out std_logic;
vic_ctl_emu_edge_o : out std_logic;
vic_ctl_emu_len_o : out std_logic_vector(15 downto 0);
vic_risr_i : in std_logic_vector(31 downto 0);
vic_ier_o : out std_logic_vector(31 downto 0);
vic_ier_wr_o : out std_logic;
......@@ -103,13 +105,15 @@ architecture syn of wb_vic is
vic_ivt_ram_data_o : out std_logic_vector(31 downto 0);
vic_ivt_ram_rd_i : in std_logic);
end component;
type t_state is (WAIT_IRQ, PROCESS_IRQ, WAIT_ACK, WAIT_MEM, WAIT_IDLE);
signal irqs_i_reg : std_logic_vector(32 downto 0);
signal vic_ctl_enable : std_logic;
signal vic_ctl_pol : std_logic;
signal vic_ctl_emu_edge : std_logic;
signal vic_ctl_emu_len : std_logic_vector(15 downto 0);
signal vic_risr : std_logic_vector(31 downto 0);
signal vic_ier : std_logic_vector(31 downto 0);
signal vic_ier_wr : std_logic;
......@@ -133,9 +137,10 @@ architecture syn of wb_vic is
signal irq_id_encoded : std_logic_vector(4 downto 0);
signal state : t_state;
signal wb_in : t_wishbone_slave_in;
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal timeout_count : unsigned(15 downto 0);
begin -- syn
......@@ -168,16 +173,16 @@ begin -- syn
vic_ivt_ram_addr <= current_irq;
U_Slave_adapter: wb_slave_adapter
U_Slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
sl_adr_i => wb_adr_i,
sl_dat_i => wb_dat_i,
......@@ -191,27 +196,29 @@ begin -- syn
master_i => wb_out,
master_o => wb_in);
wb_out.stall <= '0';
wb_out.rty <= '0';
wb_out.err <= '0';
wb_out.int <= '0';
wb_out.rty <= '0';
wb_out.err <= '0';
wb_out.int <= '0';
U_wb_controller : wb_slave_vic
port map (
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_in.adr(5 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(5 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
vic_ctl_enable_o => vic_ctl_enable,
vic_ctl_pol_o => vic_ctl_pol,
vic_ctl_emu_edge_o => vic_ctl_emu_edge,
vic_ctl_emu_len_o => vic_ctl_emu_len,
vic_risr_i => vic_risr,
vic_ier_o => vic_ier,
vic_ier_wr_o => vic_ier_wr,
......@@ -313,9 +320,19 @@ begin -- syn
swi_mask <= (others => '0');
end if;
timeout_count <= (others => '0');
when WAIT_IDLE =>
state <= WAIT_IRQ;
if(vic_ctl_emu_edge = '0') then
state <= WAIT_IRQ;
else
irq_master_o <= not vic_ctl_pol;
timeout_count <= timeout_count + 1;
if(timeout_count = unsigned(vic_ctl_emu_len)) then
state <= WAIT_IRQ;
end if;
end if;
end case;
end if;
end if;
......
......@@ -7,6 +7,7 @@ files = [ "VME64xCore_Top.vhd",
"VME_CR_pack.vhd",
"VME_CSR_pack.vhd",
# "VME_DpBlockRam.vhd",
"VME_CRAM.vhd",
"VME_Funct_Match.vhd",
"VME_Init.vhd",
"VME_IRQ_Controller.vhd",
......
......@@ -28,7 +28,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
package VME_CSR_pack is
......
......@@ -686,12 +686,12 @@ function f_log2_size (A : natural) return natural;
d_o : out std_logic_vector(63 downto 0)
);
end component VME_swapper;
component Reg32bit is
port (
component Reg32bit is
port (
reset, clk_i, enable: in std_logic;
di : in std_logic_vector(31 downto 0);
di : in std_logic_vector(31 downto 0);
do: out std_logic_vector(31 downto 0)
);
);
end component Reg32bit;
component FlipFlopD is
port (
......
*.*\#
\#*
.\#*
*.*~
syn/
work
*.wlf
modelsim.ini
transcript
*.vstf
*.bak
*.vcd
*.h
doc/
*.o
*.bin
*.elf
Makefile
\ No newline at end of file
fetchto = "ip_cores"
modules = {"local" :
[ "modules/fabric",
"modules/wr_tbi_phy",
"modules/timing",
"modules/wr_mini_nic",
"modules/wr_softpll_ng",
"modules/wr_endpoint",
"modules/wr_pps_gen",
"modules/wrc_core" ],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git"
}
Currently this is only a test repo for testing hdlmake. Please do not use any modules from here as they are very likely to be broken.
\ No newline at end of file
files = ["wr_fabric_pkg.vhd", "xwb_fabric_sink.vhd", "xwb_fabric_source.vhd"]
\ No newline at end of file
library ieee;
use ieee.std_logic_1164.all;
package wr_fabric_pkg is
constant c_WRF_DATA : std_logic_vector(1 downto 0) := "00";
constant c_WRF_OOB : std_logic_vector(1 downto 0) := "01";
constant c_WRF_STATUS : std_logic_vector(1 downto 0) := "10";
constant c_WRF_USER : std_logic_vector(1 downto 0) := "11";
constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
type t_wrf_status_reg is record
is_hp : std_logic;
has_smac : std_logic;
has_crc : std_logic;
error : std_logic;
tag_me : std_logic;
match_class : std_logic_vector(7 downto 0);
end record;
type t_wrf_source_out is record
adr : std_logic_vector(1 downto 0);
dat : std_logic_vector(15 downto 0);
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : std_logic_vector(1 downto 0);
end record;
type t_wrf_source_in is record
ack : std_logic;
stall : std_logic;
err : std_logic;
rty : std_logic;
end record;
type t_wrf_oob is record
valid: std_logic;
oob_type : std_logic_vector(3 downto 0);
ts_r : std_logic_vector(27 downto 0);
ts_f : std_logic_vector(3 downto 0);
frame_id : std_logic_vector(15 downto 0);
port_id : std_logic_vector(5 downto 0);
end record;
subtype t_wrf_sink_in is t_wrf_source_out;
subtype t_wrf_sink_out is t_wrf_source_in;
type t_wrf_source_in_array is array (natural range <>) of t_wrf_source_in;
type t_wrf_source_out_array is array (natural range <>) of t_wrf_source_out;
subtype t_wrf_sink_in_array is t_wrf_source_out_array;
subtype t_wrf_sink_out_array is t_wrf_source_in_array;
function f_marshall_wrf_status (stat : t_wrf_status_reg) return std_logic_vector;
function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg;
constant c_dummy_src_in : t_wrf_source_in :=
('0', '0', '0', '0');
constant c_dummy_snk_in : t_wrf_sink_in :=
("XX", "XXXXXXXXXXXXXXXX", '0', '0', '0', "XX");
end wr_fabric_pkg;
package body wr_fabric_pkg is
function f_marshall_wrf_status(stat : t_wrf_status_reg)
return std_logic_vector is
variable tmp : std_logic_vector(15 downto 0);
begin
tmp(0) := stat.is_hp;
tmp(1) := stat.error;
tmp(2) := stat.has_smac;
tmp(3) := stat.has_crc;
tmp(15 downto 8) := stat.match_class;
return tmp;
end function;
function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg is
variable tmp : t_wrf_status_reg;
begin
tmp.is_hp := stat(0);
tmp.error := stat(1);
tmp.has_smac := stat(2);
tmp.has_crc := stat(3);
tmp.match_class := stat(15 downto 8);
return tmp;
end function;
end wr_fabric_pkg;
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-16
-- Last update: 2012-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-16 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity xwb_fabric_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end xwb_fabric_sink;
architecture rtl of xwb_fabric_sink is
constant c_fifo_width : integer := 16 + 2 + 4;
signal q_valid, full, we, rd : std_logic;
signal fin, fout, fout_reg : std_logic_vector(c_fifo_width-1 downto 0);
signal cyc_d0, rd_d0 : std_logic;
signal pre_sof, pre_eof, pre_bytesel, pre_dvalid : std_logic;
signal post_sof, post_dvalid : std_logic;
signal post_addr : std_logic_vector(1 downto 0);
signal post_data : std_logic_vector(15 downto 0);
signal snk_out : t_wrf_sink_out;
begin -- rtl
p_delay_cyc_and_rd : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_d0 <= '0';
rd_d0 <= '0';
else
if(full = '0') then
cyc_d0 <= snk_i.cyc;
end if;
rd_d0 <= rd;
end if;
end if;
end process;
pre_sof <= snk_i.cyc and not cyc_d0; -- sof
pre_eof <= not snk_i.cyc and cyc_d0; -- eof
pre_bytesel <= not snk_i.sel(0); -- bytesel
pre_dvalid <= snk_i.stb and snk_i.we and snk_i.cyc and not snk_out.stall; -- data valid
fin(15 downto 0) <= snk_i.dat;
fin(17 downto 16) <= snk_i.adr;
fin(21 downto 18) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
snk_out.stall <= full or (snk_i.cyc and not cyc_d0);
snk_out.err <= '0';
snk_out.rty <= '0';
p_gen_ack : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
snk_out.ack <= '0';
else
snk_out.ack <= snk_i.cyc and snk_i.stb and snk_i.we and not snk_out.stall;
end if;
end if;
end process;
snk_o <= snk_out;
we <= '1' when fin(21 downto 18) /= "0000" and full = '0' else '0';
rd <= q_valid and dreq_i and not post_sof;
U_FIFO : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => 16)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid);
p_fout_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fout_reg <= (others => '0');
elsif(rd = '1') then
fout_reg <= fout;
end if;
end if;
end process;
post_data <= fout_reg(15 downto 0);
post_addr <= fout_reg(17 downto 16);
post_sof <= fout_reg(21) and rd_d0; --and q_valid;
post_dvalid <= fout_reg(18);
sof_o <= post_sof and rd_d0;
dvalid_o <= post_dvalid and rd_d0;
error_o <= '1' when rd_d0 = '1' and (post_addr = c_WRF_STATUS) and (f_unmarshall_wrf_status(post_data).error = '1') else '0';
eof_o <= fout_reg(20) and rd_d0;
bytesel_o <= fout_reg(19);
data_o <= post_data;
addr_o <= post_addr;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity wb_fabric_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_dat_i : in std_logic_vector(15 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_sel_i : in std_logic_vector(1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_ack_o : out std_logic;
snk_err_o : out std_logic;
snk_rty_o : out std_logic;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end wb_fabric_sink;
architecture wrapper of wb_fabric_sink is
component xwb_fabric_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic);
end component;
signal snk_in : t_wrf_sink_in;
signal snk_out : t_wrf_sink_out;
begin -- wrapper
U_Wrapped_Sink : xwb_fabric_sink
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
snk_i => snk_in,
snk_o => snk_out,
addr_o => addr_o,
data_o => data_o,
dvalid_o => dvalid_o,
sof_o => sof_o,
eof_o => eof_o,
error_o => error_o,
bytesel_o => bytesel_o,
dreq_i => dreq_i);
snk_in.adr <= snk_adr_i;
snk_in.dat <= snk_dat_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_in.cyc <= snk_cyc_i;
snk_in.sel <= snk_sel_i;
snk_stall_o <= snk_out.stall;
snk_ack_o <= snk_out.ack;
snk_err_o <= snk_out.err;
snk_rty_o <= snk_out.rty;
end wrapper;
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity xwb_fabric_source is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
-- Decoded & buffered fabric
addr_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(15 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic
);
end xwb_fabric_source;
architecture rtl of xwb_fabric_source is
constant c_fifo_width : integer := 16 + 2 + 4;
signal q_valid, full, we, rd, rd_d0 : std_logic;
signal fin, fout : std_logic_vector(c_fifo_width-1 downto 0);
signal pre_dvalid : std_logic;
signal pre_eof : std_logic;
signal pre_data : std_logic_vector(15 downto 0);
signal pre_addr : std_logic_vector(1 downto 0);
signal post_dvalid, post_eof, post_bytesel, post_sof : std_logic;
signal err_status : t_wrf_status_reg;
signal cyc_int : std_logic;
begin -- rtl
err_status.error <= '1';
dreq_o <= not full;
rd <= not src_i.stall;
we <= sof_i or eof_i or error_i or dvalid_i;
pre_dvalid <= dvalid_i or error_i;
pre_data <= data_i when (error_i = '0') else f_marshall_wrf_status(err_status);
pre_addr <= addr_i when (error_i = '0') else c_WRF_STATUS;
pre_eof <= error_i or eof_i;
fin <= sof_i & pre_eof & bytesel_i & pre_dvalid & pre_addr & pre_data;
U_FIFO : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => 16)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid);
post_sof <= fout(21);
post_eof <= fout(20);
post_dvalid <= fout(18);
p_gen_cyc : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_int <= '0';
else
if(src_i.stall = '0' and q_valid = '1') then
if(post_sof = '1')then
cyc_int <= '1';
elsif(post_eof = '1') then
cyc_int <= '0';
end if;
end if;
end if;
end if;
end process;
src_o.cyc <= cyc_int or post_sof;
src_o.we <= '1';
src_o.stb <= post_dvalid and q_valid;
src_o.sel <= '1' & not fout(19);
src_o.dat <= fout(15 downto 0);
src_o.adr <= fout(17 downto 16);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.wr_fabric_pkg.all;
entity wb_fabric_source is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
src_sel_o : out std_logic_vector(1 downto 0);
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_stall_i : in std_logic;
src_ack_i : in std_logic;
src_err_i : in std_logic;
-- Decoded & buffered fabric
addr_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(15 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic
);
end wb_fabric_source;
architecture wrapper of wb_fabric_source is
component xwb_fabric_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
addr_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(15 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic);
end component;
signal src_in : t_wrf_source_in;
signal src_out : t_wrf_source_out;
begin -- wrapper
U_Wrapped_Source : xwb_fabric_source
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
src_i => src_in,
src_o => src_out,
addr_i => addr_i,
data_i => data_i,
dvalid_i => dvalid_i,
sof_i => sof_i,
eof_i => eof_i,
error_i => error_i,
bytesel_i => bytesel_i,
dreq_o => dreq_o);
src_cyc_o <= src_out.cyc;
src_stb_o <= src_out.stb;
src_we_o <= src_out.we;
src_sel_o <= src_out.sel;
src_adr_o <= src_out.adr;
src_dat_o <= src_out.dat;
src_in.rty <= '0';
src_in.err <= src_err_i;
src_in.ack <= src_ack_i;
src_in.stall <= src_stall_i;
end wrapper;
files = [
"lpc_peripheral.vhd",
"lpc_uart.vhd",
"lpc_uart_pkg.vhd",
"postcode.vhd",
"serirq_defines.v",
"serirq_slave.v"
]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity lpc_uart is
port (
lpc_clk: in std_logic;
lpc_serirq: inout std_logic;
lpc_ad: inout std_logic_vector(3 downto 0);
lpc_frame_n: in std_logic;
lpc_reset_n: in std_logic;
serial_rxd: in std_logic;
serial_txd: out std_logic;
serial_dtr: out std_logic;
serial_dcd: in std_logic;
serial_dsr: in std_logic;
serial_ri: in std_logic;
serial_cts: in std_logic;
serial_rts: out std_logic;
seven_seg_L: out std_logic_vector(7 downto 0); -- SSeg Data output
seven_seg_H: out std_logic_vector(7 downto 0) -- SSeg Data output
);
end lpc_uart;
architecture lpc_uart_arch of lpc_uart is
component lpc_decoder is
Port (
lclk: in std_logic; -- LPC: 33MHz clock (rising edge)
lframe_n: in std_logic; -- LPC: frame, active low
lreset_n: in std_logic; -- LPC: reset, active low
lad: in std_logic_vector(3 downto 0); -- LPC: multiplexed bus
paddr: out std_logic_vector(15 downto 0); -- port addr
pdata_in: out std_logic_vector(7 downto 0); -- data to the slave
pdata_out: in std_logic_vector(7 downto 0); -- data from the slave
paddr_valid: out std_logic;
pdata_valid: out std_logic
);
end component;
component lpc_peripheral is
port (
clk_i: in std_logic;
nrst_i: in std_logic;
lframe_i: in std_logic; -- LPC Frame input (active high)
lad_oe: out std_logic; -- LPC AD Output Enable
lad_i: in std_logic_vector(3 downto 0); -- LPC AD Input Bus
lad_o: out std_logic_vector(3 downto 0); -- LPC AD Output Bus
dma_chan_o: out std_logic_vector(2 downto 0); -- DMA Channel
dma_tc_o: out std_logic; -- DMA Terminal Count
wbm_err_i: in std_logic;
io_bus_dat_o: out std_logic_vector(7 downto 0);
io_bus_dat_i: in std_logic_vector(7 downto 0);
io_bus_addr: out std_logic_vector(15 downto 0);
io_bus_we: out std_logic;
io_ack: in std_logic;
io_data_valid: out std_logic
);
end component;
component postcode is
port (
lclk: in std_logic;
paddr: in std_logic_vector(15 downto 0);
pdata: in std_logic_vector(7 downto 0);
addr_hit: out std_logic;
data_valid: in std_logic;
seven_seg_L: out std_logic_vector(7 downto 0); -- SSeg Data output
seven_seg_H: out std_logic_vector(7 downto 0) -- SSeg Data output
);
end component;
component uart_16750 is
port (
CLK : in std_logic; -- Clock 24Mhz
RST : in std_logic; -- Reset
BAUDCE : in std_logic; -- Baudrate generator clock enable
CS : in std_logic; -- Chip select
WR : in std_logic; -- Write to UART
RD : in std_logic; -- Read from UART
A : in std_logic_vector(2 downto 0); -- Register select
DIN : in std_logic_vector(7 downto 0); -- Data bus input
DOUT : out std_logic_vector(7 downto 0); -- Data bus output
DDIS : out std_logic; -- Driver disable
INT : out std_logic; -- Interrupt output
OUT1N : out std_logic; -- Output 1
OUT2N : out std_logic; -- Output 2
RCLK : in std_logic; -- Receiver clock (16x baudrate)
BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate)
RTSN : out std_logic; -- RTS output
DTRN : out std_logic; -- DTR output
CTSN : in std_logic; -- CTS input
DSRN : in std_logic; -- DSR input
DCDN : in std_logic; -- DCD input
RIN : in std_logic; -- RI input
SIN : in std_logic; -- Receiver input
SOUT : out std_logic -- Transmitter output
);
end component;
component uart_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC;
c1 : out std_logic
);
END component;
component serirq_slave is
port (
clk_i : in std_logic;
nrst_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0);
serirq_o : out std_logic;
serirq_i : in std_logic;
serirq_oe : out std_logic
);
end component;
constant uart_base_addr: unsigned(15 downto 0) := x"03F8";
signal io_addr: std_logic_vector(15 downto 0);
signal io_to_slave: std_logic_vector(7 downto 0);
signal io_from_slave: std_logic_vector(7 downto 0);
signal s_paddr_valid: std_logic;
signal s_pdata_valid: std_logic;
signal clk_24: std_logic;
signal s_baudout: std_logic;
signal s_uart_addr: std_logic_vector(2 downto 0);
signal s_uart_cs: std_logic;
signal s_addr_hit: std_logic;
signal s_rd_en: std_logic;
signal s_wr_en: std_logic;
signal io_bus_we: std_logic;
signal s_lad_i: std_logic_vector(3 downto 0);
signal s_lad_o: std_logic_vector(3 downto 0);
signal lad_oe: std_logic;
signal io_data_valid: std_logic;
signal rst: std_logic;
signal serirq_i: std_logic;
signal serirq_o: std_logic;
signal serirq_oe: std_logic;
signal irq_vector: std_logic_vector(31 downto 0);
signal uart_int: std_logic;
begin
rst <= not lpc_reset_n;
s_wr_en <= io_bus_we and io_data_valid;
s_rd_en <= not io_bus_we and io_data_valid;
irq_vector <= x"FFFFFF" & "111" & not uart_int & "1111"; -- IRQ4 is IRQ frame 4 on CA945
decoder: lpc_peripheral port map (
clk_i => lpc_clk,
lframe_i => lpc_frame_n,
nrst_i => lpc_reset_n,
lad_oe => lad_oe,
lad_i => s_lad_i,
lad_o => s_lad_o,
dma_chan_o => open,
dma_tc_o => open,
wbm_err_i => '0',
io_bus_dat_o => io_to_slave,
io_bus_dat_i => io_from_slave,
io_bus_addr => io_addr,
io_bus_we => io_bus_we,
io_ack => '1',
io_data_valid => io_data_valid
);
pcode: postcode port map (
lclk => lpc_clk,
data_valid => io_data_valid,
paddr => io_addr,
pdata => io_to_slave,
addr_hit => s_addr_hit,
seven_seg_L => seven_seg_L,
seven_seg_H => seven_seg_H
);
uart: uart_16750 port map (
clk => lpc_clk,
rst => rst,
baudce => '1',
cs => s_uart_cs,
wr => s_wr_en,
rd => s_rd_en,
a => s_uart_addr,
din => io_to_slave,
dout => io_from_slave,
ddis => open,
int => uart_int,
out1n => open,
out2n => open,
rclk => s_baudout,
baudoutn => s_baudout,
rtsn => serial_rts,
dtrn => serial_dtr,
ctsn => serial_cts,
dsrn => serial_dsr,
dcdn => serial_dcd,
rin => serial_ri,
sin => serial_rxd,
sout => serial_txd
);
serirq: serirq_slave port map (
clk_i => lpc_clk,
nrst_i => lpc_reset_n,
irq_i => irq_vector,
serirq_o => serirq_o,
serirq_i => serirq_i,
serirq_oe => serirq_oe
);
tri_lad: process (lad_oe)
begin
if lad_oe = '1' then
lpc_ad <= s_lad_o;
else
lpc_ad <= (others => 'Z');
end if;
end process;
s_lad_i <= lpc_ad;
tri_serirq: process (serirq_oe)
begin
if serirq_oe = '1' then
lpc_serirq <= serirq_o;
else
lpc_serirq <= 'Z';
end if;
end process;
serirq_i <= lpc_serirq;
uart_addr_deco: process (lpc_clk, io_addr)
begin
if rising_edge(lpc_clk) then
case unsigned(io_addr) is
when (uart_base_addr + 0) => s_uart_addr <= "000";
s_uart_cs <= '1';
when (uart_base_addr + 1) => s_uart_addr <= "001";
s_uart_cs <= '1';
when (uart_base_addr + 2) => s_uart_addr <= "010";
s_uart_cs <= '1';
when (uart_base_addr + 3) => s_uart_addr <= "011";
s_uart_cs <= '1';
when (uart_base_addr + 4) => s_uart_addr <= "100";
s_uart_cs <= '1';
when (uart_base_addr + 5) => s_uart_addr <= "101";
s_uart_cs <= '1';
when (uart_base_addr + 6) => s_uart_addr <= "110";
s_uart_cs <= '1';
when (uart_base_addr + 7) => s_uart_addr <= "111";
s_uart_cs <= '1';
when others => s_uart_addr <= "000";
s_uart_cs <= '0';
end case;
end if;
end process;
end architecture;
\ No newline at end of file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
package lpc_uart_pkg is
component lpc_uart is
port (
lpc_clk: in std_logic;
lpc_serirq: inout std_logic;
lpc_ad: inout std_logic_vector(3 downto 0);
lpc_frame_n: in std_logic;
lpc_reset_n: in std_logic;
serial_rxd: in std_logic;
serial_txd: out std_logic;
serial_dtr: out std_logic;
serial_dcd: in std_logic;
serial_dsr: in std_logic;
serial_ri: in std_logic;
serial_cts: in std_logic;
serial_rts: out std_logic;
seven_seg_L: out std_logic_vector(7 downto 0); -- SSeg Data output
seven_seg_H: out std_logic_vector(7 downto 0) -- SSeg Data output
);
end component;
end lpc_uart_pkg;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity postcode is
port (
lclk: in std_logic;
pdata_valid: in std_logic;
paddr_valid: in std_logic;
paddr: in std_logic_vector(15 downto 0);
pdata: in std_logic_vector(7 downto 0);
addr_hit: out std_logic;
data_valid: in std_logic;
seven_seg_L: out std_logic_vector(7 downto 0); -- SSeg Data output
seven_seg_H: out std_logic_vector(7 downto 0) -- SSeg Data output
);
end entity;
architecture postcode_arch of postcode is
signal postcode_data: std_logic_vector(7 downto 0);
constant postcode_addr: std_logic_vector(15 downto 0) := x"0080";
begin
postcode_reg: process(lclk)
begin
if rising_edge(lclk) then
if (paddr = postcode_addr and data_valid = '1') then
addr_hit <= '1';
postcode_data <= pdata;
else
addr_hit <= '0';
end if;
end if;
end process;
P_sseg_decode: process(lclk) -- decode section for 7 seg displays
begin
if rising_edge(lclk) then
case postcode_data(7 downto 4) is -- Most sig digit for display
when "0000" => seven_seg_H <= "00000011"; -- Hex 03 displays a 0
when "0001" => seven_seg_H <= "10011111"; -- Hex 9f displays a 1
when "0010" => seven_seg_H <= "00100101"; -- Hex 25 displays a 2
when "0011" => seven_seg_H <= "00001101"; -- Hex 0d displays a 3
when "0100" => seven_seg_H <= "10011001"; -- Hex 99 displays a 4
when "0101" => seven_seg_H <= "01001001"; -- Hex 49 displays a 5
when "0110" => seven_seg_H <= "01000001"; -- Hex 41 displays a 6
when "0111" => seven_seg_H <= "00011111"; -- Hex 1f displays a 7
when "1000" => seven_seg_H <= "00000001"; -- Hex 01 displays a 8
when "1001" => seven_seg_H <= "00001001"; -- Hex 09 displays a 9
when "1010" => seven_seg_H <= "00010001"; -- Hex 11 displays a A
when "1011" => seven_seg_H <= "11000001"; -- Hex c1 displays a b
when "1100" => seven_seg_H <= "01100011"; -- Hex 63 displays a C
when "1101" => seven_seg_H <= "10000101"; -- Hex 85 displays a d
when "1110" => seven_seg_H <= "01100001"; -- Hex 61 displays a E
when "1111" => seven_seg_H <= "01110001"; -- Hex 71 displays a F
when others => seven_seg_H <= "00000001"; -- Hex 01 displays a 8
end case;
case postcode_data(3 downto 0) is -- Least sig digit for display
when "0000" => seven_seg_L <= "00000011"; -- Hex 03 displays a 0
when "0001" => seven_seg_L <= "10011111"; -- Hex 9f displays a 1
when "0010" => seven_seg_L <= "00100101"; -- Hex 25 displays a 2
when "0011" => seven_seg_L <= "00001101"; -- Hex 0d displays a 3
when "0100" => seven_seg_L <= "10011001"; -- Hex 99 displays a 4
when "0101" => seven_seg_L <= "01001001"; -- Hex 49 displays a 5
when "0110" => seven_seg_L <= "01000001"; -- Hex 41 displays a 6
when "0111" => seven_seg_L <= "00011111"; -- Hex 1f displays a 7
when "1000" => seven_seg_L <= "00000001"; -- Hex 01 displays a 8
when "1001" => seven_seg_L <= "00001001"; -- Hex 09 displays a 9
when "1010" => seven_seg_L <= "00010001"; -- Hex 11 displays a A
when "1011" => seven_seg_L <= "11000001"; -- Hex c1 displays a b
when "1100" => seven_seg_L <= "01100011"; -- Hex 63 displays a C
when "1101" => seven_seg_L <= "10000101"; -- Hex 85 displays a d
when "1110" => seven_seg_L <= "01100001"; -- Hex 61 displays a E
when "1111" => seven_seg_L <= "01110001"; -- Hex 71 displays a F
when others => seven_seg_L <= "00000001"; -- Hex 01 displays a 8
end case;
end if;
end process;
end architecture;
\ No newline at end of file
//////////////////////////////////////////////////////////////////////
//// ////
//// $Id: serirq_defines.v,v 1.2 2008-12-27 19:46:18 hharte Exp $
//// wb_lpc_defines.v ////
//// ////
//// This file is part of the Wishbone LPC Bridge project ////
//// http://www.opencores.org/projects/wb_lpc/ ////
//// ////
//// Author: ////
//// - Howard M. Harte (hharte@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Howard M. Harte ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Wishbone SERIRQ Host/Slave Interface Definitions
`define SERIRQ_ST_IDLE 13'h000 // SERIRQ Idle state
`define SERIRQ_ST_START 13'h001 // SERIRQ Start state
`define SERIRQ_ST_START_R 13'h002 // SERIRQ Start state
`define SERIRQ_ST_START_T 13'h004 // SERIRQ Start state
`define SERIRQ_ST_IRQ 13'h008 // SERIRQ IRQ Frame State
`define SERIRQ_ST_IRQ_R 13'h010 // SERIRQ IRQ Frame State
`define SERIRQ_ST_IRQ_T 13'h020 // SERIRQ IRQ Frame State
`define SERIRQ_ST_STOP 13'h040 // SERIRQ Stop State
`define SERIRQ_ST_STOP_R 13'h080 // SERIRQ Stop State
`define SERIRQ_ST_STOP_T 13'h100 // SERIRQ Stop State
`define SERIRQ_ST_WAIT_STOP 13'h200
`define SERIRQ_MODE_CONTINUOUS 1'b1 // Serirq "Continuous Mode"
`define SERIRQ_MODE_QUIET 1'b0 // Serirq "Quiet Mode"
\ No newline at end of file
//////////////////////////////////////////////////////////////////////
//// ////
//// $Id: serirq_slave.v,v 1.2 2008-12-27 19:46:18 hharte Exp $ ////
//// serirq_slave.v - Wishbone Slave to SERIRQ Host Bridge ////
//// ////
//// This file is part of the Wishbone LPC Bridge project ////
//// http://www.opencores.org/projects/lpc/ ////
//// ////
//// Author: ////
//// - Howard M. Harte (hharte@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Howard M. Harte ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ns
`include "serirq_defines.v"
module serirq_slave(clk_i, nrst_i,
irq_i,
serirq_o, serirq_i, serirq_oe
);
// Wishbone Slave Interface
input clk_i;
input nrst_i; // Active low reset.
// SERIRQ Master Interface
output reg serirq_o; // SERIRQ output
input serirq_i; // SERIRQ Input
output reg serirq_oe; // SERIRQ Output Enable
input [31:0] irq_i; // IRQ Input Bus
reg [31:0] current_irq;
reg [12:0] state; // Current state
reg [4:0] irq_cnt; // IRQ Frame counter
reg found_stop;
reg found_start;
reg serirq_mode;
wire irq_changed = (serirq_mode & (current_irq != irq_i));
always @(posedge clk_i or negedge nrst_i)
if(~nrst_i)
begin
state <= `SERIRQ_ST_IDLE;
serirq_oe <= 1'b0;
serirq_o <= 4'b1;
irq_cnt <= 5'h00;
current_irq <= irq_i;
end
else begin
case(state)
`SERIRQ_ST_IDLE:
begin
serirq_oe <= 1'b0;
irq_cnt <= 5'h00;
serirq_o <= 1'b1;
if(found_start == 1'b1) // Wait for Start cycle
begin
current_irq <= irq_i;
if(irq_i[irq_cnt] == 1'b0) begin
serirq_oe <= 1'b1;
serirq_o <= 1'b0;
end
state <= `SERIRQ_ST_IRQ_R;
end
else if(irq_changed) begin
current_irq <= irq_i;
serirq_o <= 1'b0;
serirq_oe <= 1'b1;
state <= `SERIRQ_ST_IDLE;
end else
state <= `SERIRQ_ST_IDLE;
end
`SERIRQ_ST_IRQ:
begin
if(irq_i[irq_cnt] == 1'b0) begin
serirq_oe <= 1'b1;
serirq_o <= 1'b0;
end
if(found_stop == 1'b0)
state <= `SERIRQ_ST_IRQ_R;
else
state <= `SERIRQ_ST_IDLE;
end
`SERIRQ_ST_IRQ_R:
begin
serirq_o <= 1'b1;
if(found_stop == 1'b0)
state <= `SERIRQ_ST_IRQ_T;
else
state <= `SERIRQ_ST_IDLE;
end
`SERIRQ_ST_IRQ_T:
begin
serirq_oe <= 1'b0;
if(irq_cnt == 5'h1f)
begin
state <= `SERIRQ_ST_WAIT_STOP;
end
else begin
irq_cnt <= irq_cnt + 1;
if(found_stop == 1'b0)
state <= `SERIRQ_ST_IRQ;
else
state <= `SERIRQ_ST_IDLE;
end
end
`SERIRQ_ST_WAIT_STOP:
begin
if(found_stop == 1'b0)
state <= `SERIRQ_ST_WAIT_STOP;
else
state <= `SERIRQ_ST_IDLE;
end
endcase
end
reg [3:0] stop_clk_cnt;
// Look for STOP cycles
always @(posedge clk_i or negedge nrst_i)
if(~nrst_i)
begin
found_stop <= 1'b0;
found_start <= 1'b0;
serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
stop_clk_cnt <= 4'h0;
end
else begin
if(serirq_i == 1'b0) begin
stop_clk_cnt <= stop_clk_cnt + 1;
end
else begin
case (stop_clk_cnt)
4'h2:
begin
found_stop <= 1'b1;
found_start <= 1'b0;
serirq_mode <= `SERIRQ_MODE_QUIET;
end
4'h3:
begin
found_stop <= 1'b1;
found_start <= 1'b0;
serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
end
4'h4:
begin
found_stop <= 1'b0;
found_start <= 1'b1;
end
4'h6:
begin
found_stop <= 1'b0;
found_start <= 1'b1;
end
4'h8:
begin
found_stop <= 1'b0;
found_start <= 1'b1;
end
default:
begin
found_stop <= 1'b0;
found_start <= 1'b0;
end
endcase
stop_clk_cnt <= 4'h0;
end
end
endmodule
\ No newline at end of file
library ieee;
use ieee.std_logic_1164.all;
use work.Wishbone_pkg.all;
use work.wr_fabric_pkg.all;
entity mini_bone is
generic(
g_class_mask : std_logic_vector(7 downto 0) := x"ff";
g_our_ethertype : std_logic_vector(15 downto 0) := x"a0a0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_sel_i : in std_logic_vector(1 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_dat_i : in std_logic_vector(15 downto 0);
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_ack_o : out std_logic;
snk_err_o : out std_logic;
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
src_we_o : out std_logic;
src_ack_i : in std_logic;
src_err_i : in std_logic;
src_sel_o : out std_logic_vector(1 downto 0);
src_stall_i : in std_logic;
master_cyc_o : out std_logic;
master_we_o : out std_logic;
master_stb_o : out std_logic;
master_sel_o : out std_logic_vector(3 downto 0);
master_adr_o : out std_logic_vector(31 downto 0);
master_dat_o : out std_logic_vector(31 downto 0);
master_dat_i : in std_logic_vector(31 downto 0);
master_ack_i : in std_logic
);
end mini_bone;
architecture wrapper of mini_bone is
component xmini_bone
generic (
g_class_mask : std_logic_vector(7 downto 0);
g_our_ethertype : std_logic_vector(15 downto 0));
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink_in;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
signal src_out : t_wrf_source_out;
signal src_in : t_wrf_source_in;
signal snk_out : t_wrf_sink_out;
signal snk_in : t_wrf_sink_in;
signal master_out : t_wishbone_master_out;
signal master_in : t_wishbone_master_in;
begin -- wrapper
U_Wrapped_MB : xmini_bone
generic map (
g_class_mask => g_class_mask,
g_our_ethertype => g_our_ethertype)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
src_o => src_out,
src_i => src_in,
snk_o => snk_out,
snk_i => snk_in,
master_o => master_out,
master_i => master_in);
src_cyc_o <= src_out.cyc;
src_stb_o <= src_out.stb;
src_we_o <= src_out.we;
src_adr_o <= src_out.adr;
src_dat_o <= src_out.dat;
src_sel_o <= src_out.sel;
src_in.ack <= src_ack_i;
src_in.stall <= src_stall_i;
snk_in.cyc <= snk_cyc_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_in.sel <= snk_sel_i;
snk_in.adr <= snk_adr_i;
snk_in.dat <= snk_dat_i;
snk_ack_o <= snk_out.ack;
snk_stall_o <= snk_out.stall;
master_cyc_o <= master_out.cyc;
master_stb_o <= master_out.stb;
master_we_o <= master_out.we;
master_sel_o <= master_out.sel;
master_adr_o <= master_out.adr;
master_dat_o <= master_out.dat;
master_in.dat <= master_dat_i;
master_in.ack <= master_ack_i;
end wrapper;
files = ["dmtd_phase_meas.vhd",
"dmtd_with_deglitcher.vhd",
"multi_dmtd_with_deglitcher.vhd",
"hpll_period_detect.vhd",
"pulse_gen.vhd",
"pulse_stamper.vhd" ]
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.gencores_pkg.all;
entity multi_dmtd_with_deglitcher is
generic (
g_counter_bits : natural := 17;
g_log2_replication : natural := 2
);
port (
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
-- DMTD sampling clock
clk_dmtd_i : in std_logic;
-- system clock
clk_sys_i : in std_logic;
-- input clock
clk_in_i : in std_logic;
-- edge tag (clk_sys_i domain)
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p_o : out std_logic;
-- phase shifter enable, HI level shifts the tag forward/backward by
-- 1 clk_dmtd_i with respect to the expected tag value.
shift_en_i : in std_logic;
-- phase shift direction: 1 - forward, 0 - backward
shift_dir_i : in std_logic;
-- deglitcher parameters (clk_dmtd_i domain)
deglitch_threshold_i: in std_logic_vector(15 downto 0);
dbg_dmtdout_o : out std_logic
);
end multi_dmtd_with_deglitcher;
architecture rtl of multi_dmtd_with_deglitcher is
constant c_num_dmtds : natural := 2**g_log2_replication;
function f_count_zeroes (x : std_logic_vector) return unsigned is
variable i : integer;
variable cnt : unsigned(g_log2_replication downto 0);
begin
cnt := (others => '0');
for i in 0 to x'left loop
if(x(i) = '0') then
cnt := cnt + 1;
end if;
end loop; -- i
return cnt;
end function f_count_zeroes;
type t_state is (WAIT_STABLE_0, WAIT_EDGE, GOT_EDGE, ROUND_TAG);
signal state : t_state;
signal stab_cntr : unsigned(deglitch_threshold_i'left downto 0);
signal free_cntr : unsigned(g_counter_bits-1 downto 0);
signal new_edge_sreg : std_logic_vector(3 downto 0);
signal new_edge_p : std_logic;
signal tag_int : unsigned(g_counter_bits + g_log2_replication -1 downto 0);
signal clk_i_d0, clk_i_d1, clk_i_d2 : std_logic_vector(c_num_dmtds-1 downto 0);
signal dmtd_in : std_logic_vector(c_num_dmtds-1 downto 0);
signal n_zeroes : unsigned(g_log2_replication downto 0);
signal in_is_0, in_is_1 : std_logic;
signal ones : std_logic_vector(31 downto 0) := x"ffffffff";
signal zeroes : std_logic_vector(31 downto 0) := x"00000000";
begin -- rtl
gen_dmtds : for i in 0 to c_num_dmtds-1 generate
the_dmtd_itself : process(clk_dmtd_i)
begin
if rising_edge(clk_dmtd_i) then
clk_i_d0(i) <= clk_in_i;
clk_i_d1(i) <= clk_i_d0(i);
clk_i_d2(i) <= clk_i_d1(i);
dmtd_in(i) <= clk_i_d2(i);
end if;
end process;
end generate gen_dmtds;
dmtd_postprocess : process(clk_dmtd_i)
begin
if rising_edge(clk_dmtd_i) then
if(dmtd_in = ones(dmtd_in'left downto 0)) then
in_is_1 <= '1';
else
in_is_1 <= '0';
end if;
if(dmtd_in = zeroes(dmtd_in'left downto 0)) then
in_is_0 <= '1';
else
in_is_0 <= '0';
end if;
n_zeroes <= f_count_zeroes(dmtd_in);
dbg_dmtdout_o <= n_zeroes(0);
end if;
end process;
deglitch : process (clk_dmtd_i) -- glitchproof DMTD output edge
-- detection
begin -- process deglitch
if rising_edge(clk_dmtd_i) then -- rising clock edge
if rst_n_dmtdclk_i = '0' then -- asynchronous reset (active low)
stab_cntr <= (others => '0');
free_cntr <= (others => '0');
state <= WAIT_STABLE_0;
new_edge_sreg <= (others => '0');
else
if(shift_en_i = '0') then
free_cntr <= free_cntr + 1;
elsif(shift_dir_i = '1') then
free_cntr <= free_cntr + 2;
end if;
case state is
when WAIT_STABLE_0 => -- out-of-sync
new_edge_sreg <= '0' & new_edge_sreg(new_edge_sreg'left downto 1);
if (in_is_0 = '0') then
stab_cntr <= (others => '0');
else
stab_cntr <= stab_cntr + 1;
end if;
-- DMTD output stable counter hit the LOW level threshold?
if stab_cntr = unsigned(deglitch_threshold_i) then
state <= WAIT_EDGE;
end if;
when WAIT_EDGE =>
if (in_is_0 = '0') then -- got a glitch?
state <= GOT_EDGE;
tag_int <= free_cntr & to_unsigned(0, g_log2_replication);
end if;
when GOT_EDGE =>
tag_int <= tag_int + n_zeroes;
if (in_is_1 = '0') then
stab_cntr <= (others => '0');
else
stab_cntr <= stab_cntr + 1;
end if;
if stab_cntr = unsigned(deglitch_threshold_i) then
state <= ROUND_TAG;
end if;
when ROUND_TAG =>
if(tag_int(g_log2_replication-1) = '1') then
tag_int <= tag_int + to_unsigned(2**g_log2_replication, g_log2_replication+1);
end if;
new_edge_sreg <= (others => '1');
state <= WAIT_STABLE_0;
end case;
end if;
end if;
end process deglitch;
--n_zeroes <= f_count_zeroes(dmtd_in);
sync_reset_refclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_sysclk_i,
data_i => new_edge_sreg(0),
synced_o => open,
npulse_o => open,
ppulse_o => new_edge_p);
tag_stb_p_o <= new_edge_p;
tag_o <= std_logic_vector(tag_int(tag_int'left downto g_log2_replication));
end rtl;
files = [
"slib_clock_div.vhd",
"slib_counter.vhd",
"slib_edge_detect.vhd",
"slib_fifo_cyclone2.vhd",
"slib_fifo.vhd",
"slib_input_filter.vhd",
"slib_input_sync.vhd",
"slib_mv_filter.vhd",
"uart_16750.vhd",
"uart_baudgen.vhd",
"uart_interrupt.vhd",
"uart_receiver.vhd",
"uart_transmitter.vhd"
]
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