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Production Test Suite
Commit 3291ecb5 authored by Matthieu Cattin's avatar Matthieu Cattin
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Modify wishbone modules base addresses for SDB enabled firmware.

parent a5f2c2ca
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test/fmcadc100m14b4cha/python/fmc_adc.py
View file @ 3291ecb5
...@@ -75,19 +75,19 @@ class FmcAdc100mOperationError(Exception): ...@@ -75,19 +75,19 @@ class FmcAdc100mOperationError(Exception):
class CFmcAdc100m: class CFmcAdc100m:
FMC_SYS_I2C_ADDR = 0x60000 FMC_SYS_I2C_ADDR = 0x1600
EEPROM_ADDR = 0x50 EEPROM_ADDR = 0x50
FMC_SPI_ADDR = 0x70000 FMC_SPI_ADDR = 0x1700
FMC_SPI_DIV = 100 FMC_SPI_DIV = 100
FMC_SPI_SS = {'ADC': 0,'DAC1': 1,'DAC2': 2,'DAC3': 3,'DAC4': 4} FMC_SPI_SS = {'ADC': 0,'DAC1': 1,'DAC2': 2,'DAC3': 3,'DAC4': 4}
FMC_I2C_ADDR = 0x80000 FMC_I2C_ADDR = 0x1800
SI570_ADDR = 0x55 SI570_ADDR = 0x55
FMC_ONEWIRE_ADDR = 0xA0000 FMC_ONEWIRE_ADDR = 0x1A00
FMC_CSR_ADDR = 0x90000 FMC_CSR_ADDR = 0x1900
""" """
......
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
View file @ 3291ecb5
...@@ -36,11 +36,11 @@ class FmcAdc100mSpecOperationError(Exception): ...@@ -36,11 +36,11 @@ class FmcAdc100mSpecOperationError(Exception):
class CFmcAdc100mSpec: class CFmcAdc100mSpec:
# Wishbone core base addresses # Wishbone core base addresses
GNUM_DMA_CSR_ADDR = 0x00000 GNUM_DMA_CSR_ADDR = 0x1000
ONEWIRE_ADDR = 0x20000 ONEWIRE_ADDR = 0x1200
CSR_ADDR = 0x30000 CSR_ADDR = 0x1300
UTC_CORE_ADDR = 0x40000 UTC_CORE_ADDR = 0x1400
IRQ_CONTROLLER_ADDR = 0x50000 IRQ_CONTROLLER_ADDR = 0x1500
# Onewire core port # Onewire core port
DS18B20_PORT = 0 DS18B20_PORT = 0
......
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