Commit 29048954 authored by Evangelia Gousiou's avatar Evangelia Gousiou

- added white rabbit calibration

- cleanup of unused folders
parent 64a946ba

Too many changes to show.

To preserve performance only 1000 of 1000+ files are displayed.

......@@ -7,9 +7,10 @@ import time
class CCSR:
def __init__(self, bus, base_addr):
def __init__(self, bus, base_addr, reg_map=None):
self.base_addr = base_addr;
self.bus = bus;
self.reg_map = reg_map
def wr_reg(self, addr, val):
#print(" wr:%.8X reg:%.8X")%(val,(self.base_addr+addr))
......@@ -34,3 +35,74 @@ class CCSR:
return 1
else:
return 0
#--------------------------------------------
# Get register's field value
def get_field(self, reg, field):
if(reg in self.reg_map[1]): # test if register exist in register map
if(field in self.reg_map[1][reg][2]): # test if field exist in register
reg_addr = self.reg_map[1][reg][0]
field_mask = self.reg_map[1][reg][2][field][2]
field_offset = self.reg_map[1][reg][2][field][0]
reg_val = self.rd_reg(reg_addr)
reg_val = (field_mask & (reg_val >> field_offset))
return reg_val
else:
raise CSRDeviceOperationError(self.base_addr, self.reg_map, 'Requested field (%s) doesn\'t exist.'%field)
else:
raise CSRDeviceOperationError(self.base_addr, self.reg_map, 'Requested register (%s) doesn\'t exist.'%reg)
# Set register's field value
def set_field(self, reg, field, value):
if(reg in self.reg_map[1]): # test if register exist in register map
if(field in self.reg_map[1][reg][2]): # test if field exist in register
reg_addr = self.reg_map[1][reg][0]
field_mask = self.reg_map[1][reg][2][field][2]
field_offset = self.reg_map[1][reg][2][field][0]
reg_val = self.rd_reg(reg_addr)
reg_val &= ~(field_mask << field_offset)
reg_val |= ((field_mask & value) << field_offset)
self.wr_reg(reg_addr, reg_val)
return reg_val
else:
raise CSRDeviceOperationError(self.base_addr, self.reg_map, 'Requested field (%s) doesn\'t exist.'%field)
else:
raise CSRDeviceOperationError(self.base_addr, self.reg_map, 'Requested register (%s) doesn\'t exist.'%reg)
# Set register value
def set_reg(self, reg, value):
if(reg in self.reg_map[1]): # test if register exist in register map
self.wr_reg(self.reg_map[1][reg][0], value)
else:
raise CSRDeviceOperationError(self.base_addr, self.reg_map, 'Requested register (%s) doesn\'t exist.'%reg)
# Get register value
def get_reg(self, reg):
if(reg in self.reg_map[1]): # test if register exist in register map
return self.rd_reg(self.reg_map[1][reg][0])
else:
raise CSRDeviceOperationError(self.base_addr, self.reg_map, 'Requested register (%s) doesn\'t exist.'%reg)
# Print all register map
def print_reg_map(self):
print "\n%s:" % (self.reg_map[0])
print "--------------------------------------------------"
# loop over registers and sort them by address offset
for reg in sorted(self.reg_map[1].iteritems(), key=lambda (k,v): v[0]):
value = self.get_reg(reg[0])
print " * %-50s:0x%08X (%d)" % (reg[1][1],value, value)
# loop over fields and sort them by position
for field in sorted(reg[1][2].iteritems(), key=lambda (k,v): v[0]):
value = self.get_field(reg[0], field[0])
print " - %-48s:0x%X (%d)" % (field[1][1],value, value)
if(len(reg[1][2]) != 0):
print ''
......@@ -5,8 +5,19 @@ import rr
import time
import i2c
class Eeprom24AA64OperationError(Exception):
def __init__(self, addr, msg):
self.msg = msg
self.addr = addr
def __str__(self):
return ("EEPROM 24AA64 [I2C address:0x%02X]: %s" %(self.addr, self.msg))
class C24AA64:
PAGE_SIZE = 32 # in bytes
PAGE_BOUNDARY_MASK = 0xFFFF - (PAGE_SIZE - 1)
def __init__(self, i2c, i2c_addr):
self.i2c = i2c
self.i2c_addr = i2c_addr
......@@ -43,3 +54,67 @@ class C24AA64:
#print('24AA64:read:last i=%d')%(i)
data.append(self.i2c.read(True))
return data;
def wr_byte(self, mem_addr, byte):
try:
self.i2c.start(self.i2c_addr, True)
self.i2c.write((mem_addr >> 8), False)
self.i2c.write((mem_addr & 0xFF), False)
self.i2c.write(byte,True)
except I2CDeviceOperationError as e:
raise Eeprom24AA64OperationError(self.i2c_addr, e)
def rd_byte(self, mem_addr):
try:
self.i2c.start(self.i2c_addr, True)
self.i2c.write((mem_addr >> 8), False)
self.i2c.write((mem_addr & 0xFF), False)
self.i2c.start(self.i2c_addr, False)
return self.i2c.read(True)
except I2CDeviceOperationError as e:
raise Eeprom24AA64OperationError(self.i2c_addr, e)
def wr_page(self, mem_addr, data):
try:
#print '[24AA64] write data lenght=%d' % (len(data))
#print '[24AA64] write addr=%04X' % (mem_addr)
if(len(data) == 0):
raise Eeprom24AA64OperationError(self.i2c_addr, "Nothing to transmit, data size is 0!")
if(len(data) > self.PAGE_SIZE):
raise Eeprom24AA64OperationError(self.i2c_addr, "Maximum write size is %d byte!" % self.PAGE_SIZE)
if((mem_addr | self.PAGE_BOUNDARY_MASK) ^ self.PAGE_BOUNDARY_MASK):
raise Eeprom24AA64OperationError(self.i2c_addr, "Start write address is not aligned to a page boundary!")
self.i2c.start(self.i2c_addr, True)
self.i2c.write((mem_addr >> 8), False)
self.i2c.write((mem_addr & 0xFF), False)
#print '[24AA64] write data lenght=%d' % (len(data))
i = 0
for i in range(len(data)-1):
#print '[24AA64] write i=%d' % (i)
self.i2c.write(data[i],False)
if len(data) > 1:
i += 1
#print '[24AA64] write last i=%d' % (i)
self.i2c.write(data[i],True)
except I2CDeviceOperationError as e:
raise Eeprom24AA64OperationError(self.i2c_addr, e)
def rd_seq(self, mem_addr, size):
try:
self.i2c.start(self.i2c_addr, True)
self.i2c.write((mem_addr >> 8), False)
self.i2c.write((mem_addr & 0xFF), False)
self.i2c.start(self.i2c_addr, False)
data = []
#print '[24AA64] read data lenght=%d' % (size)
i=0
for i in range(size-1):
data.append(self.i2c.read(False))
#print '[24AA64] read i=%d' % (i)
if len(data) > 1:
i += 1
#print '[24AA64] read last i=%d' % (i)
data.append(self.i2c.read(True))
return data
except I2CDeviceOperationError as e:
raise Eeprom24AA64OperationError(self.i2c_addr, e)
......@@ -92,6 +92,10 @@ class CGN4124:
def get_physical_addr(self):
return self.pages
# Enable interrupt handling in the driver
def irq_en(self):
self.bus.irqena()
# Wait for interrupt
def wait_irq(self):
# Add here reading of the interrupt source (once the irq core will be present)
......
......@@ -5,7 +5,7 @@ import rr
import time
import csr
class CGN4124:
class CGN4124_nodma:
# Host registers (BAR12), for DMA items storage
HOST_BAR = 0xC
......@@ -56,6 +56,7 @@ class CGN4124:
def wr_reg(self, bar, addr, value):
self.bus.iwrite(bar, addr, 4, value)
"""
def __init__(self, bus, csr_addr):
self.bus = bus
self.dma_csr = csr.CCSR(bus, csr_addr)
......@@ -67,6 +68,21 @@ class CGN4124:
self.set_interrupt_config()
# Enable interrupt from gn4124
self.bus.irqena()
"""