Add wbgen file for fmc ref clock for gtp project.

1c490ed1 · Matthieu Cattin · 633f6b00 · 1c490ed1 · 1c490ed1 · 1c490ed1
Commit 1c490ed1 authored Nov 12, 2012 by Matthieu Cattin
4 changed files
--- a/test/svec/VHDL/svec_pts_gtp_clkfmc/wb_gen/Makefile
+++ b/test/svec/VHDL/svec_pts_gtp_clkfmc/wb_gen/Makefile
+WBGEN2=~/projects/wbgen2/wbgen2
+RTL=../rtl/
+
+csr_regs:
+	 $(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm -C $@.h $@.wb
\ No newline at end of file
--- a/test/svec/VHDL/svec_pts_gtp_clkfmc/wb_gen/csr_regs.h
+++ b/test/svec/VHDL/svec_pts_gtp_clkfmc/wb_gen/csr_regs.h
+/*
+  Register definitions for slave core: SVEC pts FMC GTP refclk CSR registers
+
+  * File           : csr_regs.h
+  * Author         : auto-generated by wbgen2 from csr_regs.wb
+  * Created        : Tue Nov  6 14:21:56 2012
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE csr_regs.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_CSR_REGS_WB
+#define __WBGEN2_REGDEFS_CSR_REGS_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Control register */
+
+/* definitions for field: Reserved in reg: Control register */
+#define CSR_CTL_RESERVED_MASK                 WBGEN2_GEN_MASK(0, 32)
+#define CSR_CTL_RESERVED_SHIFT                0
+#define CSR_CTL_RESERVED_W(value)             WBGEN2_GEN_WRITE(value, 0, 32)
+#define CSR_CTL_RESERVED_R(reg)               WBGEN2_GEN_READ(reg, 0, 32)
+
+/* definitions for register: Status register */
+
+/* definitions for field: Reserved in reg: Status register */
+#define CSR_STA_RESERVED_MASK                 WBGEN2_GEN_MASK(0, 32)
+#define CSR_STA_RESERVED_SHIFT                0
+#define CSR_STA_RESERVED_W(value)             WBGEN2_GEN_WRITE(value, 0, 32)
+#define CSR_STA_RESERVED_R(reg)               WBGEN2_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FMC1 clk counter register */
+
+/* definitions for field: Reserved in reg: FMC1 clk counter register */
+#define CSR_FMC1_CLK_CNT_RESERVED_MASK        WBGEN2_GEN_MASK(0, 32)
+#define CSR_FMC1_CLK_CNT_RESERVED_SHIFT       0
+#define CSR_FMC1_CLK_CNT_RESERVED_W(value)    WBGEN2_GEN_WRITE(value, 0, 32)
+#define CSR_FMC1_CLK_CNT_RESERVED_R(reg)      WBGEN2_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FMC2 clk counter register */
+
+/* definitions for field: Reserved in reg: FMC2 clk counter register */
+#define CSR_FMC2_CLK_CNT_RESERVED_MASK        WBGEN2_GEN_MASK(0, 32)
+#define CSR_FMC2_CLK_CNT_RESERVED_SHIFT       0
+#define CSR_FMC2_CLK_CNT_RESERVED_W(value)    WBGEN2_GEN_WRITE(value, 0, 32)
+#define CSR_FMC2_CLK_CNT_RESERVED_R(reg)      WBGEN2_GEN_READ(reg, 0, 32)
+
+PACKED struct CSR_WB {
+  /* [0x0]: REG Control register */
+  uint32_t CTL;
+  /* [0x4]: REG Status register */
+  uint32_t STA;
+  /* [0x8]: REG FMC1 clk counter register */
+  uint32_t FMC1_CLK_CNT;
+  /* [0xc]: REG FMC2 clk counter register */
+  uint32_t FMC2_CLK_CNT;
+};
+
+#endif
--- a/test/svec/VHDL/svec_pts_gtp_clkfmc/wb_gen/csr_regs.htm
+++ b/test/svec/VHDL/svec_pts_gtp_clkfmc/wb_gen/csr_regs.htm
--- a/test/svec/VHDL/svec_pts_gtp_clkfmc/wb_gen/csr_regs.wb
+++ b/test/svec/VHDL/svec_pts_gtp_clkfmc/wb_gen/csr_regs.wb
+peripheral {
+  name = "SVEC pts FMC GTP refclk CSR registers";
+  description = "Wishbone slave for FMC GTP refclk test";
+  hdl_entity = "csr_regs";
+
+  prefix = "csr";
+
+  reg {
+    name = "Control register";
+    prefix = "ctl";
+
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
+  reg {
+    name = "Status register";
+    prefix = "sta";
+
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 32;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+  };
+
+reg {
+    name = "FMC1 clk counter register";
+    prefix = "fmc1_clk_cnt";
+
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 32;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+  };
+
+  reg {
+    name = "FMC2 clk counter register";
+    prefix = "fmc2_clk_cnt";
+
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 32;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+  };
+
+};