#!   /usr/bin/env	python
#    coding: utf8

# Copyright CERN, 2011
# Author: Ross Millar <ross.millar@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org

## TEST FOR VCXO
import sys
import os
import os.path
import rr
import random
import time
import spi
import csr
import i2c
import gn4124
import fmc_adc_test_suite
from pylab import *
from ptsexcept import *

"""
Same as Test Suite test02 - however for FMCs with 6ch ADCs
Counts set number of clock ticks on the mez clock, in terms of the system clock.
Writes a new value to the DAC, which alters the mezzanine clock speed
Counts the same number of clock ticks on the mezzanine clock again
Compares the 2 resuls to see if the mez clock has changed appropriately
"""

def main(default_directory='.') :
       
    # Objects declaration
    spec = rr.Gennum() 
    fmc = fmc_adc_test_suite.CFmcAdc100ks(spec)
      
    # Reset DAC register  	- Set VCXO to lowest frequency
    fmc.spi_dac_write(0x0000)      
    
    # Number of sys clock ticks for counter on mezzanine clock to complete count
    result = fmc.clock_comparison()     
    time.sleep(.1)
   
    
    fmc.spi_dac_write(0xFFFF)
    time.sleep(.1)
     
    # Number of sys clock ticks for counter on mezzanine clock to complete count
    result_1 = fmc.clock_comparison()
    
    
    print "VCXO at lowest frequency - Number of system clock ticks for mezzanine clock count : %d" %result
    print "VCXO at highest frequency - Number of system clock ticks for mezzanine clock count : %d" %result_1
   
    
    if (result - result_1) >10:
    	print "DAC and VCXO fully working"
    else:
    	print "Potential problem with the DAC"
    	print "Potential problem with the VCXO"	
    	raise PtsError("VCXO or DAC operation failed")
    	
    	
    	  	
if __name__ == '__main__':
	main()    
    
