#!   /usr/bin/env   python
#    coding: utf8

# Copyright CERN, 2012
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 8/5/2012


# GN4124 DMA enhanced interrupt controller registers
DMA_EIC_REGS=['DMA EIC registers', {
        'IDR':[0x00, 'Interrupt disable', {
                'DMA_END':[0, 'End of DMA transfer', 0x1],
                'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
                'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}],
        'IER':[0x04, 'Interrupt enable', {
                'DMA_END':[0, 'End of DMA transfer', 0x1],
                'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
                'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}],
        'IMR':[0x08, 'Interrupt enable mask', {
                'DMA_END':[0, 'End of DMA transfer', 0x1],
                'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
                'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}],
        'ISR':[0x0C, 'Interrupt status', {
                'DMA_END':[0, 'End of DMA transfer', 0x1],
                'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
                'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}]
        }]
