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Production Test Suite - base
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Production Test Suite - base
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f37c936c
Commit
f37c936c
authored
Nov 05, 2014
by
Matthieu Cattin
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common:si57x: Fix register field mask issue.
parent
ac496499
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si57x.py
common/si57x.py
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common/si57x.py
View file @
f37c936c
...
@@ -111,7 +111,7 @@ class CSi57x:
...
@@ -111,7 +111,7 @@ class CSi57x:
reg
=
self
.
rd_reg
(
self
.
R_HS
)
reg
=
self
.
rd_reg
(
self
.
R_HS
)
self
.
wr_reg
(
self
.
R_HS
,
((
div
>>
2
)
|
(
reg
&
self
.
HS_DIV_MASK
)))
self
.
wr_reg
(
self
.
R_HS
,
((
div
>>
2
)
|
(
reg
&
self
.
HS_DIV_MASK
)))
reg
=
self
.
rd_reg
(
self
.
R_RFREQ4
)
reg
=
self
.
rd_reg
(
self
.
R_RFREQ4
)
self
.
wr_reg
(
self
.
R_RFREQ4
,
(((
div
&
self
.
N1_L_MASK
)
<<
6
)
|
(
reg
&
self
.
RFREQ4_MASK
)))
self
.
wr_reg
(
self
.
R_RFREQ4
,
(((
div
<<
6
)
&
self
.
N1_L_MASK
)
|
(
reg
&
self
.
RFREQ4_MASK
)))
def
freeze_m
(
self
):
def
freeze_m
(
self
):
reg
=
self
.
rd_reg
(
self
.
R_RFMC
)
|
self
.
RFMC_FREEZE_M
reg
=
self
.
rd_reg
(
self
.
R_RFMC
)
|
self
.
RFMC_FREEZE_M
...
...
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