Commit 81bfcae9 authored by Matthieu Cattin's avatar Matthieu Cattin

Add license and exception handler in csr module.

parent bd4f2624
#!/usr/bin/python
# Copyright CERN, 2011
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 27/4/2012
# Import standard modules
import sys
import rr
import time
# Import specific modules
import rr
# Class to access 32-bit wishbone registers on BAR0
class CSRDeviceOperationError(Exception):
def __init__(self, msg):
self.msg = msg
def __str__(self):
return ("CSR Device produced the error: %s" %(msg))
class CCSR:
......@@ -11,15 +27,18 @@ class CCSR:
self.base_addr = base_addr;
self.bus = bus;
def wr_reg(self, addr, val):
#print(" wr:%.8X reg:%.8X")%(val,(self.base_addr+addr))
#print '[CSR] wr:%.8X reg:%.8X' % (val,(self.base_addr+addr))
self.bus.iwrite(0, self.base_addr + addr, 4, val)
def rd_reg(self, addr):
reg = self.bus.iread(0, self.base_addr + addr, 4)
#print(" reg:%.8X value:%.8X")%((self.base_addr+addr), reg)
#print '[CSR] reg:%.8X value:%.8X' % ((self.base_addr+addr), reg)
return reg
def wr_bit(self, addr, bit, value):
reg = self.rd_reg(addr)
if(0==value):
......
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