Introduction of an other way to calculate the best foreign master. It
has been changed to fix bugs found during ISPC20119 (IOL test). Tests
showed unstable behavior in the computation of foreign master
qualification in some specific circumstances (time window of 8s with
announce messages every 5s)

Issue detected by IOL test in ICALEPS2019
The selection of the ErBest was not taking account all the time of the
qualification.

- New mechanism for clock degradation (degrade clock class, clock
accuracy, clock variance, timeSource, ptpTimeScale, frequencyTraceable,
timeTraceable)
- timeSource can be configured now
- If clock accuracy, clock variance and timeSource are not set in
ppsi.conf, default values are used depending of the clock class.

Change clock accuracy from 0x21(100ns) to 0x20(25ns) for ARB Grand Master.

This field is used to store the active peer connected to an instance. In
wr_mon tool, it replaces the field peer on the display which was not
very explicit when many peers are connected on the same port. The field
activePeer takes the value of peer field in the following cases :

           MASTER          UNCALIBRATED/SLAVE
P2P     Rx PDELAY_RESP    Rx qualified ANNOUNCE
          (Filtered)
E2E       DELAY_RESP      Rx qualified ANNOUNCE

In other cases, the activePeer field is set to 0

The fields in timePropertiesDS are been reevaluated. The file bmc.c
contains a table showing the different use cases.

For a GM the FSM must not be called until:
- the timing mode has not been programmed
- the clock quality has not been verified

These 2 actions : locking_reset() and enable_timing_output(0) must be
done also when the extension is not active.

If a port is in INITIALIZING state, we must not leave from this state as
for a GM we must stay in this state until the GM is locked.

The frequencyTraceable and timeTraceable fields in timePropertiesDS are
now set to TRUE only when the defaultDS clock class is
PTP_CLASS_GM_LOCKED(6) or PTP_CLASS_GM_HOLDOVER(7). These field values
will follow the degradation of the clock class in case of locking issue.

The wrs_locking_reset() function was sending a reset command that was
making the port going down. This function just play with the timing mode
now.

During intensive tests playing with ports up and down, the select() call
returned sometime the error value EINVAL because the given timeout was
negative.

This modification avoids duplication of files.

The timeout_t structure is already defined in libwr (wrs arch) and has
different fields. Renaming this local structure avoid compilation
conflicts.

Some default attribute values were not compliant with the PTP standard.
These default attribute values are used when :
- attributes are not defined in ppsi.conf file
- attribute values in ppsi.conf file are out of range

- Force L1SYNC DISABLE state when the extension is not ON
- Disabling of the PLL must be done only on slave/uncalibrated states
when we leave l1sync UP state.

As specified in the standard, the domain number must be in the range
[0,127]. The range [128-255] is reserved.

A master in P2P was responding to a Delay request message. A check for
the delay mechanism has been introduced to fix this issue.

This value should return to 1 when the new standard will be published
and HA released

In the new HAL version supporting LPDC, HAL set the timing mode to FR
and it must not be changed during all the calibration phase. So PPSI
needs to wait the end of the calibration before to change the timing
mode to GM if it is needed.
Also PPSi waits the end of HAL calibration before to consider a link up
on any port.

This new state is used by PPSi the end of the initialization of all
ports before starting to change the timing mode. This is particularly
the case for the GM mode which is set during the initialization of PPSi.

- Update the local definition of the HAL share memory
- Hide some structure specific to HAL like LPDC support

This is mainly to have wr_mon display correctly info about
extensin (whether it's active or not)

The port left led should indicate when the port is non-WR/HA.
This was not the case as a non WR/HA port in Master/Slave
state would still indicate WR link (should be "other").
This was corrected

The HAL states and the HAL share memory have changed. PPSi must follow
these modifications.

After around 36 hours, one PPS was missing. This was due to an issue in
the WR extension. When the sequence id in the announce message was
moving from 65535 to 0, the WR handshake was restarted. As a result of
that, the side effects would be :
- a missing PPS
- an unlock of the PLL