PPSi:672f53caf6aba1df30af48c64075dcfae329c3eb commitshttps://ohwr.org/project/ppsi/commits/672f53caf6aba1df30af48c64075dcfae329c3eb2019-10-11T11:52:22Zhttps://ohwr.org/project/ppsi/commit/672f53caf6aba1df30af48c64075dcfae329c3ebDo not execute BMCA when state is FAULTY2019-10-11T11:52:22ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/bac7d6202cddb77ba31130f473266953b8010b7cDiscard incoming messages for DISABLED/INITIALIZING/FAULTY states2019-10-11T11:52:22ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/e2be42384fe2bb51df4145a78efb849c1b54e8c4HA bug fixes2019-10-11T11:52:22ZJean-Claude Baujean-claude.bau@cern.ch
- Force L1SYNC DISABLE state when the extension is not ON
- Disabling of the PLL must be done only on slave/uncalibrated states
when we leave l1sync UP state.https://ohwr.org/project/ppsi/commit/9344198cb69c7166694a4ea27ba54d64e58bd3d2Display extension management fields in wrs_dump_shmem2019-10-11T11:52:21ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/002675afbae8707cde3f251438e5a881f1df11c3HA: Set PDETECTION state2019-10-11T11:52:21ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/a7ebba36bc15a76c3df1886e08296f1cda3b02b0Upgrade HA extension2019-10-11T11:52:21ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/58ebc13244105af8a02fca726c0d6b76fc20c118Update servo state name2019-10-11T11:52:20ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/15096993adf2b80d5b69648e624f8d3eaaa3dcbbLimit domain number to 1272019-10-11T11:52:20ZJean-Claude Baujean-claude.bau@cern.ch
As specified in the standard, the domain number must be in the range
[0,127]. The range [128-255] is reserved.https://ohwr.org/project/ppsi/commit/442feabfea6d23d9813cba7eac9bc8686b629a01Bug fix: master providing Dealy_Resp also in P2P mechanism2019-10-11T11:52:20ZJean-Claude Baujean-claude.bau@cern.ch
A master in P2P was responding to a Delay request message. A check for
the delay mechanism has been introduced to fix this issue.https://ohwr.org/project/ppsi/commit/37bd125dfdf5174997c86743d8b32c7c049bf31bSet MINOR_VERSION_PTP to 02019-10-11T11:52:20ZJean-Claude Baujean-claude.bau@cern.ch
This value should return to 1 when the new standard will be published
and HA releasedhttps://ohwr.org/project/ppsi/commit/39b837369007141a7adcb2e1d633cacd1be7f428Fix GM mode with new HAL behavior2019-10-11T11:52:20ZJean-Claude Baujean-claude.bau@cern.ch
In the new HAL version supporting LPDC, HAL set the timing mode to FR
and it must not be changed during all the calibration phase. So PPSI
needs to wait the end of the calibration before to change the timing
mode to GM if it is needed.
Also PPSi waits the end of HAL calibration before to consider a link up
on any port.https://ohwr.org/project/ppsi/commit/7a45bdcb2c508b3a81aeaed35ac238f615f1635dAdd state in HAL shared memory2019-10-11T11:52:20ZJean-Claude Baujean-claude.bau@cern.ch
This new state is used by PPSi the end of the initialization of all
ports before starting to change the timing mode. This is particularly
the case for the GM mode which is set during the initialization of PPSi.https://ohwr.org/project/ppsi/commit/8edf9486a607401c3189e5f25715131caef18851Synchronize PPSi with HAL share memory2019-10-11T11:52:20ZJean-Claude Baujean-claude.bau@cern.ch
- Update the local definition of the HAL share memory
- Hide some structure specific to HAL like LPDC supporthttps://ohwr.org/project/ppsi/commit/a999f8c440a48bdffee2de010151640238be78e2Removed definitions of SFP_LED_WRMODE_* from sfp_lib.h, they are used only in...2019-10-11T11:52:20ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/ppsi/commit/c0f964b7a669537b744048bf804944a1cf6ae9caclear extState when port is in DISABLED state (e.g. DOWN).2019-10-11T11:52:19ZMaciej Lipinskimaciej.lipinski@cern.ch
This is mainly to have wr_mon display correctly info about
extensin (whether it's active or not)https://ohwr.org/project/ppsi/commit/c938d2d15b492db3b72bdd29fcd6ef385d08bebaHAL share memory update for Low Phase Drift Calibration2019-10-11T11:52:19ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/a196bdc3ca3cfbcf017048889ec931e2abd2fda4[LEDs] correct behavior of the leds for non-WR/HA ports.2019-10-11T11:52:19ZMaciej Lipinskimaciej.lipinski@cern.ch
The port left led should indicate when the port is non-WR/HA.
This was not the case as a non WR/HA port in Master/Slave
state would still indicate WR link (should be "other").
This was correctedhttps://ohwr.org/project/ppsi/commit/92917a581b8aa402a1bc1a274f3cba8cd44d7d1dUpdate Hal share memory structure definition2019-10-11T11:52:19ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/9bfceb2b3a6949c2957e3f8dc488f98a608ff30fHAL code review: PPSi adaptation2019-10-11T11:52:19ZJean-Claude Baujean-claude.bau@cern.ch
The HAL states and the HAL share memory have changed. PPSi must follow
these modifications.https://ohwr.org/project/ppsi/commit/ec89448c1db94019a719c68329297f90edd210deFix PPS missing issue2019-08-14T13:02:19ZJean-Claude Baujean-claude.bau@cern.ch
After around 36 hours, one PPS was missing. This was due to an issue in
the WR extension. When the sequence id in the announce message was
moving from 65535 to 0, the WR handshake was restarted. As a result of
that, the side effects would be :
- a missing PPS
- an unlock of the PLLhttps://ohwr.org/project/ppsi/commit/135c480e387345315ed3d205342629fea45a1ca3wrh_servo: Print error message when the PLL is unlocking2019-08-02T13:12:30ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/48a914ff9349d34f9cf7d5f2607dec55560abfc1servo.c: Add comments2019-07-23T08:27:58ZJean-Claude Baujean-claude.bau@cern.ch
Just comments, no code changes.https://ohwr.org/project/ppsi/commit/13e4a0cfda3f368cb63edf5834fdd145a2f8a2d4Remove hack: Use tai field2019-07-03T12:23:37ZJean-Claude Baujean-claude.bau@cern.ch
Due to C library changes the tai field is now available in the structure
timex,https://ohwr.org/project/ppsi/commit/3436fdc8ff87dbaa8f6efadea813bfb8eb3f185fFix Clock identity calculation from mac address2019-06-21T15:37:49ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/b2195fc03215710df482cc8df1ab6d8d8a30448dBug fix: Error in servo calculation for negative delay asymmetry2019-06-14T15:17:26ZJean-Claude Baujean-claude.bau@cern.ch
- Problem was coming from the interval to pico conversion when the
interval is negative.
- fix also issue in wrs_ajust_in_progresshttps://ohwr.org/project/ppsi/commit/98746394741105f243e968b82504495b71b97fb0WR profile: Force asymmetryCorrectionEnable to true2019-06-12T09:36:24ZJean-Claude Baujean-claude.bau@cern.ch
As HA profile, the WR profile must always have the asymmetryCorrection
enabled.https://ohwr.org/project/ppsi/commit/3c27f391927480457dff031cdc8ccb15eb046230adjtimex: Clear structure to make a read only access2019-06-07T13:36:43ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/9b1ae8a387a078755e59b3df6a2b034dc464460cImprove WR extension protocol detection2019-06-06T13:59:13ZJean-Claude Baujean-claude.bau@cern.ch
When the extension is inactive due to some circonstances, an instance
will reactivate the extension when the instance will jump to
UNCALIBRATED state.https://ohwr.org/project/ppsi/commit/5fb66400289a6c525177e144e50830b2c6de0b20tools: add monotonicClock to .gitignore2019-06-05T15:11:32ZAdam Wujekadam.wujek@cern.chSigned-off-by: <span data-trailer="Signed-off-by:" data-user="9297"><a href="https://ohwr.org/awujek" title="adam.wujek@cern.ch"><img alt="Adam Wujek's avatar" src="https://secure.gravatar.com/avatar/bee62ad02d8f8c7c40900167722fb9d3?s=32&d=identicon" class="avatar s16 avatar-inline" title="Adam Wujek"></a><a href="https://ohwr.org/awujek" title="adam.wujek@cern.ch">Adam Wujek</a> <<a href="mailto:adam.wujek@cern.ch" title="adam.wujek@cern.ch">adam.wujek@cern.ch</a>></span>https://ohwr.org/project/ppsi/commit/552c0bc3cd1e672f7d6daa1c23a61454bc43b2c1time-wrs: improving error message in case mmap fail2019-06-05T14:26:48ZBenoit Ratbenoit@sevensols.comhttps://ohwr.org/project/ppsi/commit/53f668f2b7754b88fcb5023166de247b3a54ae23time-wrs: enable setting the RTS FPGA offset from arch-wrs2019-06-05T14:26:48ZBenoit Ratbenoit@sevensols.com
In the previous code all these values where hardcoded and thus difficult
to port to a device similar to wrs without needing to fully rewrite the
wrs-time.c. With this new code the user can now modify the device to
access to FPGA and the offset of RT subsystem.https://ohwr.org/project/ppsi/commit/d5c639b811686b6d4a24e65f80b80a6dddc9ac09time-wrs: using volatile to force HW access when adjust_freq2019-06-05T14:26:48ZBenoit Ratbenoit@sevensols.comhttps://ohwr.org/project/ppsi/commit/6b15236d77063e912d0fa7d7d34635342662fbfdignore files generated by IDE (eclipse, vscode, etc.)2019-06-05T14:26:48ZBenoit Ratbenoit@sevensols.com
Also ignore generated size_wrs_info.txthttps://ohwr.org/project/ppsi/commit/3a8a8a4fedf7ed8900638b72cc1a89e783aaa47darch-wrs: get hw specification from hal shmem instead of define2019-06-05T13:49:40ZBenoit Ratbenoit@sevensols.com
For security we still use define in the case that the hal as not
properly set these value.https://ohwr.org/project/ppsi/commit/6c8dd4fc33e25f3f38d2aa9f0a30c22dc92f5ee2wr-constants.h: Add missing include limit.h2019-06-05T09:43:38ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/420da467c4edbc76e830aca7a8b4b43be8e6ffddImprove behavior when link up->down->up not detected.2019-06-04T15:02:21ZJean-Claude Baujean-claude.bau@cern.ch
When the link state changes rapidly, it can't be detected by PPSi. This
is the case with the BTrain configuration. So we must detect that the
peer has changed and restart the servo for a slave and use the right
protocol (extension/ptp).https://ohwr.org/project/ppsi/commit/0e5b88179706580dec3375aede5ebdbe82d1ad37timeout.c: Fix issue on array of timer2019-06-04T11:47:45ZJean-Claude Baujean-claude.bau@cern.ch
The structure was not updated when the FAULT timer was removed.https://ohwr.org/project/ppsi/commit/1661d43bb662a07568fc4156273a287e1675ab2eSet instance state to DISABLED at startup2019-06-04T08:05:48ZJean-Claude Baujean-claude.bau@cern.ch
At startup the state of a instance is set to DISABLED and will be set
if the link is up to INITIALIZING. This is done to be coherent with the
curent behavior: the state becomes DISABLED when the link is downhttps://ohwr.org/project/ppsi/commit/043af2b4d68575034da03b302936cd5c459fb6b8Fix issue: Enable PPS output for GM when PLL not locked at startup2019-05-29T07:32:15ZJean-Claude Baujean-claude.bau@cern.chhttps://ohwr.org/project/ppsi/commit/a0091b90de4136b49805bb4044fc4318bbefaa25WR extension: Disable it when timeout detected during the handshake.2019-05-28T07:52:28ZJean-Claude Baujean-claude.bau@cern.ch