Commit f08c8449 authored by Alessandro Rubini's avatar Alessandro Rubini

Merge branch 'ML-bmc-fixes'

parents c8fd61ad 0cd4f99a
......@@ -246,7 +246,9 @@ passive:
return PPS_PASSIVE;
master:
m1(ppi);
//TODO: consider whether a smarter solution is needed for non-simple cases
if(cmpres < 0) // it is M1 and M2, see IEEE1588-2008, page 87, in short switch is a GM
m1(ppi); //GM
pp_diag(ppi, bmc, 1,"%s: master\n", __func__);
return PPS_MASTER;
......
......@@ -56,7 +56,6 @@ int st_com_execute_slave(struct pp_instance *ppi)
ppi->frgn_rec_num = 0;
if (DSDEF(ppi)->clockQuality.clockClass != PP_CLASS_SLAVE_ONLY
&& (ppi->role != PPSI_ROLE_SLAVE)) {
m1(ppi);
ppi->next_state = PPS_MASTER;
} else {
ppi->next_state = PPS_LISTENING;
......
......@@ -144,10 +144,10 @@ static int msg_pack_announce(struct pp_instance *ppi)
memset((buf + 34), 0, 10);
*(Integer16 *) (buf + 44) = htons(DSPRO(ppi)->currentUtcOffset);
*(UInteger8 *) (buf + 47) = DSPAR(ppi)->grandmasterPriority1;
*(UInteger8 *) (buf + 48) = DSDEF(ppi)->clockQuality.clockClass;
*(Enumeration8 *) (buf + 49) = DSDEF(ppi)->clockQuality.clockAccuracy;
*(UInteger8 *) (buf + 48) = DSPAR(ppi)->grandmasterClockQuality.clockClass;
*(Enumeration8 *) (buf + 49) = DSPAR(ppi)->grandmasterClockQuality.clockAccuracy;
*(UInteger16 *) (buf + 50) =
htons(DSDEF(ppi)->clockQuality.offsetScaledLogVariance);
htons(DSPAR(ppi)->grandmasterClockQuality.offsetScaledLogVariance);
*(UInteger8 *) (buf + 52) = DSPAR(ppi)->grandmasterPriority2;
memcpy((buf + 53), &DSPAR(ppi)->grandmasterIdentity,
PP_CLOCK_IDENTITY_LENGTH);
......
......@@ -64,8 +64,6 @@ int pp_initializing(struct pp_instance *ppi, unsigned char *pkt, int plen)
pp_diag(ppi, bmc, 1, "clock accuracy = %d\n",
DSDEF(ppi)->clockQuality.clockAccuracy);
m1(ppi);
msg_pack_header(ppi, ppi->tx_ptp); /* This is used for all tx */
if (ppi->role != PPSI_ROLE_MASTER)
......
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