Revision {#revision}
========

- [FIX] Rename RMII Rx data valid input in openMAC
- [FIX] Fix axi openMAC ipcore
- [FIX] Fix openMAC DMA address width
- [TASK] Update license header
- [FIX] Fix synthesis warnings in openMAC components
- [FEATURE] Create libraries for common vhdl sources
- [TASK] Move DPRAM components in memory subdirectory
- [TASK] Set ipcore versions to 1.0.0
- [TASK] Revise simulation handling
- [FIX] Fix openHUB doxygen documentation
- [FEATURE] Add openMAC doxygen documentation
- [TASK] Refactor openMAC core
- [FIX] Add select strobe for write decoding to openMAC timer
- [TASK] Remove POWERLINK IP-Core
- [FIX] Add simplex DPRAM implementation for Xilinx platform
- [FIX] Slave converter outputs byte addresses
- [FEATURE] Add Xilinx openMAC component
- [FEATURE] Add openMAC Qsys component
- [TASK] Refactor openMAC components
- [TASK] Rework openMAC toplevel
- [FIX] Fix synthesis warnings of openMAC and openHUB
- [FIX] Adapt stimuli files for revised bus master
- [TASK] Source file cleanup
- [FIX] X: openMAC DMA fifo component declaration
- [FIX] Eliminate false error in eclipse
- [TASK] Revise repo directory structure - 6
- [TASK] Revise repo directory structure - 3
- [TASK] Revise repo directory structure - 1
