Power PC FMC carrier (POWEC)
CANCELLED*
Project description
The Power PC FMC carrier is an FMC carrier that can hold one FMC card
and an SFP connector. On the CPU side it has plenty of various
interfaces, while the FMC mezzanine slot uses a low-pin count connector.
This board is optimised for cost and will be usable with most of the FMC
cards designed within the OHR project (e.g. ADC cards, Fine Delay). The
CPU is connected with the FPGA using one of its PCI Express ports as
well as with parallel local bus. The CPU enables the possibility of
direct FPGA reconfiguration using embedded software programmer.
The work is derived from the
SPEC and therefore licensed
under CERN OHL. The project was done with great help from Mikolaj
Jamrozy, student of the
WUT.
Main Features
* Power PC PPC405EX embedded CPU with FPU, MMU, PCI Express and Gigabit
Ethernet MAC
* FMC slot with low pin count (LPC) connector
o Vadj fixed to 2.5V
o No dedicated clock signals from Carrier to FMC (only available on HPC
pins)
o LPC cheaper than HPC and also easier to mount
o FMC connectivity: all 34 differential pairs connected, 1 GTP
transceiver with clock, 2 clock pairs, JTAG
* 1 Xilinx Spartan6 FPGA (XC6SLX45T)
* Simple clocking resources
o 1 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs Si570)
o 1 25 MHz TCXO controlled by a DAC with SPI interface (AD5662)
o 1 20 MHz VCXO controlled by a DAC with SPI interface (AD5662)
o 1 low-jitter frequency synthesizer (TI CDCM61004, fixed configuration,
Fout=125MHz)
o PCI Express 100MHz clock and buffer
* On board memory
o A 2Gbit DDR3 + 1Gbit DDR2 for CPU
o 1 SPI 32Mbit flash PROM for multiboot FPGA powerup configuration,
storage of the FPGA firmware or of critical data
o NAND & NOR Flash for CPU boot
* Front panel containing
o 1 Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver
(WhiteRabbit support)
o Programmable LED
o FMC front panel
o 2 Gigabit Ethernet RJ45 connectors
o 3 push button switches (2 user, 1 reset)
o several user and defined LEDs
* Rear panel containing
o DC jack for 12V supply
o USB 2.0 HS HOST connector
o USB 2.0 FS DEVICE (SPEC Terminal)
o USB 2.0 FS DEVICE (Power PC Terminal)
o RS232C (DB9) Power PC UART
o 1 SATA connector (FPGA GTP)
* Internal connectors
o 1 JTAG header for Xilinx programming during debugging
o Mini PCI Express connector
* FPGA configuration. The FPGA can optionally be programmed from:
o Power PC IO interface (loaded by software driver at startup)
o JTAG header
o SPI 32Mbit flash PROM
* On board peripherals
o RTC with battery
o Power PC expansion connector
* Optimised for cost
Releases
- Hardware: POWEC V1
Status
Date | Event |
---|---|
10-06-2011 | Start of project. Design will be done by Creotech company, based on the FMC Simple PCIe Carrier. |
11-01-2012 | Schematics and PCB review at Creotech |
01-02-2012 | Schematics and PCB ready for production |
19-09-2013 | Project cancelled due to good results obtained with ZYNQ SoC |
Grzegorz Kasprowicz, Michal Jamrozy