Review12042010
Design review of PCB layout of the NanoFIP Test Board
12 May 2010
PCB layout of 29 April 2010. All documentation of the verified version
at link
Present
Matthieu Cattin (BE/CO), Javier Serrano (BE/CO), Gonzalo Peñacoba (TE/CRG), Erik van der Bij (BE/CO)
General description of the design.
The company HLP has made the PCB layout for the design and made the pdfs of the different layers available for review.
PCB layout
Important*
- The PWR plane use many split planes. On the adjacent layers many signals are crossing the split, which causes EMC and signal quality problems. Suggest to add 2 layers for the different supplies to have less splits. Also verify that no signal lines are crossing the splits (return current should not need to cross from one domain to the other).
- The Gnd plane is also split in two for no obvious reason. Remove this.
- Decoupling capacitors: there is a long line from the via to the
decoupling capacitors (e.g page TOP). This will introduce an
inductor and make that fast currents cannot be delivered.
- Put the vias directly next to the decoupling capacitors.
- Give each decoupling capacitor its own via for accessing Gnd and Vcc.
- Shorten the line length between capacitor and IC power/Gnd pins.
- Do not share vias for different pins.
- Refer to some reference articles at http://hsi.web.cern.ch/HSI/s-link/devices/g-ldc/layout.html or other application notes.
- The outputs of the voltage regulators are connected with long lines
to the power planes.
- 1V5 regulator even has a very thin line and only one via. Similar with 5VFIP.
- Make these connections via very short and thick lines
- Have several vias to connect to the plane to reduce the current density in the via and to reduce the inductance.
- There are many long lines that seem to connect to Gnd or a Pwr. It seems that they share a single via (e.g. pins 1 of P5, P6, P9, P11) or P7, P8, P10, P12). See if they can have their own vias, reducing line length.
- It seems there are some vias exactly in the middle of the cuts in the power plane. This is dangerous as it may short-circuit the different planes together.
- There are some vias in the planes that we do not understand. These show up like little rings 'o'. What is the difference between those and the ones that show up as black dots?
- The DAT_I and DAT_O connectors have no Gnd or Vcc pins. Without these it will not be easy to set values or read them. Add Gnd and Vcc pins so that the board can be easier used for testing and simple applications (needs 2 pins additional per connector).
- Add Gnd and Vcc test points on the board (Vcc relative to DAT_I and DAT_O).
- Top solder mask: near U6 (regulator) there is a very large square where a 'blob' of solder will be put. This square is too large as the solder will not be spread evenly. Better to split it up in several (four?) smaller windows.
- Bottom solder mask: U6 does not need solder at the bottom, only at the top layer.
- Top solder mask: Fieldrive has solder under the package, while there is no heatsink there. Verify with datasheet and remove if needed.
Minor*
- Silkscreen: add text "CERN NanoFIP test board"
- Scaling: all pages are marked "Echelle 1:2" while they are on different sizes (notably the ones with 2 layers on one page).
- The symbol on the PCB for the switches (jumpers?) is the same as for the 3M connectors. This is confusing and should be changed.
Other
- The controller FPGA code should have triplicated logic if possible, to guarantee that even little radiation will not generate single event upsets.
- Production documentation is missing (BOM, assembly of heating resistors, where to mount switches/jumpers/connectors, etc.).
- Not all comments from the schematics
review are replied to.
- e.g. why 24 MHz and 40 MHz, evaluate the voltage drop in cable.
- Please reply on the page Review25032010-improvements.
Related to next steps in project
- Which CAE tool is used? We need either a .brd file or gerber files (less preferred) to verify in more detail the layout.
- Are the components ordered?
- How is the software development going?
- What test software will be developed on the Host side?
Conclusions
This has been a very useful review that revealed several issues that will make the design more robust and that will improve its documentation. As there are major corrections to be done, another review will be needed before the PCB may be produced. We thank all people involved in the review.
- Erik van der Bij - 12 May 2010