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nanoFIP - Gateware
Commit faa2b429 authored by egousiou's avatar egousiou
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rstpon considered for wb_rst 

nanofip status byte bit 5 considers also manch. encoding errors
wf_tx_serializer state synch_to_txclk added
all units cleaned up

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@126 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 7e6a0c2a
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DualClkRAM.vhd
View file @ faa2b429
......@@ -236,7 +236,7 @@ begin
WMODEA => GROUND,
-- INPUTS concerning port B
-- datain B (1 byte, (7 downto 0))
-- data in B (1 byte, (7 downto 0))
DINB8 => GROUND,
DINB7 => DINB(7),
DINB6 => DINB(6),
......@@ -275,7 +275,7 @@ begin
-- Oututs
-- output concerning port A
-- dataout A (1 byte)
-- data out A (1 byte)
DOUTA8 => OPEN,
DOUTA7 => DOUTA(7),
DOUTA6 => DOUTA(6),
......@@ -287,7 +287,7 @@ begin
DOUTA0 => DOUTA(0),
-- output concerning port B
-- dataout B (1 byte)
-- data out B (1 byte)
DOUTB8 => OPEN,
DOUTB7 => DOUTB(7),
DOUTB6 => DOUTB(6),
......
nanofip.vhd
View file @ faa2b429
......@@ -57,8 +57,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! After a 14xy or a 10xy or a 06xy ID_DAT, if nanoFIP's address (SUBS) is xy, it will respond
--! with a "produced" RP_DAT frame, containing the variable requested. Figure 2 shows the structure
--! of a RP_DAT frame:
--! ___________ ______ _____________________ ___________ _______
--! |____FSS____|_Ctrl_||_____...-Data..._____||____FCS____|__FES__|
--! ___________ ______ ____________________ ___________ _______
--! |____FSS____|_Ctrl_||_____...Data..._____||____FCS____|__FES__|
--!
--! Figure 2 : RP_DAT frame structure
--!
......@@ -77,6 +77,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o External reset input pin, RST_I, activated by the user, that resets only the WISHBONE logic
--! o Addressed reset by the reset broadcast consumed variable (E0..h),
--! validated by station address as data
--! o External Power On Reset input pin, RSTPON
--!
--! nanoFIP also provides resets to the user and to the FIELDRIVE:
--! o Reset output available to external logic (RSTON) by the reset broadcast consumed variable
......@@ -85,7 +86,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! validated by station address as data
--!
--! nanoFIP's main building blocks are (Figure 3):
--! o WF_inputs_synchronizer : for the synchronization of all the input signals with the user
--! o WF_inputs_synchronizer : for the synchronization of the input signals with the user
--! or the WISHBONE clock.
--! o WF_reset_unit : for the treatment of the reset input signals and the generation
--! of the reset outputs.
......@@ -141,7 +142,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Complete information about this project at: http://www.ohwr.org/projects/cern-fip
--
--
--! @author Erik Van der Bij (Erik.Van.der.Bij@cern.ch) \n
--! @authors Erik Van der Bij (Erik.Van.der.Bij@cern.ch) \n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
......@@ -162,6 +163,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! WF_consumption \n
--! WF_production \n
--! WF_engine_control \n
--! WF_wb_controller \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -189,7 +191,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- Synplify Premier Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W MT420 Found inferred clock nanofip|wclk_i"; "W MT420 Found inferred clock nanofip|uclk_i" --
-- The wclk and uclk are the nanoFIP's input clocks. --
-- The wclk and uclk are the nanoFIP's input clocks. --
---------------------------------------------------------------------------------------------------
......@@ -255,7 +257,7 @@ entity nanofip is
we_i : in std_logic; --! WISHBONE write enable
-- OUTUTS
-- OUTPUTS
-- WorldFIP settings
......@@ -322,8 +324,8 @@ architecture struc of nanofip is
signal s_rst, s_rx_byte_ready, s_start_prod_p, s_rst_rx_osc, s_prod_request_byte_p : std_logic;
signal s_prod_last_byte_p : std_logic;
signal s_rstin_synch, s_slone_synch, s_nostat_synch, s_fd_wdgn_synch, s_fd_txer_synch: std_logic;
signal s_fss_crc_fes_manch_ok_p, s_cons_fss_decoded_p : std_logic;
signal s_crc_wrong_p, s_reset_nFIP_and_FD_p, s_rx_manch_clk_p, s_rx_bit_clk_p : std_logic;
signal s_fss_crc_fes_manch_ok_p, s_cons_fss_decoded_p, s_wb_rst, s_rx_bit_clk_p : std_logic;
signal s_crc_or_manch_wrong_p, s_reset_nFIP_and_FD_p, s_rx_manch_clk_p : std_logic;
signal s_var1_access_synch, s_var2_access_synch, s_var3_access_synch, s_wb_stb_synch : std_logic;
signal s_var1_rdy, s_var2_rdy, s_var3_rdy, s_assert_RSTON_p, s_wb_ack_prod : std_logic;
signal s_rst_rx_unit_p, s_nfip_status_r_tler, s_signif_edge_window , s_wb_we_synch : std_logic;
......@@ -355,7 +357,7 @@ begin
wb_clk_i => wclk_i,
nfip_rst_i => s_rst,
rstin_a_i => rstin_i,
wb_rst_a_i => rst_i,
wb_rst_i => s_wb_rst,
slone_a_i => slone_i,
nostat_a_i => nostat_i,
fd_wdgn_a_i => fd_wdgn_i,
......@@ -387,7 +389,7 @@ begin
wb_cyc_o => s_wb_cyc_synch,
wb_we_o => s_wb_we_synch,
wb_stb_o => s_wb_stb_synch,
wb_stb_r_edge_o => s_wb_stb_r_edge,
wb_stb_r_edge_p_o => s_wb_stb_r_edge,
var1_access_o => s_var1_access_synch,
var2_access_o => s_var2_access_synch,
var3_access_o => s_var3_access_synch,
......@@ -411,12 +413,14 @@ begin
rstin_i => s_rstin_synch,
rstpon_i => rstpon_i,
rate_i => s_rate_synch,
rst_i => rst_i,
var_i => s_var_from_control,
rst_nFIP_and_FD_p_i => s_reset_nFIP_and_FD_p,
assert_RSTON_p_i => s_assert_RSTON_p,
---------------------------------------------------------
rston_o => rston_o,
nFIP_rst_o => s_rst,
wb_rst_o => s_wb_rst,
rston_o => rston_o,
fd_rstn_o => fd_rstn_o
---------------------------------------------------------
);
......@@ -475,8 +479,8 @@ begin
byte_o => s_rx_byte,
byte_ready_p_o => s_rx_byte_ready,
fss_received_p_o => s_cons_fss_decoded_p,
crc_wrong_p_o => s_crc_wrong_p,
fss_crc_fes_manch_ok_p_o => s_fss_crc_fes_manch_ok_p,
crc_or_manch_wrong_p_o => s_crc_or_manch_wrong_p,
fss_crc_fes_manch_ok_p_o=> s_fss_crc_fes_manch_ok_p,
nfip_status_r_tler_o => s_nfip_status_r_tler,
assert_rston_p_o => s_assert_RSTON_p,
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p,
......@@ -512,7 +516,7 @@ begin
byte_request_accept_p_i => s_prod_byte_ready_p,
last_byte_p_i => s_prod_last_byte_p,
nfip_status_r_tler_i => s_nfip_status_r_tler,
nfip_status_r_fcser_p_i => s_crc_wrong_p,
nfip_status_r_fcser_p_i => s_crc_or_manch_wrong_p,
var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy,
tx_clk_p_buff_i => s_tx_clk_p_buff,
......@@ -538,7 +542,6 @@ begin
engine_control : WF_engine_control
generic map( c_QUARTZ_PERIOD => c_QUARTZ_PERIOD)
port map(
uclk_i => uclk_i,
nfip_rst_i => s_rst,
......@@ -547,7 +550,7 @@ begin
rx_byte_i => s_rx_byte,
rx_byte_ready_p_i => s_rx_byte_ready,
rx_fss_crc_fes_manch_ok_p_i => s_fss_crc_fes_manch_ok_p,
rx_crc_wrong_p_i => s_crc_wrong_p,
rx_crc_or_manch_wrong_p_i => s_crc_or_manch_wrong_p,
rate_i => s_rate_synch,
subs_i => s_subs_synch,
p3_lgth_i => s_p3_lgth_synch,
......
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ faa2b429
......@@ -17,23 +17,26 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! Specific Packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_DualClkRAM_clka_rd_clkb_wr --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name WF_DualClkRAM_clka_rd_clkb_wr.vhd
--
--
--! @brief The unit provides, transparently to the outside world, the memory triplication.
--! The component DualClkRam (512 bytes) is triplicated; each incoming byte is written
--! @brief The unit provides the memory triplication, transparently to the outside world.
--! The component DualClkRam (512 bytes) is triplicated: each incoming byte is written
--! at the same position in the three memories, whereas each outgoing byte is the
--! outcome of a majority voter.
--! The memory is dual port; port A is used for reading only, port B for writing only.
--!
--! Remark: MajorityVoter(A,B,C) = (A and B) OR (A and C) OR (B and C)
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
......@@ -103,26 +106,6 @@ end WF_DualClkRAM_clka_rd_clkb_wr;
architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
---------------------------------------------------------------------------------------------------
--!@brief: component DualClkRam declaration
component DualClkRam is
port(
CLKA : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
DINA : in std_logic_vector (7 downto 0);
RWA : in std_logic;
CLKB : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DINB : in std_logic_vector (7 downto 0);
RWB : in std_logic;
RESETn : in std_logic;
DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector (7 downto 0)
);
end component DualClkRam;
---------------------------------------------------------------------------------------------------
type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
......@@ -169,13 +152,11 @@ end generate;
---------------------------------------------------------------------------------------------------
--!@brief majority voter: when a reading is done from the memory, the output of the unit is the
--! output of the majority voter. The majority voter considers the outputs of the three memories
--! and "calculates" their majority with combinatorial logic.
--!@brief Combinatorial Majority_Voter
majority_voter: data_porta_o <= (data_o_A_array(0) and data_o_A_array(1)) or
(data_o_A_array(1) and data_o_A_array(2)) or
(data_o_A_array(2) and data_o_A_array(0));
Majority_Voter: data_porta_o <= (data_o_A_array(0) and data_o_A_array(1)) or
(data_o_A_array(1) and data_o_A_array(2)) or
(data_o_A_array(2) and data_o_A_array(0));
end syn;
--=================================================================================================
......
wf_bits_to_txd.vhd
View file @ faa2b429
......@@ -119,7 +119,7 @@ end entity WF_bits_to_txd;
--! architecture declaration
--=================================================================================================
architecture rtl of WF_bits_to_txd is
signal s_fss : std_logic_vector (31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -162,6 +162,7 @@ begin
end if;
end process;
s_fss<=c_FSS;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the
......
wf_cons_bytes_processor.vhd
View file @ faa2b429
......@@ -26,7 +26,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: WF_cons_bytes_processor
--
--! @brief The unit is consuming the data bytes that are arriving from the WF_rx_deserializer,
--! according to the following:
......@@ -37,25 +36,24 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! application-data bytes along with the PDU_TYPE, Length and MPS bytes in the
--! Consumed memories
--!
--! o If the operation is in standalone mode: the unit is transferring the 2 appli-
--! o If the operation is in stand-alone mode: the unit is transferring the 2 appli-
--! cation-data bytes to the "nanoFIP User Interface, NON_WISHBONE" data bus DAT_O
--!
--! o If the consumed variable had been a var_rst, the 2 application-data bytes are just
--! identified and sent to the WF_reset_unit.
--!
--! ------------------------------------------------------------------------------------
--!
--! Reminder:
--!
--! Consumed RP_DAT frame structure :
--! ___________ ______ _______ ________ __________________ _______ ___________ _______
--! |____FSS____|_Ctrl_||__PDU__|__LGTH__|__..ApplicData..__|__MPS__||____FCS____|__FES__|
--!
--! |-------LGTH bytes-------|
--! |--------write to Consumed memory---------|
--! |----to DAT_O----|
--! |--to ResetUnit--|
--! |--------LGTH bytes--------|
--! |---------write to Consumed memory----------|
--! |-----to DAT_O-----|
--! |---to Reset Unit--|
--!
--! ------------------------------------------------------------------------------------
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
......@@ -246,7 +244,7 @@ begin
--! are written in the memory one by one as they arrive, on the moments when the signal
--! byte_ready_p_i is active.
--! The signals byte_index_i and Length (s_cons_lgth_byte) are used to distinguish the Control and
--! CRC bytes from hte rest:
--! CRC bytes from the rest:
--! o the Control byte arrives when byte_index_i = 0
--! o the CRC bytes arrive $Length bytes after the Length byte
--! The byte_index_i signal is counting each byte after the FSS and before the FES.
......@@ -416,12 +414,12 @@ end process;
---------------------------------------------------------------------------------------------------
-- Control, PDU_TYPE, Length bytes --
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Buffer_Ctrl_PDU_Length_bytes: Storage of the Control, PDU_TYPE
--!@brief Synchronous process Register_Ctrl_PDU_Length_bytes: Storage of the Control, PDU_TYPE
--! and Length bytes of an incoming RP_DAT frame. The bytes are sent to the WF_cons_frame_validator
--! unit that validates them and accordingly signals the WF_outcome unit for the activation of the
--! VAR1_RDY(for a var_1), VAR2_RDY(for a var_2), assert_rston_p & rst_nfip_and_fd_p(for a var_rst).
Buffer_Ctrl_PDU_Length_bytes: process (uclk_i)
Register_Ctrl_PDU_Length_bytes: process (uclk_i)
begin
if rising_edge (uclk_i) then
......
wf_cons_bytes_to_dato.vhd
View file @ faa2b429
......@@ -27,9 +27,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief In stand-alone mode, after the reception of a consumed or consumed broadcast
--! variable, the unit is responsible for transering the two application-data bytes to
--! the 2-bytes long bus DAT_O.
--! @brief In stand-alone mode, after the reception of a consumed (var_1) or a consumed
--! broadcast variable (var_2), the unit is responsible for transering the two
--! application-data bytes to the 2-bytes long bus DAT_O.
--! The bytes are put in the bus one by one as they arrive, as the signal
--! transfer_byte_p_i indicates.
--!
......@@ -101,7 +101,7 @@ entity WF_cons_bytes_to_dato is
-- OUTPUTS
-- Signal to the WF_prod_bytes_retriever
-- nanoFIP, User Interface NON WISHBONE output
slone_data_o : out std_logic_vector (15 downto 0) --! output bus DAT_O
);
end entity WF_cons_bytes_to_dato;
......@@ -119,9 +119,9 @@ architecture rtl of WF_cons_bytes_to_dato is
begin
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Data_Transfer_To_Dat_o: In stand-alone mode, accrording to the signal
--! transfer_byte_p_i, the first or second byte of the user interface bus DAT_O takes the
--! incoming byte byte_i.
--!@brief Synchronous process Data_Transfer_To_Dat_o: In stand-alone mode, according to the signal
--! transfer_byte_p_i, the first or second byte of the "User Interface, NON WISHBONE" bus DAT_O
--! takes the byte byte_i.
Data_Transfer_To_Dat_o: process (uclk_i)
begin
......
wf_cons_frame_validator.vhd
View file @ faa2b429
......@@ -22,22 +22,30 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_cons_frame_validator --
-- WF_cons_frame_validator --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Validation of a consumed RP_DAT frame with respect to the correctness of:
--! o the Control, PDU_TYPE and Length bytes. The unit receives those
--! bytes from the the WF_cons_bytes_processor unit.
--! o the CRC, FSS and FES bytes. The unit receives those bytes from
--! the WF_rx_deserializer unit.
--! o the manchester encoding (no occurence of unwanted code violations).
--! This information comes also from the WF_rx_deserializer unit.
--! o the Control, PDU_TYPE and Length bytes;
--! the bytes are received from the the WF_cons_bytes_processor unit.
--! o the CRC, FSS, FES bytes and the Manchester encoding;
--! the rx_fss_crc_fes_manch_ok_p_i pulse from the WF_rx_deserializer unit groups
--! these checks.
--!
--! The output cons_frame_ok_p is used by the WF_cons_outcome unit, which treats
--! The output cons_frame_ok_p is used by the WF_cons_outcome unit, which handles
--! accordingly the signals VAR1_RDY/ VAR2_RDY (if it had been a var_1 or a var_2)
--! or the signals nFIP_and_FD_p/ assert_RSTON_p (if it had been a var_rst)
--!
--!
--! Reminder:
--!
--! Consumed RP_DAT frame structure :
--! ___________ ______ _______ ______ _________________________ _______ ___________ _______
--! |____FSS____|_Ctrl_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__|
--!
--! |---------------LGTH bytes---------------|
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......@@ -53,13 +61,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_cons_bytes_processor \n
--! WF_engine_control \n
--! WF_rx_deserializer \n
--! WF_cons_bytes_processor \n
--! WF_engine_control \n
--! WF_rx_deserializer \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......@@ -101,13 +109,13 @@ entity WF_cons_frame_validator is
-- Signals from the WF_engine_control unit
rx_byte_index_i : in std_logic_vector (7 downto 0); --! index of byte being received
var_i : in t_var; --! variable type that is being treated
var_i : in t_var; --! variable type that is being treated
-- OUTPUT
-- Signal to the WF_cons_outcome unit
cons_frame_ok_p_o : out std_logic; --! pulse at the end of the FES
--! indicating a valid frame
--! indicating a valid received RP_DAT frame
-- Signal to the WF_status_bytes_gen unit
nfip_status_r_tler_o : out std_logic --! received PDU_TYPE or Length error
......@@ -131,7 +139,7 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Consumed_Frame_Validator: validation of an RP_DAT
--! frame with respect to the Ctrl, PDU_TYPE and Length bytes as well as to the CRC, FSS, FES and
--! to the manchester encoding. The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that
--! to the Manchester encoding. The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that
--! arrive at the beginning of a frame, have been registered and keep their values until the end
--! of it. The signal rx_fss_crc_fes_manch_ok_p_i, is a pulse at the end of the FES that combines
--! the checks of the FSS, CRC, FES and of the manch. encoding.
......@@ -163,8 +171,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_fss_crc_fes_manch_ok_p_i = '1' then -- checking the RP_DAT.Data.Length
-- byte, when the end of frame
-- arrives correctly.
-- byte, when the FES arrives.
if unsigned(rx_byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5) then
s_cons_lgth_byte_ok <= '1'; -- rx_byte_index starts counting
-- from 0 and apart from the
......
wf_cons_outcome.vhd
View file @ faa2b429
......@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--
--! @brief According to the consumed variable that has been received (var_1, var_2, var_rst)
--! and the outcome of the WF_cons_frame_VALIDATOR, the unit generates the signals:
--! and the output of the WF_cons_frame_validator, the unit generates the signals:
--!
--! o "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY and VAR2_RDY,
--! o rst_nFIP_and_FD_p and assert_RSTON_p, that are inputs to the WF_reset_unit.
......@@ -48,7 +48,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_enginr_control \n
--! WF_engine_control \n
--! WF_cons_frame_validator \n
--! WF_cons_bytes_processor \n
--
......@@ -90,11 +90,11 @@ entity WF_cons_outcome is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode
-- nanoFIP WorldFIP Settings (synchronized with uclk)
subs_i : in std_logic_vector (7 downto 0); --! subscriber number coding
subs_i : in std_logic_vector(7 downto 0);--! subscriber number coding
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
......@@ -110,7 +110,7 @@ entity WF_cons_outcome is
cons_var_rst_byte_2_i : in std_logic_vector(7 downto 0);--! 2nd data-byte of a received var_rst
-- OUTPUT
-- OUTPUTS
-- nanoFIP User Interface, NON-WISHBONE outputs
var1_rdy_o : out std_logic; --! signals new data is received and can safely be read
var2_rdy_o : out std_logic; --! signals new data is received and can safely be read
......@@ -144,9 +144,9 @@ begin
--!@brief Synchronous process VAR_RDY_Generation:
--! Memory Mode:
--! Since the three memories (consumed, consumed broadcast, produced) are independant, when a
--! produced var. is being sent, the user can read form the consumed memories; similarly, when a
--! consumed var. is being received the user can read from the consumed broadcast memory.
--! Since the three memories (consumed, consumed broadcast, produced) are independent, when a
--! produced var is being sent, the user can read form the consumed memories; similarly, when a
--! consumed var is being received the user can read from the consumed broadcast memory.
--! VAR1_RDY (for consumed vars): signals that the user can safely read from the consumed memory.
--! The signal is asserted only after the reception of a correct RP_DAT frame.
......@@ -160,9 +160,9 @@ begin
--! Stand-alone Mode:
--! Similarly, in stand-alone mode, the DAT_I and DAT_O buses for the produced and the consumed
--! bytes are independant. Stand-alone mode though does not treat the consumed broadcast variable.
--! bytes are independent. Stand-alone mode though does not treat the consumed broadcast variable.
--! VAR1_RDY (for consumed vars): signals that the user can safely retreive data from the DAT_O
--! VAR1_RDY (for consumed vars): signals that the user can safely retrieve data from the DAT_O
--! bus. The signal is asserted only after the reception of a correct RP_DAT frame.
--! It is de-asserted after the reception of a correct var_1 ID_DAT frame(same as in memory mode).
......@@ -172,7 +172,7 @@ begin
--! ID_DAT frame along with the variable it contained is signaled by the var_i.
--! For consumed variables, var_i gets its value (var_1, var_2, var_rst) after the reception of a
--! correct ID_DAT frame and of a correct FSS of the corresponding RP_DAT frame and it retains it
--! unitl the end of the reception.
--! until the end of the reception.
VAR_RDY_Generation: process (uclk_i)
begin
......
wf_consumption.vhd
View file @ faa2b429
......@@ -35,8 +35,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--!
--! o WF_rx_deserializer : for the formation of bytes of data
--!
--! o WF_cons_bytes_processor : for the handling of the data as they arrive (mainly
--! registering them to the RAM or putting them to DAT_O)
--! o WF_cons_bytes_processor : for the handling of the data as they arrive
--! (registration to the RAM or outputting to the DAT_O)
--!
--! o WF_cons_frame_validator : for the validation of the consumed frame, at the end of
--! of its arrival (in terms of FSS, Ctrl, PDU_TYPE, Lgth,
......@@ -76,9 +76,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--!
--! _______________________________________________________________
--! 0__________________________FIELDBUS____________________________O
--1
--!
--! Note: In the entity declaration of this unit, below each input signal, we mark
--!
--! Important Notice : The WF_rx_deserializer is "blindly" responsible for the formation
--! of bytes arriving to the FD_RXD input. The bytes belong to either RP_DAT or ID_DAT
--! frames. The WF_cons_bytes_processor is in charge of the RP_DATs, whereas the
--! external unit WF_engine_control is in charge of the ID_DATs.
--!
--! Note : In the entity declaration of this unit, below each input signal, we mark
--! which of the instantiated units needs it.
--
--
......@@ -136,7 +141,7 @@ entity WF_consumption is
-- used by: all the units
slone_i : in std_logic;
-- used by: WF_cons_bytes_processor for selecting the data storage (RAM or DATO bus)
-- used by: WF_cons_bytes_processor for selecting the data storage (RAM or DAT_O bus)
-- used by: WF_cons_outcome for the VAR2_RDY signal (stand-alone mode does not treat var_2)
......@@ -216,7 +221,7 @@ entity WF_consumption is
fss_crc_fes_manch_ok_p_o : out std_logic;
-- Signals to the WF_engine_control and the WF_produce
crc_wrong_p_o : out std_logic;
crc_or_manch_wrong_p_o : out std_logic;
-- Signals to the WF_produce
nfip_status_r_tler_o : out std_logic;
......@@ -238,8 +243,9 @@ end entity WF_consumption;
--=================================================================================================
architecture struc of WF_consumption is
signal s_rxd_filtered, s_rxd_filtered_f_edge_p, s_cons_frame_ok_p, s_crc_wrong_p : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p, s_fss_crc_fes_manch_ok_p, s_byte_ready_p: std_logic;
signal s_rxd_filtered,s_rxd_filtered_f_edge_p,s_cons_frame_ok_p : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p, s_fss_crc_fes_manch_ok_p : std_logic;
signal s_crc_or_manch_wrong_p, s_byte_ready_p : std_logic;
signal s_cons_ctrl_byte, s_cons_pdu_byte, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_cons_var_rst_byte_1, s_cons_var_rst_byte_2 : std_logic_vector (7 downto 0);
signal s_byte_from_rx : std_logic_vector (7 downto 0);
......@@ -251,7 +257,7 @@ architecture struc of WF_consumption is
begin
---------------------------------------------------------------------------------------------------
-- Consumption Level 0: Deglitcher --
-- Deglitcher --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_rx_deglitcher unit that applies a glitch filter to the "nanoFIP
--! FIELDRIVE" input signal fd_rxd.
......@@ -272,8 +278,10 @@ begin
-------------------------------------------------
);
---------------------------------------------------------------------------------------------------
-- Consumption Level 0 : Deserializer --
-- Deserializer --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_rx_deserializer unit that deserializes the deglitched fd_rxd
--! and constructs bytes of data.
......@@ -297,12 +305,14 @@ begin
fss_crc_fes_manch_ok_p_o => s_fss_crc_fes_manch_ok_p,
rst_rx_osc_o => rst_rx_osc_o,
fss_received_p_o => fss_received_p_o,
crc_wrong_p_o => s_crc_wrong_p
crc_or_manch_wrong_p_o => s_crc_or_manch_wrong_p
-------------------------------------------------
);
---------------------------------------------------------------------------------------------------
-- Consumption Level 1 : Bytes Processing --
-- Bytes Processing --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_cons_bytes_processor unit that is "consuming" data bytes
--! arriving from the WF_rx_deserializer, by registering them to the Consumed memories or by
......@@ -329,8 +339,10 @@ begin
-------------------------------------------------
);
---------------------------------------------------------------------------------------------------
-- Consumption Level 2 : Validation --
-- Frame Validation --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_cons_frame_validator unit, responsible for the validation of a
--! received RP_DAT frame with respect to the correctness of the Control, PDU_TYPE and Length
......@@ -351,8 +363,9 @@ begin
);
---------------------------------------------------------------------------------------------------
-- Consumption Level 2 : Outcome --
-- Outcome --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_cons_outcome unit that is generating :
--! the "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY & VAR2_RDY (for a var_1/2)
......@@ -384,7 +397,7 @@ begin
byte_o <= s_byte_from_rx;
byte_ready_p_o <= s_byte_ready_p;
fss_crc_fes_manch_ok_p_o <= s_fss_crc_fes_manch_ok_p;
crc_wrong_p_o <= s_crc_wrong_p;
crc_or_manch_wrong_p_o <= s_crc_or_manch_wrong_p;
end architecture struc;
......
wf_crc.vhd
View file @ faa2b429
This diff is collapsed.
wf_decr_counter.vhd
View file @ faa2b429
......@@ -24,8 +24,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
--
--
--! @brief Synchronous decreasing counter with a reset, a load enable & a decrease
--! enable signal.
--! @brief Decreasing counter with synchronous reset, load enable and decrease enable.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
......@@ -68,7 +67,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
entity WF_decr_counter is
generic (g_counter_lgth : natural := 4); --! default length
generic (g_counter_lgth : natural := 4); --! default length
port (
-- INPUTS
-- nanoFIP User Interface general signal
......
wf_engine_control.vhd
View file @ faa2b429
......@@ -33,8 +33,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! During the production or consumption the unit is keeping track of the amounts of
--! produced and consumed bytes.
--!
--! ------------------------------------------------------------------------------------
--! Reminder
--!
--! Reminder:
--!
--! ID_DAT frame structure :
--! ___________ ______ _______ ______ ___________ _______
......@@ -53,10 +53,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--!
--! Turnaround time : Time between the end of the reception of an ID_DAT frame
--! requesting for a variable to be produced and the starting of the delivery of a
--! produced RP_DAT frame
--! produced RP_DAT frame.
--!
--! Silence time : Maximum time that nanoFIP waits for a consumed RP_DAT frame after
--! the reception of an ID_DAT frame indicating a variable to be consumed
--! the reception of an ID_DAT frame indicating a variable to be consumed.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
......@@ -94,12 +94,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! for #bytes>4; in slone no broadcast
--! 01/2011 v0.04 EG signals named according to their origin; signals var_rdy (1,2,3),
--! assert_rston_p_o,rst_nfip_and_fd_p_o, nFIP status bits and
--! rx_byte_ready_p_o removedl cleaning-up+commenting
--! rx_byte_ready_p_o removed cleaning-up+commenting
--
---------------------------------------------------------------------------------------------------
--
--! @todo -> add an extra time counter (on top of the more complicated bytes counters) that after
--! 134*8 transmission periods can reset tx and rx
--! @todo -> could add an extra time counter (on top of the more complicated bytes counters) that
--! after 134*8 transmission periods can reset tx and rx
--!
---------------------------------------------------------------------------------------------------
......@@ -153,7 +153,7 @@ entity WF_engine_control is
rx_fss_crc_fes_manch_ok_p_i: in std_logic; --! indication of a frame (ID_DAT or RP_DAT) with
--! correct FSS, FES, CRC and manch. encoding
rx_crc_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC
rx_crc_or_manch_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC or manch.
-- pulse arrives after the FES detection
rx_fss_received_p_i : in std_logic; --! pulse after a correct FSS detection (ID/ RP_DAT)
......@@ -220,7 +220,7 @@ architecture rtl of WF_engine_control is
signal s_producing, s_consuming, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_cons_wait_FSS : std_logic;
signal s_prod_data_length_match, s_tx_byte_request_accept_p, s_prod_wait_turnar_time : std_logic;
signal s_tx_byte_request_accept_p_d1, s_load_time_counter, s_prod_time_over : std_logic;
signal s_tx_byte_request_accept_p_d1, s_load_time_counter : std_logic;
signal s_rst_rx_bytes_counter, s_tx_last_byte_p_d, s_tx_last_byte_p : std_logic;
signal s_id_dat_subs_byte, s_id_dat_frame_ok, s_tx_byte_request_accept_p_d2 : std_logic;
signal s_rx_bytes_c, s_prod_bytes_c : unsigned (7 downto 0);
......@@ -282,7 +282,7 @@ begin
s_var_id, rx_byte_ready_p_i,rx_byte_i,
control_st, rx_fss_received_p_i,
s_rx_bytes_c, s_tx_last_byte_p,
rx_crc_wrong_p_i)
rx_crc_or_manch_wrong_p_i)
begin
......@@ -392,7 +392,7 @@ begin
when consume =>
if (rx_fss_crc_fes_manch_ok_p_i = '1') or -- the cons frame arrived to the end,as expected
(rx_crc_wrong_p_i = '1') or -- FES detected but wrong CRC or manch. encoding
(rx_crc_or_manch_wrong_p_i = '1') or -- FES detected but wrong CRC or manch. encoding
(s_rx_bytes_c > 130) then -- no FES detected after the max number of bytes
nx_control_st <= idle; -- back to idle
......@@ -844,7 +844,7 @@ begin
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief: Essential buffering of the signals tx_last_byte_p_o, tx_byte_request_accept_p_o,tx_start_prod_p_o
--!@brief: Registering the signals tx_last_byte_p_o, tx_byte_request_accept_p_o,tx_start_prod_p_o
process (uclk_i)
begin
......
wf_incr_counter.vhd
View file @ faa2b429
......@@ -24,8 +24,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
--
--
--! @brief Synchronous increasing counter with a reset, a reinitialise and an increase
--! enable signal.
--! @brief Increasing counter with synchronous reset, reinitialise and increase enable.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
......@@ -48,6 +47,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 01/2011 EG v0.011 counter_full became a constant
--
---------------------------------------------------------------------------------------------------
--
......@@ -69,7 +69,7 @@ entity WF_incr_counter is
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from any unit
incr_counter_i : in std_logic; --! increment enable
......@@ -90,15 +90,14 @@ end entity WF_incr_counter;
--=================================================================================================
architecture rtl of WF_incr_counter is
signal c_COUNTER_FULL : unsigned(g_counter_lgth-1 downto 0);
signal s_counter : unsigned(g_counter_lgth-1 downto 0);
constant c_COUNTER_FULL : unsigned(g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned(g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
c_COUNTER_FULL <= (others => '1');
---------------------------------------------------------------------------------------------------
-- Synchronous process Incr_Counter
......
wf_inputs_synchronizer.vhd
View file @ faa2b429
......@@ -27,10 +27,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit synchronises all the input signals with to the uclk or wb_clk, to be used
-- by all the other units of nanoFIP; a set of 3ple buffers is used for each signal.
-- Note: Because of the 3ple buffering, transitions on input signals of less than 2
-- clk cycles are not considered.
--! @brief The unit synchronizes the nanoFIP's input signals to the uclk or the wb_clk;
--! a set of 3 registers is used for each signal.
--! Notes : Regarding the WISHBONE interface, only the control signals STB, CYC, WE are
--! synchronized.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......@@ -60,6 +60,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! in nanoFIP input fd_rxd we also see the nanoFIP output fd_txd; in order to
--! get only the receiver's data, we filter fd_rxd with the reception activity
--! detection fd_rxcdn.
--! 1/2011 v0.021 EG wb_rst_a_i renamed to wb_rst_i
--
---------------------------------------------------------------------------------------------------
--
......@@ -84,13 +85,13 @@ entity WF_inputs_synchronizer is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
uclk_i : in std_logic; --! 40 MHz clock
nostat_a_i : in std_logic;
rstin_a_i : in std_logic;
slone_a_i : in std_logic;
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP WorldFIP Settings
c_id_a_i : in std_logic_vector(3 downto 0);
......@@ -100,9 +101,11 @@ entity WF_inputs_synchronizer is
subs_a_i : in std_logic_vector(7 downto 0);
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_clk_i : in std_logic; --! WISHBONE clock
wb_rst_i : in std_logic; --! WISHBONE reset, includes also the PowerOnReset
--! Note: wb_rst is not registered, to comply
--! with WISHBONE rule 3.15
wb_cyc_a_i : in std_logic;
wb_rst_a_i : in std_logic; --! WISHBONE reset
wb_stb_a_i : in std_logic;
wb_we_a_i : in std_logic;
......@@ -135,10 +138,9 @@ entity WF_inputs_synchronizer is
-- nanoFIP User Interface, WISHBONE Slave
wb_cyc_o : out std_logic;
wb_stb_o : out std_logic;
wb_stb_r_edge_o : out std_logic;
wb_stb_r_edge_p_o : out std_logic; --! 1 wb_clk-wide pulse on the rising edge of a STB_I
wb_we_o : out std_logic;
-- nanoFIP User Interface, NON WISHBONE
slone_dati_o : out std_logic_vector(15 downto 0);
var1_access_o : out std_logic;
......@@ -183,7 +185,7 @@ begin
---------------------------------------------------------------------------------------------------
RSTIN_synchronisation_with_uclk: process (uclk_i)
RSTIN_synchronization_with_uclk: process (uclk_i)
begin
if rising_edge (uclk_i) then
s_u_rst_d3 <= s_u_rst_d3 (1 downto 0) & rstin_a_i;
......@@ -194,7 +196,7 @@ begin
---------------------------------------------------------------------------------------------------
User_interf_general_signals_synchronisation: process (uclk_i)
User_interf_general_signals_synchronization: process (uclk_i)
begin
if rising_edge (uclk_i) then
......@@ -214,7 +216,7 @@ begin
---------------------------------------------------------------------------------------------------
FIELDRIVE_inputs_synchronisation: process (uclk_i)
FIELDRIVE_inputs_synchronization: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
......@@ -245,7 +247,7 @@ begin
---------------------------------------------------------------------------------------------------
VAR_ACC_synchronisation: process (uclk_i)
VAR_ACC_synchronization: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
......@@ -282,10 +284,10 @@ begin
---------------------------------------------------------------------------------------------------
WISHBONE_inputs_synchronisation: process (wb_clk_i)
WISHBONE_inputs_synchronization: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if wb_rst_a_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
if wb_rst_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
s_wb_stb_d1 <= '0';
s_wb_stb_d2 <= '0';
s_wb_stb_d3 <= '0';
......@@ -317,7 +319,7 @@ begin
wb_cyc_o <= s_wb_cyc_d3;
wb_we_o <= s_wb_we_d3;
wb_stb_o <= s_wb_stb_d3;
wb_stb_r_edge_o <= (not s_wb_stb_d4) and s_wb_stb_d3;
wb_stb_r_edge_p_o <= (not s_wb_stb_d4) and s_wb_stb_d3;
--------------------------------------------------------------------------------------------------
......@@ -342,7 +344,7 @@ begin
--------------------------------------------------------------------------------------------------
WorldFIP_Settings_synchronisation: process (uclk_i)
WorldFIP_Settings_synchronization: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
......
wf_manch_code_viol_check.vhd
View file @ faa2b429
......@@ -22,7 +22,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_rx_manch_code_check --
-- WF_rx_manch_code_check --
-- --
---------------------------------------------------------------------------------------------------
--
......@@ -35,9 +35,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Remark: We refer to
--! o a significant edge : for the edge of a manch. encoded bit
--! (bit 0: __|--, bit 1: --|__)
--!
--! o the sampling of a manch. bit : for the moments when a manch. encoded bit
--! should be sampled, before and after a significant edge. The period of this
--! sampling is that of the half-bit-clock.
--!
--! o the sampling of a bit : for the sampling of only the 1st part,
--! before the transition (the period is the double of the manch. sampling)
--!
......@@ -122,11 +124,10 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Check_Code_Violations: in order to check for code violations, the
--! input signal is delayed by half-bit-clock period (serial_input_signal_d).
--! The signal check_code_viol_p is a pulse occuring 2 uclk periods after a manch. edge is expected.
--! As the following drawing roughly indicates, a violation exists if the signal and its delayed
--! version are identical on the check_code_viol_p moments.
--! input signal is delayed for 1 half-bit-clock period.
--! The signal check_code_viol_p is a pulse occurring 2 uclk periods after a manch. edge is expected.
--! A violation exists if the signal and its delayed version are identical on the
--! check_code_viol_p moments.
-- 0 V- 1
-- rxd_filtered : __|--|____|--|__
-- serial_input_signal_d : __|--|____|--|__
......@@ -154,6 +155,7 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment
......
wf_manch_encoder.vhd
View file @ faa2b429
......@@ -25,10 +25,10 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! @brief Encoding of a word to its Manchester 2 (manch.) equivalent.
--! This code ensures that there is one transition for each bit.
--! bit : "0" "1"
--! manch. encoded : "0 1" "1 0"
--! scheme : _|- -|_
--! The manch. encoding ensures that there is one transition for each bit.
--! o bit : "0" "1"
--! o manch. encoded : "0 1" "1 0"
--! o scheme : _|- -|_
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
......@@ -38,7 +38,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @date 10/12/2010
--
--
--! @version v0.02
--! @version v0.01
--
--
--! @details \n
......@@ -52,8 +52,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG 1st version \n
--! -> 12/2010 v0.02 EG cleaned-up, commented \n
--! -> 12/2010 v0.01 EG cleaned-up, commented (all 3 lines!) \n
--!
--
---------------------------------------------------------------------------------------------------
......
wf_model_constr_decoder.vhd
View file @ faa2b429
......@@ -26,8 +26,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name WF_model_constr_decoder
--
--
--! @brief Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID.
--! The output S_ID0 is a clock with period the double of uclk's period and the S_ID1
......@@ -43,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--! @date 06/10/2010
--! @date 21/01/2011
--
--
--! @version v0.03
......@@ -67,12 +65,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! "for" loop replaced with signals concatenation;
--! Counter is of c_RELOAD_MID_CID bits; Code cleaned-up \n
--! -> 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed;
--! separate processes for counter and the rest
--! counter unit instantiated
--! -> 01/2011 v0.031 EG loading aftern the 2nd cycle (no need for 3)
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--!
--! -> select_id_o not the output of a dff:-s
--
---------------------------------------------------------------------------------------------------
......@@ -138,8 +137,8 @@ begin
--! of all the odd bits of M_ID & C_ID are loaded on the registers s_model_stage1/ s_constr_stage1
--! and on the second uclk tick, the values of the odd bits move to the registers s_model_stage2/
--! s_constr_stage2, giving place to all the even bits to be loaded to the s_model_stage1/
--! s_constr_stage1. On a third uclk tick the loaded odd and even values are combined to give
--! the decoded outputs (model_id_dec_o & constr_id_dec_o).
--! s_constr_stage1. The loaded odd and even values are combined after the 2 periods to give the
--! decoded outputs model_id_dec_o & constr_id_dec_o.
Model_Constructor_Decoder: process (uclk_i)
begin
......@@ -154,23 +153,24 @@ begin
else
s_model_stage1 <= model_id_i; -- after 2 uclk ticks stage1 keeps the even bits
s_model_stage2 <= s_model_stage1; -- and stage2 the odd ones
s_model_stage2 <= s_model_stage1; -- after 2 uclk ticks stage1 keeps the even bits
s_model_stage1 <= model_id_i; -- and stage2 the odd ones
s_constr_stage2 <= s_constr_stage1;
s_constr_stage1 <= constr_id_i; -- same for the constructor
s_constr_stage1 <= constr_id_i; -- same for the constructor
s_constr_stage2 <= s_constr_stage1;
if s_counter="10" then
if s_counter = "01" then
model_id_dec_o <= s_model_stage2(3) & s_model_stage1(3) & -- putting together
s_model_stage2(2) & s_model_stage1(2) & -- odd and even bits
s_model_stage2(1) & s_model_stage1(1) &
s_model_stage2(0) & s_model_stage1(0);
constr_id_dec_o <= s_constr_stage1(3) & s_constr_stage2(3) &
s_constr_stage1(2) & s_constr_stage2(2) &
s_constr_stage1(1) & s_constr_stage2(1) &
s_constr_stage1(0) & s_constr_stage2(0);
constr_id_dec_o <= s_constr_stage2(3) & s_constr_stage1(3) &
s_constr_stage2(2) & s_constr_stage1(2) &
s_constr_stage2(1) & s_constr_stage1(1) &
s_constr_stage2(0) & s_constr_stage1(0);
end if;
end if;
......@@ -185,7 +185,7 @@ begin
generic map(g_counter_lgth => 2)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
nfip_rst_i => nfip_rst_i,
reinit_counter_i => '0',
incr_counter_i => '1',
-----------------------------------------
......@@ -197,7 +197,7 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Concurrent signal assignment for the output select_id_o
select_id_o <= ((not s_counter(0)) & s_counter(0)); -- 2 opposite clocks generated using
select_id_o <= ((not s_counter(0)) & s_counter(0));-- 2 opposite clocks generated using
-- the LSB of the counter
-- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_
-- S_ID0 : |----|____|----|____|----|___
......
wf_package.vhd
View file @ faa2b429
......@@ -49,7 +49,8 @@ use ieee.numeric_std.all;
--! -> 8/2010 v0.01 EG byte_array of all vars cleaned_up (ex: subs_i removed) \n
--! -> 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of
--! std_logic_vector(9 downto 0) to simplify calculations; cleaning-up
--! -> 11/1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs
--! -> 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs
--! added DualClkRam
--
---------------------------------------------------------------------------------------------------
--
......@@ -348,7 +349,7 @@ package WF_package is
wb_clk_i : in std_logic;
nfip_rst_i : in std_logic;
rstin_a_i : in std_logic;
wb_rst_a_i : in std_logic;
wb_rst_i : in std_logic;
slone_a_i : in std_logic;
nostat_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
......@@ -380,7 +381,7 @@ package WF_package is
wb_cyc_o : out std_logic;
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_stb_r_edge_o : out std_logic;
wb_stb_r_edge_p_o : out std_logic;
var1_access_o : out std_logic;
var2_access_o : out std_logic;
var3_access_o : out std_logic;
......@@ -412,7 +413,7 @@ end component WF_inputs_synchronizer;
-----------------------------------------------------------------
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
crc_wrong_p_o : out std_logic;
crc_or_manch_wrong_p_o : out std_logic;
fss_crc_fes_manch_ok_p_o : out std_logic;
fss_received_p_o : out std_logic;
rst_rx_osc_o : out std_logic
......@@ -529,7 +530,7 @@ end component WF_inputs_synchronizer;
byte_ready_p_o : out std_logic;
fss_received_p_o : out std_logic;
nfip_status_r_tler_o : out std_logic;
crc_wrong_p_o : out std_logic;
crc_or_manch_wrong_p_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic;
fss_crc_fes_manch_ok_p_o : out std_logic;
......@@ -640,7 +641,7 @@ end component WF_production;
nostat_i : in std_logic;
tx_byte_request_p_i : in std_logic;
rx_fss_received_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic;
rx_crc_or_manch_wrong_p_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
......@@ -664,12 +665,14 @@ end component WF_production;
rstin_i : in std_logic;
rstpon_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
rst_i : in std_logic;
var_i : in t_var;
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
---------------------------------------------------------------
rston_o : out std_logic;
wb_rst_o : out std_logic;
nFIP_rst_o : out std_logic;
rston_o : out std_logic;
fd_rstn_o : out std_logic
---------------------------------------------------------------
);
......@@ -694,6 +697,26 @@ end component WF_production;
end component WF_DualClkRAM_clka_rd_clkb_wr;
---------------------------------------------------------------------------------------------------
component DualClkRam is
port(
CLKA : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
DINA : in std_logic_vector (7 downto 0);
RWA : in std_logic;
CLKB : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DINB : in std_logic_vector (7 downto 0);
RWB : in std_logic;
RESETn : in std_logic;
--------------------------------------------------------------------------
DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector (7 downto 0)
--------------------------------------------------------------------------
);
end component DualClkRam;
---------------------------------------------------------------------------------------------------
component WF_crc
generic (c_GENERATOR_POLY_length : natural := 16);
......
wf_prod_bytes_retriever.vhd
View file @ faa2b429
This diff is collapsed.
wf_prod_bytes_to_dati.vhd
View file @ faa2b429
......@@ -29,7 +29,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @brief Unit responsible for the sampling of the DAT_I bus in stand-alone operation.
--! Following to the functional specs page 15, in stand-alone mode, the nanoFIP
--! samples the data on the first clock cycle after the deassertion of VAR3_RDY.
--! samples the data on the first clock cycle after the de-assertion of VAR3_RDY.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......@@ -47,6 +47,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_engine_control \n
--! WF_prod_permit \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -89,13 +90,14 @@ entity WF_prod_bytes_from_dati is
-- nanoFIP User Interface, NON-WISHBONE
slone_data_i : in std_logic_vector (15 downto 0); --! input data bus for stand-alone mode
-- (synchronised with uclk)
-- (synchronized with uclk)
-- Signals from the WF_engine_control unit
byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes
byte_index_i : in std_logic_vector (7 downto 0); --! index of the byte to be produced
-- Signals from the WF_prod_permit unit
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
-- OUTPUTS
-- Signal to the WF_prod_bytes_retriever
slone_byte_o : out std_logic_vector (7 downto 0) --! sampled byte to be sent
......@@ -119,9 +121,9 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Sample_DAT_I_bus: the sampling of the DAT_I bus in stand-alone mode
--! has to take place on the first clock cycle after the de-assertion of VAR3_RDY.
--! Note: Since slone_data_i is the triply buffered version of the bus DAT_I (for synchronisation),
--! Note: Since slone_data_i is the triply registered version of the bus DAT_I (for synchronization),
--! the signal VAR3_RDY has to be (internally) delayed for 3 uclk cycles too, before the sampling;
--! the 4th delay is added in order to achieve the sampling 1 uclk AFTER the de-assertion.
--! the 4th delay is added in order to have the sampling 1 uclk AFTER the de-assertion.
Sample_DAT_I_bus: process (uclk_i)
begin
......@@ -145,6 +147,7 @@ Sample_DAT_I_bus: process (uclk_i)
slone_byte_o <= s_sampled_data(7 downto 0) when byte_index_i = c_1st_DATA_BYTE_INDEX
else s_sampled_data(15 downto 8);
end architecture rtl;
--=================================================================================================
-- architecture end
......
wf_prod_data_lgth_calc.vhd
View file @ faa2b429
......@@ -22,21 +22,28 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_data_lgth_calc --
-- WF_prod_data_lgth_calc --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Calculation of the total amount of bytes, after the FSS and before the FCS, that
--! have to be transferreed when a variable is produced. In detail, the calculation
--! takes into account the: RP_DAT.Control, RP_DAT.Data.PDU_TYPE, RP_DAT.Data.Length,
--! RP_DAT.Data.MPS_status, RP_DAT.Data.nanoFIP_status bytes as well as the user-data
--! bytes described by the P3_LGTH.
--! @brief Calculation of the amount of bytes, after the FSS and before the FCS, that have
--! to be transferred when a variable is produced (var_presence, var_identif, var_3).
--! In detail the unit adds:
--! o 1 byte RP_DAT.Control,
--! o 1 byte RP_DAT.Data.PDU_TYPE,
--! o 1 byte RP_DAT.Data.Length,
--! o 2-124 bytes RP_DAT.Data.User_Data, defined by the "nanoFIP User Interface,General
--! signal" SLONE and the "nanoFIP WorldFIP Settings" input P3_LGTH
--! o 1 byte RP_DAT.Data.MPS_status, if applicable (only in var_3)
--! o 1 byte RP_DAT.Data.nanoFIP_status, only for a var_3, if the "nanoFIP User
--! Interface General signal" NOSTAT is negated.
--!
--! ------------------------------------------------------------------------------------
--! Reminder
--!
--! Reminder:
--!
--! Produced RP_DAT frame structure :
--! ||--------------------- Data ---------------------||
--! ___________ ______ _______ ______ _________________ _______ _______ ___________ _______
--! |____FSS____|_Ctrl_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__|
--!
......@@ -125,9 +132,9 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief: Combinatorial process data_length_calcul: calculation of the amount of bytes, after the
--! FSS and before the FCS, that have to be transferreed when a variable is produced. In the case
--! FSS and before the FCS, that have to be transferred when a variable is produced. In the case
--! of the presence and the identification variables, the data length is predefined in the WF_package.
--! In the case of a var3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation.
--! In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the calculation.
data_length_calcul: process (var_i, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i)
begin
......@@ -153,7 +160,7 @@ begin
when var_3 =>
-- data length calculation according to the operational mode (memory or stand-alone)
-- in slone mode 2 bytes of user-data are produced(independantly of p3_lgth)
-- in slone mode 2 bytes of user-data are produced(independently of P3_LGTH)
-- to these there should be added: 1 byte Control
-- 1 byte PDU_TYPE
-- 1 byte Length
......@@ -172,23 +179,23 @@ begin
if nostat_i = '1' then -- 6 bytes (counting starts from 0)
s_prod_data_length <= to_unsigned(5, s_prod_data_length'length);
else -- 7 bytes (counting starts from 0)
else -- 7 bytes
s_prod_data_length <= to_unsigned(6, s_prod_data_length'length);
end if;
else
if nostat_i = '0' then
s_prod_data_length <= s_p3_length_decoded + 4; -- (counting starts from 0)
s_prod_data_length <= s_p3_length_decoded + 4;
else
s_prod_data_length <= s_p3_length_decoded + 3; -- (counting starts from 0)
s_prod_data_length <= s_p3_length_decoded + 3;
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_1 | var_2 | var_rst => -- to avoid Warnings from Synthesiser
when var_1 | var_2 | var_rst =>
s_prod_data_length <= (others => '0');
when others =>
......@@ -196,6 +203,7 @@ begin
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment for the output
prod_data_length_o <= std_logic_vector (s_prod_data_length);
......
wf_production.vhd
View file @ faa2b429
This diff is collapsed.
wf_reset_unit.vhd
View file @ faa2b429
This diff is collapsed.
wf_rx_deglitcher.vhd
View file @ faa2b429
......@@ -26,15 +26,17 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! @brief The unit applies a glitch filter; it follows each Manchester 2 encoded bit (manch.)
--! of the "nanoFIP FIELDRIVE" input signal fd_rxd (synchronized with uclk), counts the
--! of the "nanoFIP FIELDRIVE" input signal FD_RXD (synchronized with uclk), counts the
--! number of zeros and ones throughout its duration and finally outputs the majority.
--! The output deglitched signal is one half-bit-clock period later than the input.
--!
--! Remark: We refer to
--! o a significant edge : for the edge of a manch. encoded bit
--! (bit 0: _|-, bit 1: -|_)
--!
--! o the sampling of a manch. bit : for the moments when a manch. encoded bit
--! should be sampled, before and after a significant edge
--!
--! o the sampling of a bit : for the sampling of only the 1st part,
--! before the transition.
--!
......@@ -58,7 +60,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @details
--
--! \n<b>Dependencies:</b>\n
--! WF_tx-_rx_osc \n
--! WF_tx_rx_osc \n
--! WF_reset_unit \n
--
--
......@@ -201,7 +203,7 @@ Detect_f_edge_rxd_filtered: process (uclk_i)
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
-- Concurrent signal assignments
rxd_filtered_f_edge_p_o <= s_rxd_filtered_buff(1) and (not s_rxd_filtered_buff(0));
......
wf_rx_deserializer.vhd
View file @ faa2b429
......@@ -34,15 +34,24 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! The unit is also responsible for the identification of the FSS and FES fields of
--! ID_DAT and RP_DAT frames and the verification of their FCS and Manchester 2 (manch.)
--! encoding.
--! At the end of a frame (FES detection) either the fss_crc_fes_manch_ok_p_o pulse
--! is assserted, indicating a frame with with correct FSS, CRC, FES and manch. encoding
--! or the pulse crc_or_manch_wrong_p_o is asserted indicating an error on the CRC or
--! manch. encoding.
--! If a FES is not detected after the reception of more than 8 bytes for an ID_DAT or
--! more than 130 bytes for a RP_DAT the unit is reset by the WF_engine_control.
--!
--! Remark: We refer to
--! o a significant edge : for the edge of a manch. encoded bit
--! (bit 0: _|-, bit 1: -|_)
--! (bit 0: _|-, bit 1: -|_).
--!
--! o a transition : for the moment in between two adjacent bits,
--! that may or may not result in an edge (eg. a 0 followed by a 0 will give an edge
--! _|-|_|-, but a 0 followed by a 1 will not _|--|_ ).
--!
--! o the sampling of a manch. bit : for the moments when a manch. encoded bit
--! should be sampled, before and after a significant edge
--! should be sampled, before and after a significant edge.
--!
--! o the sampling of a bit : for the sampling of only the 1st part,
--! before the transition.
--!
......@@ -54,14 +63,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! sample_manch_bit_p : ^ ^ ^ ^
--! sample_bit_p : ^ ^ (this sampling will give the 0 and the 1)
--!
--! ------------------------------------------------------------------------------------
--!
--! Reminder:
--!
--! Consumed RP_DAT frame structure :
--! _______ _______ ______ _______ ______ ________________ _______ ___________ _______
--! |__PRE__|__FSD__|_Ctrl_||__PDU__|_LGTH_|_..ApplicData.._|__MPS__||____FCS____|__FES__|
--!
--! ------------------------------------------------------------------------------------
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
......@@ -71,7 +79,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @date 9/12/2010
--
--
--! @version v0.03
--! @version v0.04
--
--
--! @details \n
......@@ -106,6 +114,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! code(more!)cleaned-up
--! -> 01/2011 v0.04 EG changed way of detecting the FES to be able to detect a FES even if
--! bytes with size different than 8 have preceeded.
--! crc_or_manch_wrong_p_o replaced the crc_wrong_p_o.
--
---------------------------------------------------------------------------------------------------
--
......@@ -166,7 +175,8 @@ entity WF_rx_deserializer is
--! correct FSS, FES, CRC and manch. encoding
-- Signal to the WF_production and the WF_engine_control units
crc_wrong_p_o : out std_logic; --! indication of a wrong CRC on a ID_DAT or RP_DAT
crc_or_manch_wrong_p_o : out std_logic; --! indication of a wrong CRC or manch. encoding on a
--! ID_DAT or RP_DAT; pulse after the FES detection
-- Signal to the WF_engine_control units
fss_received_p_o : out std_logic; --! pulse after the reception of a correct FSS (ID/RP)
......@@ -188,7 +198,7 @@ architecture rtl of WF_rx_deserializer is
fsd_field, switch_to_deglitched, data_fcs_fes_fields);
signal rx_st, nx_rx_st : rx_st_t;
signal s_manch_code_viol_p, s_CRC_ok_p, s_CRC_ok_p_d16 : std_logic;
signal s_manch_code_viol_p, s_CRC_ok_p, s_crc_ok_p_d15 : std_logic;
signal s_fsd_last_bit, s_fes_wrong_bit, s_sample_manch_bit_p_d1 : std_logic;
signal s_fes_detected_p : std_logic;
signal s_manch_not_ok, s_switching_to_deglitched : std_logic;
......@@ -200,7 +210,7 @@ architecture rtl of WF_rx_deserializer is
signal s_manch_r_edge_p, s_manch_f_edge_p : std_logic;
signal s_manch_bit_index, s_manch_bit_index_top : unsigned(3 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
signal s_arriving_fes : std_logic_vector (15 downto 0);
signal s_arriving_fes : std_logic_vector (15 downto 0);
signal s_CRC_ok_p_buff : std_logic_vector (14 downto 0);
--=================================================================================================
......@@ -224,7 +234,7 @@ architecture rtl of WF_rx_deserializer is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process Deserializer_FSM_Sync: storage of the current state of the FSM
Deserializer_FSM_Sync: process (uclk_i)
Deserializer_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
......@@ -338,7 +348,7 @@ architecture rtl of WF_rx_deserializer is
-- nanoFIP can receive ID_DATs of a predefined length of 8 bytes and RP_DATs of any length
-- (not predefined) up to 132 bytes (FSD+Ctrl+PDU_TYPE+LGTH+124 application_data+MPS+FCS+FES).
-- The WF_engine_control unit is following the amount of bytes being received and in case
-- their number overpasses the expected one, it activates the signal rst_rx_unit_p_i.
-- their number exceeds the expected one, it activates the signal rst_rx_unit_p_i.
-- Therefore, the Receiver_FSM stays in the data_fcs_fes_fields state until the arrival of a
-- correct FES, or until the arrival of a reset signal from the WF_engine_control.
......@@ -563,7 +573,7 @@ architecture rtl of WF_rx_deserializer is
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_fes_detected_p <= '1' when s_arriving_fes = (c_FES) and s_receiving_bytes = '1' else '0';
s_fes_detected_p <= '1' when s_arriving_fes = (c_FES) else '0'; -- 1 uclk-wide pulse
---------------------------------------------------------------------------------------------------
......@@ -658,7 +668,7 @@ architecture rtl of WF_rx_deserializer is
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_crc_ok_p_d16 <= s_CRC_ok_p_buff(14); -- pulse 1 half-bit-clock period long
s_crc_ok_p_d15 <= s_CRC_ok_p_buff(14); -- pulse 1 half-bit-clock period long
......@@ -678,9 +688,9 @@ architecture rtl of WF_rx_deserializer is
byte_o <= s_byte;
rst_rx_osc_o <= s_idle;
fss_received_p_o <= s_receiving_fsd and s_fsd_last_bit;
crc_wrong_p_o <= s_fes_detected_p and (not s_crc_ok_p_d16);
fss_crc_fes_manch_ok_p_o <= s_fes_detected_p and s_crc_ok_p_d16 and (not s_manch_not_ok);
fss_received_p_o <= s_receiving_fsd and s_fsd_last_bit;
crc_or_manch_wrong_p_o <= s_fes_detected_p and ((not s_crc_ok_p_d15) or (not s_manch_not_ok));
fss_crc_fes_manch_ok_p_o <= s_fes_detected_p and s_crc_ok_p_d15 and (not s_manch_not_ok);
end architecture rtl;
......
wf_rx_tx_osc.vhd
View file @ faa2b429
......@@ -25,8 +25,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name WF_rx_tx_osc
--
--! @brief Generation the clock signals needed for the receiver (WF_rx_deglitcher and
--! WF_rx_deserializer) and transmiter (WF_tx_serializer)\n
--!
......
wf_status_bytes_gen.vhd
View file @ faa2b429
This diff is collapsed.
wf_tx_serializer.vhd
View file @ faa2b429
This diff is collapsed.
wf_wb_controller.vhd
View file @ faa2b429
......@@ -35,7 +35,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 20/01/2011
--! @date 21/01/2011
--
--
--! @version v0.01
......@@ -47,15 +47,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! WF_production \n
--! WF_consumption \n
--
---------------------------------------------------------------------------------------------------
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! ->
--
--! -> 21/01/2011 v0.011 EG changed registering
--
---------------------------------------------------------------------------------------------------
--
......@@ -67,7 +66,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 1, 3, 4 of var_i(0 to 6) are unused" --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
......@@ -84,20 +83,22 @@ entity WF_wb_controller is
wb_rst_i : in std_logic; --! WISHBONE reset
wb_cyc_i : in std_logic; --! WISHBONE cycle
wb_stb_r_edge_p_i : in std_logic; --! rising edge on WISHBONE strobe
--! 1 wb-clk wide pulse
wb_we_i : in std_logic; --! WISHBONE write enable
wb_adr_id_i : in std_logic_vector (2 downto 0); --! 3 first bits of WISHBONE address
wb_adr_id_i : in std_logic_vector (2 downto 0);--! 3 first bits of WISHBONE address
-- OUTPUTS
-- Signal from the WF_production_unit
wb_ack_prod_p_o : out std_logic; --! response to a write cycle
-- latching moment of wb_dat_i
wb_ack_prod_p_o : out std_logic; --! response to a write cycle
-- latching moment of wb_dat_i
-- nanoFIP User Interface, WISHBONE Slave output
wb_ack_p_o : out std_logic --! WISHBONE acknowledge
-- response to master's strobe
wb_ack_p_o : out std_logic --! WISHBONE acknowledge
);
end entity WF_wb_controller;
......@@ -107,7 +108,7 @@ end entity WF_wb_controller;
--=================================================================================================
architecture rtl of WF_wb_controller is
signal s_wb_ack_write_p, s_wb_ack_read_p, s_wb_ack_write_p_d, s_wb_ack_read_p_d : std_logic;
signal s_wb_ack_write_p, s_wb_ack_read_p : std_logic;
begin
......@@ -123,6 +124,7 @@ begin
(wb_cyc_i = '1'))
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Generate_wb_ack_read_p: Generation of the wb_ack_read_p signal
--! (acknowledgement from WISHBONE Slave of the read cycle, as a response to the master's strobe).
......@@ -134,25 +136,24 @@ begin
(wb_cyc_i = '1'))
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Output_Register:
--!@brief Output_Register
WB_ACK: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then
s_wb_ack_read_p_d <= '0';
s_wb_ack_write_p_d <= '0';
wb_ack_p_o <= '0';
wb_ack_prod_p_o <= '0';
else
s_wb_ack_read_p_d <= s_wb_ack_read_p;
s_wb_ack_write_p_d <= s_wb_ack_write_p;
wb_ack_p_o <= s_wb_ack_read_p or s_wb_ack_write_p;
wb_ack_prod_p_o <= s_wb_ack_write_p;
end if;
end if;
end process;
wb_ack_p_o <= s_wb_ack_read_p_d or s_wb_ack_write_p_d;
wb_ack_prod_p_o <= s_wb_ack_write_p_d;
end architecture rtl;
--=================================================================================================
......
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