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Commit e1bd8403 authored by egousiou's avatar egousiou
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wf_cons_outcome: bug on var1/2_rdy generation corrected 

top level nanofip comments on structure updated

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@177 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 297713da
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nanofip.vhd
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wf_cons_outcome.vhd
View file @ e1bd8403
......@@ -84,6 +84,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 01/2010 v0.04 EG Unit WF_var_rdy_generator separated in WF_cons_outcome
--! (for var1_rdy,var2_rdy+var_rst outcome) & WF_prod_permit (for var3)
--! -> 02/2010 v0.05 EG Added here functionality of wf_cons_frame_validator
--! Bug on var1_rdy, var2_rdy generation corrected (the s_varX_received
--! was always set to 1!)
--
---------------------------------------------------------------------------------------------------
--
......@@ -156,9 +158,8 @@ end entity WF_cons_outcome;
--=================================================================================================
architecture rtl of WF_cons_outcome is
signal s_var_type_match, s_cons_frame_ok_p : std_logic;
signal s_var1_received, s_var2_received : std_logic;
signal s_rst_nfip_and_fd, s_assert_rston : std_logic;
signal s_cons_frame_ok_p : std_logic;
signal s_rst_nfip_and_fd, s_assert_rston : std_logic;
--=================================================================================================
......@@ -260,52 +261,38 @@ begin
if nfip_rst_i = '1' then
var1_rdy_o <= '0';
var2_rdy_o <= '0';
s_var1_received <= '0';
s_var2_received <= '0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
case var_i is
when var_1 => -- nanoFIP consuming
--------------------
var1_rdy_o <= '0'; -- while consuming a var_1, VAR1_RDY is 0
var2_rdy_o <= s_var2_received; -- VAR2_RDY retains its value
-- VAR1_RDY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if (var_i = var_1) and (s_cons_frame_ok_p = '1') then
-- only if the received var_1 RP_DAT frame is correct
var1_rdy_o <= '1'; -- the nanoFIP signals the user to retreive data
-- note: the signal var1_rdy_o remains asserted
-- until the beginning of the arrival of a new var_1
elsif (var_i = var_1) then
-- -- -- -- -- -- -- -- -- -- --
if s_cons_frame_ok_p = '1' then -- only if the received RP_DAT frame is correct,
-- the nanoFIP signals the user to retreive data
s_var1_received <= '1'; -- note:the signal s_var1_received remains asser-
-- ted after the end of the cons_frame_ok_p pulse
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_2 => -- nanoFIP consuming broadcast
------------------------------
var2_rdy_o <= '0'; -- while consuming a var_2, VAR2_RDY is 0
var1_rdy_o <= s_var1_received; -- VAR1_RDY retains its value
if slone_i = '0' and s_cons_frame_ok_p = '1' then
-- only in memory mode and if the received RP_DAT
s_var2_received <= '1'; -- frame is correct, the nanoFIP signals the user
-- to retreive data.
-- note:the signal s_var2_received remains asser-
end if; -- ted after the end of the cons_frame_ok_p pulse
var1_rdy_o <= '0'; -- while consuming a var_1, VAR1_RDY is 0
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- VAR2_RDY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if (var_i = var_2) and (s_cons_frame_ok_p = '1') and (slone_i = '0') then
-- only in memory mode and if the received var_2
var2_rdy_o <= '1'; -- RP_DAT is correct the nanoFIP signals the user
-- to retreive data
-- note: the signal var2_rdy_o remains asserted
-- until the beginning of the arrival of a new var_2
when others =>
elsif (var_i = var_2) then
var1_rdy_o <= s_var1_received;
var2_rdy_o <= s_var2_received;
var2_rdy_o <= '0'; -- while consuming a var_2, VAR2_RDY is 0
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
end case;
end if;
end if;
end process;
......
wf_engine_control.vhd
View file @ e1bd8403
......@@ -38,7 +38,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--!
--! ID_DAT frame structure :
--! ___________ ______ _______ ______ ___________ _______
--! |____FSS____|_Ctrl_||__Var__|_Subs_||____FCS____|__FES__|
--! |____FSS____|_Ctrl_||__Var__|_SUBS_||____FCS____|__FES__|
--!
--!
--! Produced RP_DAT frame structure :
......@@ -208,7 +208,7 @@ architecture rtl of WF_engine_control is
signal control_st, nx_control_st : control_st_t;
signal s_var_aux, s_var : t_var;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_id_dat_subs_byte : std_logic;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte : std_logic;
signal s_id_dat_frame_ok, s_cons_wait_FSS, s_consuming, s_prod_wait_turnar_time : std_logic;
signal s_producing, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
signal s_rst_rx_bytes_counter, s_inc_rx_bytes_counter, s_var_identified : std_logic;
......@@ -457,7 +457,6 @@ begin
---------------------------------
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
......@@ -472,7 +471,6 @@ begin
s_id_dat_ctrl_byte <= '1';
---------------------------------
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
......@@ -487,7 +485,6 @@ begin
---------------------------------
s_id_dat_var_byte <= '1';
---------------------------------
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
......@@ -500,9 +497,6 @@ begin
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
---------------------------------
s_id_dat_subs_byte <= '1';
---------------------------------
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
......@@ -515,7 +509,6 @@ begin
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
---------------------------------
s_id_dat_frame_ok <= '1';
---------------------------------
......@@ -530,7 +523,6 @@ begin
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
---------------------------------
s_prod_wait_turnar_time <= '1';
......@@ -545,7 +537,6 @@ begin
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
---------------------------------
......@@ -560,7 +551,6 @@ begin
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
......@@ -575,7 +565,6 @@ begin
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
......@@ -592,7 +581,6 @@ begin
---------------------------------
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
......@@ -649,7 +637,7 @@ begin
--! being received by the WF_rx_deserializer unit. The same counter is used for the bytes of an
--! ID_DAT frame or a consumed RP_DAT frame (that is why the name of the counter is s_rx_bytes_c
--! and not s_cons_bytes_c!)
--! Regarding an ID_DAT frame : the FSS,Control, var and subs bytes are being followed by the state
--! Regarding an ID_DAT frame : the FSS,Control, var and SUBS bytes are being followed by the state
--! machine and the counter is used for the counting of the bytes from then on until the arrival
--! of a FES. Therefore, the counter is reset at the "id_dat_subs_byte" state and counts bytes
--! following the "rx_byte_ready_p_i" pulse in the "id_dat_frame_ok" state.
......@@ -857,39 +845,39 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue then
s_var_aux <= var_identif;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).broadcast;
s_var_aux <= var_identif;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue then
s_var_aux <= var_1;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_1_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_1_INDEX).broadcast;
s_var_aux <= var_1;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_1_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_1_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue then
s_var_aux <= var_2;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_2_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_2_INDEX).broadcast;
s_var_aux <= var_2;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_2_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_2_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue then
s_var_aux <= var_3;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_3_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_3_INDEX).broadcast;
s_var_aux <= var_3;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_3_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_3_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue then
s_var_aux <= var_rst;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_RST_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_RST_INDEX).broadcast;
s_var_aux <= var_rst;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_RST_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_RST_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
else
s_var_aux <= var_whatever;
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
else
s_var_aux <= var_whatever;
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
end if;
......@@ -905,7 +893,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment (needed by the FSM)
-- Concurrent signal assignment (used by the FSM)
s_var_identified <= '1' when rx_byte_i = c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue or
......
wf_model_constr_decoder.vhd
View file @ e1bd8403
......@@ -112,7 +112,6 @@ end entity WF_model_constr_decoder;
--=================================================================================================
architecture rtl of WF_model_constr_decoder is
signal s_counter_is_full : std_logic;
signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0);
......@@ -179,10 +178,10 @@ begin
uclk_i => uclk_i,
reinit_counter_i => nfip_rst_i,
incr_counter_i => '1',
-----------------------------------------
counter_o => s_counter,
counter_is_full_o => s_counter_is_full);
-----------------------------------------
counter_is_full_o => open,
-----------------------------------------
counter_o => s_counter);
-----------------------------------------
---------------------------------------------------------------------------------------------------
......
wf_package.vhd
View file @ e1bd8403
......@@ -236,16 +236,16 @@ package WF_package is
constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) :=
(c_31K25_INDEX => (turnaround => integer (480000.0 / c_QUARTZ_PERIOD),
silence => integer (5160000.0 / c_QUARTZ_PERIOD)),
silence => integer (4096000.0 / c_QUARTZ_PERIOD)),
c_1M_INDEX => (turnaround => integer (14000.0 / c_QUARTZ_PERIOD),
silence => integer (150000.0 / c_QUARTZ_PERIOD)),
c_2M5_INDEX => (turnaround => integer (6000.0 / c_QUARTZ_PERIOD),
silence => integer (100000.0 / c_QUARTZ_PERIOD)),
silence => integer (96000.0 / c_QUARTZ_PERIOD)),
c_RESERVE_INDEX => (turnaround => integer (480000.0 /C_QUARTZ_PERIOD),
silence => integer (5160000.0 /C_QUARTZ_PERIOD)));
silence => integer (4096000.0 /C_QUARTZ_PERIOD)));
......
wf_rx_deglitcher.vhd
View file @ e1bd8403
......@@ -103,7 +103,6 @@ architecture Behavioral of WF_rx_deglitcher is
signal s_rxd_filtered, s_rxd_filtered_d1 : std_logic;
signal s_rxd_filtered_r_edge_p : std_logic;
signal s_rxd_filtered_f_edge_p : std_logic;
signal s_fd_rxd_no_activity : std_logic;
signal s_deglitch_c : unsigned (3 downto 0);
signal s_fd_rxd_synch : std_logic_vector (1 downto 0);
......
wf_rx_osc.vhd
View file @ e1bd8403
......@@ -126,8 +126,8 @@ end entity WF_rx_osc;
--=================================================================================================
architecture rtl of WF_rx_osc is
signal s_period_c, s_period, s_jitter : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_half_period, s_one_forth_period : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_period_c, s_period, s_margin : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_half_period : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_reinit_counter, s_counter_is_full : std_logic;
signal s_adjac_bits_window, s_signif_edge_window : std_logic;
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
......@@ -144,8 +144,8 @@ begin
s_counter_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator
s_half_period <= s_period srl 1; -- 1/2 s_period
s_one_forth_period <= s_period srl 2; -- 1/4 s_period
s_jitter <= s_period srl 3; -- jitter defined as 1/8 s_period
s_margin <= s_period srl 3; -- margin for jitter defined
-- as 1/8 s_period
---------------------------------------------------------------------------------------------------
......@@ -176,7 +176,8 @@ begin
-- if the rx_osc_rst_i is active or
-- if an edge is detected in the expected window or
-- if it fills up
s_reinit_counter <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i) or s_counter_is_full;
s_reinit_counter <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i)
or s_counter_is_full;
......@@ -216,7 +217,7 @@ begin
-- regarding significant edges:
-- looking for a significant edge inside the corresponding window
if (s_signif_edge_window = '1') and (fd_rxd_edge_p_i = '1') and (s_signif_edge_found = '0') then
if (s_signif_edge_window='1') and (fd_rxd_edge_p_i='1') and (s_signif_edge_found='0') then
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_signif_edge_found <= '1'; -- indication that the edge was found
......@@ -224,7 +225,7 @@ begin
-- if a significant edge is not found where expected (code violation), the rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
elsif (s_signif_edge_found = '0') and (s_period_c = s_jitter) then
elsif (s_signif_edge_found = '0') and (s_period_c = s_margin) then
s_manch_clk <= not s_manch_clk;
s_adjac_bits_edge_found <= '0'; -- re-initialization before the
......@@ -246,7 +247,7 @@ begin
-- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right
-- after the end of it
elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_jitter) then
elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_margin) then
s_manch_clk <= not s_manch_clk;
s_bit_clk <= not s_bit_clk;
......@@ -274,17 +275,17 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Concurrent signal assignments: creation of the windows where
--! "significant edges" and "adjacent bits transitions" are expected on the input signal.
--! o s_signif_edge_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
--! o s_signif_edge_window : extends s_margin uclk ticks before and s_margin uclk ticks after
--! the completion of a period, where significant edges are expected.
--! o s_adjac_bits_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
--! o s_adjac_bits_window : extends s_margin uclk ticks before and s_margin uclk ticks after
--! the middle of a period, where transitions between adjacent bits are expected.
s_signif_edge_window <= '1' when ((s_period_c < s_jitter) or
(s_period_c > s_period-1 - s_jitter-1))
s_signif_edge_window <= '1' when ((s_period_c < s_margin) or
(s_period_c > s_period-1 - s_margin-1))
else '0';
s_adjac_bits_window <= '1' when ((s_period_c >= s_half_period-s_jitter-1) and
(s_period_c < s_half_period+s_jitter))
s_adjac_bits_window <= '1' when ((s_period_c >= s_half_period-s_margin-1) and
(s_period_c < s_half_period+s_margin))
else '0';
......
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