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nanoFIP - Gateware
Commit d24b13cd authored by egousiou's avatar egousiou
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aux JTAG version with test points 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@229 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent d96c6aaa
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Showing with 78 additions and 32 deletions
nanofip.vhd
View file @ d24b13cd
......@@ -279,13 +279,14 @@ entity nanofip is
-- User Interface, JTAG Controller
TP39 : out std_logic;
TP10 : out std_logic;
TP11 : out std_logic;
TP12 : out std_logic;
TP13 : out std_logic;
TP14 : out std_logic;
TP15 : out std_logic;
TP16 : out std_logic;
TP39 : out std_logic;
jc_tms_o : out std_logic;
jc_tdi_o : out std_logic;
......@@ -339,7 +340,7 @@ architecture struc of nanofip is
signal s_jc_mem_adr_rd : std_logic_vector (8 downto 0);
signal s_jc_tdo_byte : std_logic_vector (7 downto 0);
signal s_jc_tdi_o, s_jc_tms_o, s_jc_tck_o, s_fd_txd_o : std_logic;
signal s_jc_tdi_o, s_jc_tms_o, s_jc_tck_o, s_fd_txd_o, s_fd_rstn_o : std_logic;
--=================================================================================================
......@@ -366,7 +367,7 @@ begin
nFIP_rst_o => s_nfip_intern_rst,
wb_rst_o => s_wb_rst,
rston_o => rston_o,
fd_rstn_o => fd_rstn_o);
fd_rstn_o => s_fd_rstn_o);
-------------------------------------------------------------
......@@ -420,6 +421,12 @@ begin
rx_byte_ready_p_o => s_rx_byte_ready_p,
rx_fss_crc_fes_ok_p_o => s_rx_fss_crc_fes_ok_p,
rx_fss_received_p_o => s_rx_fss_received_p,
TP14 => TP14,
TP15 => TP15,
TP16 => TP16,
TP39 => TP39,
rx_crc_wrong_p_o => s_rx_crc_wrong_p);
-------------------------------------------------------------
......@@ -509,13 +516,18 @@ begin
jc_mem_adr_rd_o => s_jc_mem_adr_rd);
-----------------------------------------------------------------
TP39 <= jc_tdo_i;
TP10 <= s_jc_tms_o;
TP11 <= s_jc_tdi_o;
TP12 <= s_jc_tck_o;
TP13 <= s_rx_crc_wrong_p;
TP14 <= s_rx_fss_received_p;
TP15 <= s_rx_fss_crc_fes_ok_p;
-- TP39 <= jc_tdo_i;
TP10 <= fd_wdgn_i; --s_jc_tck_o;--s_jc_tms_o;
TP11 <= not (s_fd_rstn_o);-- s_jc_tdi_o;
TP12 <= s_nfip_intern_rst;--s_rx_crc_wrong_p;--s_jc_tck_o;
TP13 <= fd_txer_i; --s_rx_crc_wrong_p;
-- TP14 <= s_rx_fss_received_p;
-- TP15 <= s_rx_fss_crc_fes_ok_p;
fd_rstn_o <= s_fd_rstn_o;
jc_tms_o <= s_jc_tms_o;
jc_tdi_o <= s_jc_tdi_o;
jc_tck_o <= s_jc_tck_o;
......
wf_cons_bytes_processor.vhd
View file @ d24b13cd
......@@ -491,7 +491,7 @@ end process;
s_cons_lgth_byte <= (others => '0');
else
if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) or (var_i = var_jc1)then -- only for consumed vars
if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) or (var_i = var_jc1) then -- only for consumed vars
if (byte_index_i = c_CTRL_BYTE_INDEX) and (byte_ready_p_i='1') then
cons_ctrl_byte_o <= byte_i;
......
wf_engine_control.vhd
View file @ d24b13cd
......@@ -291,13 +291,13 @@ begin
when id_dat_control_byte =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= rst_rx;
nx_control_st <= idle; --rst_rx;
elsif (rx_byte_ready_p_i = '1') and (rx_byte_i(5 downto 0) = c_ID_DAT_CTRL_BYTE) then
nx_control_st <= id_dat_var_byte; -- check of ID_DAT Control byte
elsif rx_byte_ready_p_i = '1' then
nx_control_st <= rst_rx; -- byte different than the expected ID_DAT Control
nx_control_st <= idle;-- rst_rx; -- byte different than the expected ID_DAT Control
else
nx_control_st <= id_dat_control_byte;-- ID_DAT Control byte being arriving
......@@ -308,13 +308,13 @@ begin
when id_dat_var_byte =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= rst_rx;
nx_control_st <= idle;--rst_rx;
elsif (rx_byte_ready_p_i = '1') and (s_var_identified = '1') then
nx_control_st <= id_dat_subs_byte; -- check of the ID_DAT variable
elsif rx_byte_ready_p_i = '1' then
nx_control_st <= rst_rx; -- byte not corresponding to an expected variable
nx_control_st <= idle;--rst_rx; -- byte not corresponding to an expected variable
else
nx_control_st <= id_dat_var_byte; -- ID_DAT variable byte being arriving
......@@ -325,7 +325,7 @@ begin
when id_dat_subs_byte =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= rst_rx;
nx_control_st <= idle;--rst_rx;
elsif (rx_byte_ready_p_i = '1') and ((rx_byte_i = subs_i) or (s_broadcast_var = '1')) then
nx_control_st <= id_dat_frame_ok; -- check of the ID_DAT subscriber
......@@ -336,7 +336,7 @@ begin
-- also in stand-alone mode.
elsif rx_byte_ready_p_i = '1' then -- not the station's address, neither a broadcast
nx_control_st <= rst_rx;
nx_control_st <= idle;--rst_rx;
else
nx_control_st <= id_dat_subs_byte; -- ID_DAT subscriber byte being arriving
......@@ -347,7 +347,7 @@ begin
when id_dat_frame_ok =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= rst_rx;
nx_control_st <= idle;--rst_rx;
elsif (rx_fss_crc_fes_ok_p_i = '1') and (s_prod_or_cons = "10") then
nx_control_st <= produce_wait_turnar_time; -- ID_DAT frame ok! station has to produce
......@@ -356,7 +356,7 @@ begin
nx_control_st <= consume_wait_FSS; -- ID_DAT frame ok! station has to consume
elsif (s_rx_bytes_c > 2) then -- 3 bytes after the arrival of the subscriber
nx_control_st <= rst_rx; -- byte, a FES has not been detected
nx_control_st <= idle;--rst_rx; -- byte, a FES has not been detected
else
nx_control_st <= id_dat_frame_ok; -- CRC & FES bytes being arriving
......@@ -367,7 +367,7 @@ begin
when produce_wait_turnar_time =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= rst_rx;
nx_control_st <= idle;--rst_rx;
elsif s_time_c_is_zero = '1' then -- turnaround time passed
nx_control_st <= produce;
......@@ -387,7 +387,7 @@ begin
nx_control_st <= consume;
elsif s_time_c_is_zero = '1' then -- if the FSS of the consumed RP_DAT frame doesn't
nx_control_st <= rst_rx; -- arrive before the expiration of the silence time,
nx_control_st <= idle;--rst_rx; -- arrive before the expiration of the silence time,
-- the engine goes back to idle
else
nx_control_st <= consume_wait_FSS; -- counting silence time
......@@ -398,13 +398,13 @@ begin
when consume =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= rst_rx;
nx_control_st <= idle;--rst_rx;
elsif (rx_fss_crc_fes_ok_p_i = '1') or -- the cons frame arrived to the end, as expected
(rx_crc_wrong_p_i = '1') or -- FES detected but wrong CRC or wrong # bits
(s_rx_bytes_c > 130) then -- no FES detected after the max number of bytes
nx_control_st <= rst_rx; -- back to idle
nx_control_st <= idle;--rst_rx; -- back to idle
else
nx_control_st <= consume; -- consuming bytes
......@@ -990,9 +990,9 @@ begin
-- It also stays reset during a production session.
-- Note: the first 5 bytes of an ID_DAT and 2 bytes of an RP_DAT have been covered in the other
-- states of the Engine_Control_FSM and the s_rx_bytes_c starts counting from 0!
rx_rst_o <= '1' when s_rst_rx_p = '1' or
--(s_id_dat_frame_ok = '1'and (s_rx_bytes_c > 2)) or
--((s_consuming = '1') and (s_rx_bytes_c > 130)) or
rx_rst_o <= '1' when --s_rst_rx_p = '1' or
(s_id_dat_frame_ok = '1'and (s_rx_bytes_c > 2)) or
((s_consuming = '1') and (s_rx_bytes_c > 130)) or
(s_prod_wait_turnar_time = '1' or s_producing = '1') else '0';
-- indication of a consumed RP_DAT frame with more than 133 bytes
......
wf_fd_receiver.vhd
View file @ d24b13cd
......@@ -120,6 +120,11 @@ entity WF_fd_receiver is
rx_crc_wrong_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- wrong CRC; pulse upon FES detection
TP14 : out std_logic;
TP15 : out std_logic;
TP16 : out std_logic;
TP39 : out std_logic;
-- Signals to the WF_engine_control
rx_fss_received_p_o : out std_logic -- pulse upon FSS detection (ID/ RP_DAT)
......@@ -205,6 +210,12 @@ begin
fss_crc_fes_ok_p_o => rx_fss_crc_fes_ok_p_o,
rx_osc_rst_o => s_rx_osc_rst,
fss_received_p_o => rx_fss_received_p_o,
TP14 => TP14,
TP15 => TP15,
TP16 => TP16,
TP39 => TP39,
crc_wrong_p_o => rx_crc_wrong_p_o);
------------------------------------------------------
......
wf_package.vhd
View file @ d24b13cd
......@@ -387,6 +387,12 @@ package WF_package is
crc_wrong_p_o : out std_logic;
fss_crc_fes_ok_p_o : out std_logic;
fss_received_p_o : out std_logic;
TP14 : out std_logic;
TP15 : out std_logic;
TP16 : out std_logic;
TP39 : out std_logic;
rx_osc_rst_o : out std_logic);
-----------------------------------------------------------------
end component WF_rx_deserializer;
......@@ -504,6 +510,12 @@ package WF_package is
rx_byte_ready_p_o : out std_logic;
rx_fss_crc_fes_ok_p_o : out std_logic;
rx_fss_received_p_o : out std_logic;
TP14 : out std_logic;
TP15 : out std_logic;
TP16 : out std_logic;
TP39 : out std_logic;
rx_crc_wrong_p_o : out std_logic );
-----------------------------------------------------------------
end component WF_fd_receiver;
......
wf_rx_deserializer.vhd
View file @ d24b13cd
......@@ -163,6 +163,13 @@ entity WF_rx_deserializer is
-- Signal to the WF_engine_control unit
fss_received_p_o : out std_logic; -- pulse upon reception of a correct FSS (ID/RP)
TP14 : out std_logic;
TP15 : out std_logic;
TP16 : out std_logic;
TP39 : out std_logic;
-- Signal to the WF_rx_osc unit
rx_osc_rst_o : out std_logic -- resets the clk recovery procedure
);
......@@ -645,6 +652,10 @@ begin
-- with number of bits not multiple of 8, but with correct FES, can be detected.
crc_wrong_p_o <= s_fes_detected and s_sample_manch_bit_p_d1 and (not s_CRC_ok_p_d);
TP14 <= fd_rxd_i;
TP15 <= s_CRC_ok_p_d;
TP16 <= s_sample_manch_bit_p_d1;
TP39 <= s_byte_ready_p_d1;
end architecture rtl;
--=================================================================================================
......
wf_status_bytes_gen.vhd
View file @ d24b13cd
......@@ -294,8 +294,8 @@ begin
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- reinitialization after the transmission of a produced variable
if rst_status_bytes_p_i = '1' then -- bits 0 to 5 reinitialised
s_nFIP_status_byte(5 downto 0) <= (others => '0'); -- after having been delivered
if rst_status_bytes_p_i = '1' then -- bits 0 to 5 reinitialised ------------------------------------------
s_nFIP_status_byte(7 downto 0) <= (others => '0'); -- after having been delivered
-- bits 6 and 7 are only reset
-- when nanoFIP is reset
else
......@@ -343,7 +343,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser
if (nfip_status_r_fcser_p_i = '1' and ((var_i = var_1) or (var_i = var_2) or (var_i = var_jc1) or (var_i = var_rst))) then
if (nfip_status_r_fcser_p_i = '1') then--and ((var_i = var_1) or (var_i = var_2) or (var_i = var_jc1) or (var_i = var_rst))) then
s_nFIP_status_byte(c_R_FCSER_INDEX) <= '1';
end if;
......@@ -373,7 +373,7 @@ begin
s_var1_rdy_c_reinit <= var1_rdy_i or nfip_rst_i;
s_var1_rdy_c_incr <= '1' when s_var1_rdy_c < "1111" else '0';
s_var1_rdy_extended <= '1' when var1_rdy_i= '1' or s_var1_rdy_c_incr = '1' else '0';
s_var1_rdy_extended <= '1' when var1_rdy_i= '1' or s_var1_rdy_c_incr = '1' else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR2_RDY: WF_incr_counter
......@@ -389,7 +389,7 @@ begin
s_var2_rdy_c_reinit <= var2_rdy_i or nfip_rst_i;
s_var2_rdy_c_incr <= '1' when s_var2_rdy_c < "1111" else '0';
s_var2_rdy_extended <= '1' when var2_rdy_i= '1' or s_var2_rdy_c_incr = '1' else '0';
s_var2_rdy_extended <= '1' when var2_rdy_i= '1' or s_var2_rdy_c_incr = '1' else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR3_RDY: WF_incr_counter
......@@ -405,7 +405,7 @@ begin
s_var3_rdy_c_reinit <= var3_rdy_i or nfip_rst_i;
s_var3_rdy_c_incr <= '1' when s_var3_rdy_c < "1111" else '0';
s_var3_rdy_extended <= '1' when VAR3_RDY_i= '1' or s_var3_rdy_c_incr = '1' else '0';
s_var3_rdy_extended <= '1' when VAR3_RDY_i= '1' or s_var3_rdy_c_incr = '1' else '0';
......
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