new smaller units created to simplify the design; code cleaned-up

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@94 7f0067c9-7624-46c7-bd39-3fb5400c0213

new smaller units created to simplify the design; code cleaned-up
git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@94 7f0067c9-7624-46c7-bd39-3fb5400c0213
9e8eb517 · egousiou · 22660930 · 9e8eb517 · 9e8eb517 · 9e8eb517
Commit 9e8eb517 authored Oct 25, 2010 by egousiou
26 changed files
--- a/nanofip.vhd
+++ b/nanofip.vhd
--- a/wf_DualClkRAM_clka_rd_clkb_wr.vhd
+++ b/wf_DualClkRAM_clka_rd_clkb_wr.vhd
@@ -17,7 +17,7 @@ use IEEE.NUMERIC_STD.all;     -- conversion functions
 --                                                                                               --
 ---------------------------------------------------------------------------------------------------
 --
-- unit name   dpblockram.vhd
+-- unit name   wf_DualClkRAM_clka_rd_clkb_wr.vhd
 --
 --
 --! @brief     The unit provides, transparently to the outside world, the memory triplication.
@@ -62,20 +62,20 @@ use IEEE.NUMERIC_STD.all;     -- conversion functions
 --=================================================================================================

 entity wf_DualClkRAM_clka_rd_clkb_wr is
-  generic (c_data_length : integer := 8; 		-- 8: length of data word (1 byte)
-           c_addr_length : integer := 9);       -- 2^9: memory depth (512 bytes)
+  generic (C_RAM_DATA_LGTH : integer;  -- length of data word
+           C_RAM_ADDR_LGTH : integer); -- memory depth


  port (
        clk_A_i  :     in std_logic;
-        addr_A_i :     in std_logic_vector (c_addr_length - 1 downto 0);
+        addr_A_i :     in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
        
        clk_B_i :      in std_logic;
-        addr_B_i :     in std_logic_vector (c_addr_length - 1 downto 0);
-        data_B_i :     in std_logic_vector (c_data_length - 1 downto 0);
+        addr_B_i :     in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
+        data_B_i :     in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
        write_en_B_i : in std_logic;
 
-       data_A_o :      out std_logic_vector (c_data_length -1 downto 0)
+       data_A_o :      out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
 );
 end wf_DualClkRAM_clka_rd_clkb_wr; 

@@ -118,10 +118,10 @@ signal s_zeros :          std_logic_vector (7 downto 0);
 --=================================================================================================
 begin 

-zero <= '0';
-one <= '1';
+zero    <= '0';
+one     <= '1';
 s_zeros <= (others => '0');
-s_rwB <= not write_en_B_i;
+s_rwB   <= not write_en_B_i;

 --------------------------------------------------------------------------------------------------- 
 --!@brief: memory triplication
@@ -149,23 +149,6 @@ UDualClkRam : DualClkRam
              DOUTB  => open) ;
 end generate;

--------------------------------------------------------------------------------------------------- 
--without memory triplication:
--UDualClkRam : DualClkRam  
--    port map ( DINA   => s_zeros,
--               ADDRA  => addr_A_i,
--               RWA    => one, 
--               CLKA   => clk_A_i, 
--
--               DINB   => data_B_i,
--               ADDRB  => addr_B_i, 
--               RWB    => s_rwB, 
--               CLKB   => clk_B_i, 
--
--               RESETn => one,
--
--               DOUTA  => data_A_o,
--               DOUTB  => open) ;

 --------------------------------------------------------------------------------------------------- 
 --!@brief majority voter: when a reading is done from the memory, the output of the unit is the

--- a/wf_VAR_RDY_generator.vhd
+++ b/wf_VAR_RDY_generator.vhd
--- a/wf_bits_to_txd.vhd
+++ b/wf_bits_to_txd.vhd
+--=================================================================================================
+--! @file wf_bits_to_txd.vhd
+--=================================================================================================
+
+--! standard library
+library IEEE; 
+
+--! standard packages
+use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
+use IEEE.NUMERIC_STD.all;     --! conversion functions
+
+--! specific packages
+use work.WF_PACKAGE.all;      --! definitions of supplemental types, subtypes, constants
+
+---------------------------------------------------------------------------------------------------
+--                                                                                               --
+--                                 wf_bits_to_txd                                        --
+--                                                                                               --
+--                                  CERN, BE/CO/HT                                               --
+--                                                                                               --
+---------------------------------------------------------------------------------------------------
+--
+--
+--! @brief     In stand-alone mode, the unit is responsible for transering the two desirialized
+--!            bytes from the filedbus to the 2bytes long bus DAT_O. The bytes are put in the bus 
+--!            one by one as they arrive.
+--!            Note: After the reception of a correct FCS and the FES the signal VAR1_RDY/ VAR2_RDY
+--!            is asserted and that signals the user that the data in DAT_O are valid and stable.  
+--
+--
+--! @author    Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
+--!            Evangelia Gousiou (evangelia.gousiou@cern.ch)
+--
+--
+--! @date      06/2010
+--
+--
+--! @version   v0.02
+--
+--
+--! @details \n  
+--
+--!   \n<b>Dependencies:</b>\n
+--
+--
+--!   \n<b>Modified by:</b>\n
+--!     Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--!   \n\n<b>Last changes:</b>\n
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--! @todo 
+--!   -> 
+--
+--------------------------------------------------------------------------------------------------- 
+
+
+--=================================================================================================
+--!                           Entity declaration for wf_bits_to_txd
+--=================================================================================================
+
+entity wf_bits_to_txd is
+  generic(C_TXCLKBUFFLENTGTH: natural);
+  port (
+  -- INPUTS 
+    -- User Interface general signals 
+    uclk_i :           in std_logic;                     --! 40MHz clock
+
+    -- Signal from the wf_reset_unit unit
+    nFIP_u_rst_i :       in std_logic;                     --! internal reset
+
+   -- Signals from wf_tx
+    txd_bit_index_i :     in unsigned(4 downto 0);
+    data_byte_manch_i :   in std_logic_vector (15 downto 0);
+    crc_byte_manch_i :    in std_logic_vector (31 downto 0);
+    sending_FSS_i :       in std_logic;
+    sending_data_i :      in std_logic;
+    sending_crc_i :       in std_logic;
+    sending_QUEUE_i :     in std_logic;
+    stop_transmission_i : in std_logic;
+    
+
+    -- Signals for the receiver wf_tx_rx_osc
+    tx_clk_p_buff_i :   in std_logic_vector (C_TXCLKBUFFLENTGTH-1 downto 0);
+                                       --! clk for transmission synchronization 
+ 
+
+  -- OUTPUTS
+    -- Signal to wf_prod_bytes_to_tx
+    txd_o :               out std_logic;
+    tx_enable_o :         out std_logic
+      );
+end entity wf_bits_to_txd;
+
+
+--=================================================================================================
+--!                                  architecture declaration
+--=================================================================================================
+architecture rtl of wf_bits_to_txd is
+
+signal s_start_tx_enable, s_tx_enable : std_logic;
+
+--=================================================================================================
+--                                      architecture begin
+--=================================================================================================  
+  begin
+
+---------------------------------------------------------------------------------------------------
+--! @brief synchronous process tx_Outputs:managment of nanoFIP output signals tx_data and tx_enable 
+--! tx_data: placement of bits of data to the output of the unit
+--! tx_enable: flip-floped s_tx_enable (s_tx_enable is activated during bits delivery: from the 
+--! beginning of tx_state send_fss until the end of send_queue state)  
+
+  Bits_Delivery: process(uclk_i)
+  begin
+    if rising_edge(uclk_i) then
+      if nFIP_u_rst_i = '1' then
+        txd_o   <= '0';
+
+      else
+
+        if  tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-3) = '1' then 
+
+          if sending_FSS_i = '1' then
+            txd_o           <= FSS (to_integer (txd_bit_index_i));
+
+          elsif sending_data_i = '1' then
+            txd_o           <= data_byte_manch_i (to_integer (resize (txd_bit_index_i, 4)));
+
+          elsif sending_crc_i = '1' then
+            txd_o           <= crc_byte_manch_i (to_integer(txd_bit_index_i)); 
+
+          elsif sending_QUEUE_i = '1' then
+            txd_o           <= FRAME_END(to_integer(resize(txd_bit_index_i,4)));
+
+          else
+            txd_o           <= '0'; 
+
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+------------------------------------------------------------------------------------------------
+  s_tx_enable <= sending_FSS_i or sending_data_i or sending_crc_i or sending_QUEUE_i or stop_transmission_i;
+                                                           -- beginning of considering data bits
+                                                           -- for the CRC calculation when the 
+                                                           -- 1st bit of data is to be sent 
+                                                           -- (note: the CRC calculator uses the
+                                                           -- signal s_bit, not tx_data_o)
+
+
+  tx_enable_manager: process(uclk_i)
+  begin
+    if rising_edge(uclk_i) then
+      if nFIP_u_rst_i = '1' then
+        tx_enable_o   <= '0';
+        s_start_tx_enable <= '0';
+
+      else
+
+        if s_tx_enable = '1' then
+          if  tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-3) = '1' then 
+            s_start_tx_enable <= '1';
+          end if;
+        else
+          s_start_tx_enable <= '0';
+        end if;   
+        
+        tx_enable_o   <= s_tx_enable and s_start_tx_enable;     
+
+      end if;
+    end if;
+  end process;
+
+
+end architecture rtl;
+--=================================================================================================
+--                                      architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                    E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
\ No newline at end of file
--- a/wf_consumed_vars.vhd
+++ b/wf_consumed_vars.vhd
--- a/wf_cons_frame_validator.vhd
+++ b/wf_cons_frame_validator.vhd
+--=================================================================================================
+--! @file wf_cons_frame_validator.vhd
+--=================================================================================================
+
+--! standard library
+library IEEE; 
+
+--! standard packages
+use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
+use IEEE.NUMERIC_STD.all;     --! conversion functions
+
+--! specific packages
+use work.WF_PACKAGE.all;      --! definitions of supplemental types, subtypes, constants
+
+---------------------------------------------------------------------------------------------------
+--                                                                                               --
+--                                 wf_cons_frame_validator                                       --
+--                                                                                               --
+--                                  CERN, BE/CO/HT                                               --
+--                                                                                               --
+---------------------------------------------------------------------------------------------------
+--
+--
+--! @brief     Validation of a received rp_dat frame with respect to: Ctrl, PDU, Length bytes as 
+--!            well as CRC and FSS, FES and code violations.
+--
+--
+--! @author    Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
+--!            Evangelia Gousiou (evangelia.gousiou@cern.ch)
+--
+--
+--! @date      06/2010
+--
+--
+--! @version   v0.02
+--
+--
+--! @details \n  
+--
+--!   \n<b>Dependencies:</b>\n
+--
+--
+--!   \n<b>Modified by:</b>\n
+--!     Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--!   \n\n<b>Last changes:</b>\n
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--! @todo 
+--!   -> 
+--
+--------------------------------------------------------------------------------------------------- 
+
+
+--=================================================================================================
+--!                           Entity declaration for wf_cons_frame_validator
+--=================================================================================================
+
+entity wf_cons_frame_validator is
+
+  port (
+  -- INPUTS 
+    -- Signals from the wf_cons_bytes_from_rx unit
+    rx_Ctrl_byte_i :         in std_logic_vector (7 downto 0); --! received Ctrl byte
+    rx_PDU_byte_i :          in std_logic_vector (7 downto 0); --! received PDU_TYPE byte          
+    rx_Length_byte_i :       in std_logic_vector (7 downto 0); --! received Length byte
+
+    -- Signal from the wf_rx unit
+    rx_FSS_CRC_FES_viol_ok_p_i : in std_logic; --! indication that CRC and FES have 
+
+   -- Signals from wf_engine_control
+    var_i:                   in t_var;
+    rx_byte_index_i :        in unsigned(7 downto 0);
+
+
+  -- OUTPUT
+    -- Signal to wf_engine_control
+    cons_frame_ok_p_o :      out std_logic
+      );
+end entity wf_cons_frame_validator;
+
+
+--=================================================================================================
+--!                                  architecture declaration
+--=================================================================================================
+architecture rtl of wf_cons_frame_validator is
+
+signal s_rx_ctrl_byte_ok, s_rx_PDU_byte_ok, s_rx_length_byte_ok : std_logic;
+
+--=================================================================================================
+--                                      architecture begin
+--=================================================================================================  
+  begin
+
+--------------------------------------------------------------------------------------------------- 
+--!@brief Combinatorial process Consumed_Frame_Validator: validation of an rp_dat 
+--! frame with respect to: Ctrl, PDU, Length bytes as well as CRC and FSS, FES and code violations.
+
+ Consumed_Frame_Validator: process ( var_i, rx_FSS_CRC_FES_viol_ok_p_i, rx_byte_index_i, rx_PDU_byte_i,
+                                    rx_Ctrl_byte_i, rx_Length_byte_i )
+  begin
+  
+  if var_i = var_1 or var_i = var_2 then
+
+    --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+    if rx_Ctrl_byte_i = c_RP_DAT_CTRL_BYTE then                  -- comparison with the expected
+      s_rx_ctrl_byte_ok <= '1';                                  -- RP_DAt_CTRL byte
+    else
+      s_rx_ctrl_byte_ok <= '0';
+    end if; 
+
+    --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+    if rx_PDU_byte_i = c_PROD_CONS_PDU_TYPE_BYTE then             -- comparison with the expected
+      s_rx_PDU_byte_ok <= '1';                                    -- PDU_TYPE byte
+    else 
+      s_rx_PDU_byte_ok <= '0' ;
+    end if;
+
+    --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+    if rx_FSS_CRC_FES_viol_ok_p_i = '1' then                         -- checking the rp_dat.Data.Length
+                                                                 -- byte, when the end of frame
+                                                                 -- arrives correctly
+      if rx_byte_index_i = (unsigned(rx_Length_byte_i) + 5) then   -- rx_byte_index starts counting 
+        s_rx_length_byte_ok <= '1';                              -- from 0 and apart from the user-data
+                                                                 -- bytes, also counts ctrl, PDU,
+      else                                                       -- Length, 2 CRC and FES bytes 
+        s_rx_length_byte_ok <= '0';
+      end if;                                                          
+
+  
+    else 
+      s_rx_length_byte_ok <= '0';
+    end if;   
+
+    --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+
+
+  else
+    s_rx_ctrl_byte_ok   <= '0';
+    s_rx_PDU_byte_ok    <= '0';
+    s_rx_length_byte_ok <= '0';
+  end if;
+
+end process;            
+
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- -- -
+ cons_frame_ok_p_o <= rx_FSS_CRC_FES_viol_ok_p_i and
+                      s_rx_length_byte_ok    and
+                      s_rx_ctrl_byte_ok      and
+                      s_rx_PDU_byte_ok;
+
+
+end architecture rtl;
+--=================================================================================================
+--                                      architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                    E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
\ No newline at end of file
--- a/wf_crc.vhd
+++ b/wf_crc.vhd
@@ -20,8 +20,8 @@ use IEEE.NUMERIC_STD.all;    --! conversion functions
 -- unit name   wf_crc
 --
 --
--! @brief     The unit includes the modules for the generation of the crc of serialized data,
--!            as well as for the verification of an incoming crc syndrome
+--! @brief     The unit includes the modules for the generation of the CRC of serialized data,
+--!            as well as for the verification of an incoming CRC syndrome
 --
 --
 --! @author	   Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
@@ -62,20 +62,18 @@ use IEEE.NUMERIC_STD.all;    --! conversion functions
 --!                                 Entity declaration for wf_crc
 --=================================================================================================
 entity wf_crc is
-generic( 
-        c_GENERATOR_POLY_length :  natural := 16);
-
+generic(c_GENERATOR_POLY_length :  natural := 16);
 port (
  -- INPUTS 
    uclk_i :             in std_logic; --! 40 MHz clock
-    nFIP_rst_i :         in std_logic; --! internal reset
-    start_crc_p_i :      in std_logic; --! signaling the beginning of the crc calculation
+    nFIP_u_rst_i :         in std_logic; --! internal reset
+    start_CRC_p_i :      in std_logic; --! signaling the beginning of the CRC calculation
    data_bit_i :         in std_logic; --! incoming data bit stream
    data_bit_ready_p_i : in std_logic; --! signaling that data_bit_i can be sampled
    
  -- OUTPUTS 
-    crc_ok_p :           out std_logic;            --! signaling of a correct received crc syndrome
-    crc_o :              out  std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated crc
+    CRC_ok_p :           out std_logic;            --! signaling of a correct received CRC syndrome
+    CRC_o :              out  std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC
                                                                                         -- 2 bytes
     );                                                         

@@ -91,7 +89,7 @@ architecture rtl of wf_crc is
 --! shift register xor mask
 constant c_GENERATOR_POLY: std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0) :=
                                                                                "0001110111001111"; 
--! crc check mask
+--! CRC check mask
 constant c_VERIFICATION_MASK:std_logic_vector (c_GENERATOR_POLY_length-1 downto 0) :=
                                                                                "0001110001101011";

@@ -128,16 +126,16 @@ end generate;
 CRC_calculation: process(uclk_i)
 begin
  if rising_edge(uclk_i) then
-    if nFIP_rst_i = '1' then
+    if nFIP_u_rst_i = '1' then
      s_q <= (others => '1');             -- register initialization
                                          -- (initially preset, according to annex A)
         
    else

-      if start_crc_p_i = '1' then
+      if start_CRC_p_i = '1' then
        s_q <= (others => '1');           -- register initialization

-      elsif data_bit_ready_p_i = '1' then -- new data bit to be considered for the crc calculation
+      elsif data_bit_ready_p_i = '1' then -- new data bit to be considered for the CRC calculation
        s_q <= s_q_nx;                    -- data propagation
      end if;

@@ -148,14 +146,14 @@ begin
 end process;

 --  --  --  --  --  
-crc_o <= not s_q;
+CRC_o <= not s_q;


 ---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Syndrome_Verification: On the reception, the crc is being
+--!@brief Combinatorial process Syndrome_Verification: On the reception, the CRC is being
 --! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_VERIFICATION_MASK. When the crc calculated from the received data maches the
--! c_VERIFICATION_MASK, it means a correct crc word has been received and the signal crc_ok_p
+--! predefined c_VERIFICATION_MASK. When the CRC calculated from the received data maches the
+--! c_VERIFICATION_MASK, it means a correct CRC word has been received and the signal CRC_ok_p
 --! gives a pulse. 

 Syndrome_Verification: process(s_q, s_crc_bit_ready_p)
@@ -165,10 +163,10 @@ begin
  s_q_check_mask <= s_q xor c_VERIFICATION_MASK;
  
  if (unsigned(not s_q_check_mask)) = 0 then 
-    crc_ok_p <= s_crc_bit_ready_p;
+    CRC_ok_p <= s_crc_bit_ready_p;

  else
-    crc_ok_p <= '0';
+    CRC_ok_p <= '0';

  end if;
 end process;

--- a/wf_decr_counter.vhd
+++ b/wf_decr_counter.vhd
+--=================================================================================================
+--! @file wf_decr_counter.vhd
+--=================================================================================================
+
+--! standard library
+library IEEE; 
+
+--! standard packages
+use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
+use IEEE.NUMERIC_STD.all;     --! conversion functions
+
+---------------------------------------------------------------------------------------------------
+--                                                                                               --
+--                                        wf_decr_counter                                        --
+--                                                                                               --
+--                                        CERN, BE/CO/HT                                         --
+--                                                                                               --
+---------------------------------------------------------------------------------------------------
+--
+--
+--! @brief     Synchronous decreasing counter with a load enable and decrease enable signals;
+--
+--
+--! @author    Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
+--!            Evangelia Gousiou (evangelia.gousiou@cern.ch)
+--
+--
+--! @date      06/2010
+--
+--
+--! @version   v0.02
+--
+--
+--! @details \n  
+--
+--!   \n<b>Dependencies:</b>\n
+--
+--
+--!   \n<b>Modified by:</b>\n
+--!     Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--!   \n\n<b>Last changes:</b>\n
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--! @todo 
+--!   -> 
+--
+--------------------------------------------------------------------------------------------------- 
+
+
+--=================================================================================================
+--!                           Entity declaration for wf_decr_counter
+--=================================================================================================
+
+entity wf_decr_counter is
+  generic(counter_length : natural);
+  port (
+  -- INPUTS 
+    -- User Interface general signals 
+    uclk_i :           in std_logic;                             --! 40MHz clock
+
+    -- Signal from the wf_reset_unit unit
+    nFIP_u_rst_i :       in std_logic;                             --! internal reset
+
+   -- Signals from any unit
+   counter_top :       in unsigned (counter_length-1 downto 0);  --! load value
+   counter_load_i :    in std_logic;                             --! load enable
+   counter_decr_p_i :  in std_logic;                             --! decrement enable
+    
+
+  -- OUTPUTS
+    -- Signal to any unit
+    counter_o :         out unsigned (counter_length-1 downto 0);--! counter 
+    counter_is_zero_o : out std_logic                            --! empty counter indication
+      );
+end entity wf_decr_counter;
+
+
+--=================================================================================================
+--!                                  architecture declaration
+--=================================================================================================
+architecture rtl of wf_decr_counter is
+
+signal s_counter : unsigned(counter_length-1 downto 0);
+
+--=================================================================================================
+--                                      architecture begin
+--=================================================================================================  
+  begin
+
+---------------------------------------------------------------------------------------------------
+  Decr_Counter: process(uclk_i)
+  begin
+    if rising_edge(uclk_i) then
+      if nFIP_u_rst_i = '1' then
+        s_counter   <= (others => '0');
+      else
+
+        if counter_load_i = '1' then
+          s_counter <= counter_top;
+
+        elsif counter_decr_p_i = '1' then
+          s_counter <= s_counter - 1;
+
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+ --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
+  counter_o         <= s_counter;
+  counter_is_zero_o <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';
+  
+
+end architecture rtl;
+--=================================================================================================
+--                                      architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                    E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
\ No newline at end of file
--- a/wf_engine_control.vhd
+++ b/wf_engine_control.vhd
--- a/wf_incr_counter.vhd
+++ b/wf_incr_counter.vhd
+--=================================================================================================
+--! @file wf_incr_counter.vhd
+--=================================================================================================
+
+--! standard library
+library IEEE; 
+
+--! standard packages
+use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
+use IEEE.NUMERIC_STD.all;     --! conversion functions
+
+---------------------------------------------------------------------------------------------------
+--                                                                                               --
+--                                         wf_incr_counter                                       --
+--                                                                                               --
+--                                         CERN, BE/CO/HT                                        --
+--                                                                                               --
+---------------------------------------------------------------------------------------------------
+--
+--
+--! @brief     Synchronous increasing counter with a reset and an increase enable signal;
+--
+--
+--! @author    Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
+--!            Evangelia Gousiou (evangelia.gousiou@cern.ch)
+--
+--
+--! @date      06/2010
+--
+--
+--! @version   v0.02
+--
+--
+--! @details \n  
+--
+--!   \n<b>Dependencies:</b>\n
+--
+--
+--!   \n<b>Modified by:</b>\n
+--!     Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--!   \n\n<b>Last changes:</b>\n
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--! @todo 
+--!   -> 
+--
+--------------------------------------------------------------------------------------------------- 
+
+
+--=================================================================================================
+--!                           Entity declaration for wf_incr_counter
+--=================================================================================================
+
+entity wf_incr_counter is
+  generic(counter_length : natural);
+  port (
+  -- INPUTS 
+    -- User Interface general signals 
+    uclk_i :         in std_logic;                           --! 40MHz clock
+
+    -- Signal from the wf_reset_unit unit
+    nFIP_u_rst_i :     in std_logic;                           --! internal reset
+
+   -- Signals from any unit
+   reset_counter_i : in std_logic;                           --! resets counter to 0
+   incr_counter_i:   in std_logic;                           --! increment enable
+
+  -- OUTPUT
+    -- Signal to any unit
+   counter_o :       out unsigned(counter_length-1 downto 0) --! counter
+      );
+end entity wf_incr_counter;
+
+
+--=================================================================================================
+--!                                  architecture declaration
+--=================================================================================================
+architecture rtl of wf_incr_counter is
+
+signal s_counter : unsigned(counter_length-1 downto 0);
+
+--=================================================================================================
+--                                      architecture begin
+--=================================================================================================  
+  begin
+
+--------------------------------------------------------------------------------------------------- 
+  Incr_Counter: process(uclk_i)
+  begin
+
+    if rising_edge(uclk_i) then
+      if nFIP_u_rst_i = '1' then
+        s_counter <= (others => '0');
+
+      elsif reset_counter_i = '1' then
+        s_counter <= (others => '0');
+
+      elsif incr_counter_i = '1' then
+        s_counter <= s_counter + 1;
+
+      end if;
+    end if;
+  end process;
+
+  counter_o <= s_counter;
+
+end architecture rtl;
+--=================================================================================================
+--                                      architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                    E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
\ No newline at end of file
--- a/wf_inputs_synchronizer.vhd
+++ b/wf_inputs_synchronizer.vhd
--- a/wf_manch_code_viol_check.vhd
+++ b/wf_manch_code_viol_check.vhd
+--=================================================================================================
+--! @file wf_decr_counter.vhd
+--=================================================================================================
+
+--! standard library
+library IEEE; 
+
+--! standard packages
+use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
+use IEEE.NUMERIC_STD.all;     --! conversion functions
+
+--! specific packages
+use work.WF_PACKAGE.all;      --! definitions of supplemental types, subtypes, constants
+
+---------------------------------------------------------------------------------------------------
+--                                                                                               --
+--                                 wf_manch_code_viol_check                                        --
+--                                                                                               --
+--                                  CERN, BE/CO/HT                                               --
+--                                                                                               --
+---------------------------------------------------------------------------------------------------
+--
+--
+--! @brief     The unit follows the incoming serial signal and outputs a pulse 
+--!            if a manchester 2 code violation is detected.
+--!            It is assumed that a violation happens if after half reception period 
+--!            plus 2 uclck periods, the incoming signal has not had a transition.
+--
+--
+--! @author    Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
+--!            Evangelia Gousiou (evangelia.gousiou@cern.ch)
+--
+--
+--! @date      06/2010
+--
+--
+--! @version   v0.02
+--
+--
+--! @details \n  
+--
+--!   \n<b>Dependencies:</b>\n
+--
+--
+--!   \n<b>Modified by:</b>\n
+--!     Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--!   \n\n<b>Last changes:</b>\n
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--! @todo 
+--!   -> 
+--
+--------------------------------------------------------------------------------------------------- 
+
+
+--=================================================================================================
+--!                           Entity declaration for wf_manch_code_viol_check
+--=================================================================================================
+
+entity wf_manch_code_viol_check is
+  port (
+  -- INPUTS 
+    -- User Interface general signals 
+    uclk_i :              in std_logic;                     --! 40MHz clock
+
+    -- Signal from the wf_reset_unit unit
+    nFIP_u_rst_i :          in std_logic;                     --! internal reset
+
+   -- Signals from wf_rx
+   serial_input_signal_i :   in std_logic;
+   sample_bit_p_i :       in std_logic;
+   sample_manch_bit_p_i : in std_logic;
+    
+
+  -- OUTPUTS
+    -- Signal to wf_rx
+    manch_code_viol_p_o : out std_logic
+      );
+end entity wf_manch_code_viol_check;
+
+
+--=================================================================================================
+--!                                  architecture declaration
+--=================================================================================================
+architecture rtl of wf_manch_code_viol_check is
+
+signal s_sample_bit_p_d1, s_sample_bit_p_d2, s_check_code_viol_p, s_serial_input_signal_d : std_logic;
+
+--=================================================================================================
+--                                      architecture begin
+--=================================================================================================  
+  begin
+
+---------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+--!@brief synchronous process Check_Code_Violations:in order to check the existance code violations
+--! the input signal is delayed by half reception period.
+--! The signal s_check_code_viol_p is a pulse with period the reception period. The pulse occurs
+--! 2 uclk periods after a manch. transition is expected.
+--! As the following drawing roughly indicates, a violation exists if the signal and its delayed
+--! version are identical on the s_check_code_viol_p moments.
+
+--                                 0    V-    1
+--   rxd_filtered_o:         __|--|____|--|__ 
+--   s_serial_input_signal_d:       __|--|____|--|__
+--   s_check_code_viol_p:             ^    ^     ^
+
+  Check_code_violations: process(uclk_i)
+    begin
+      if rising_edge (uclk_i) then 
+         if nFIP_u_rst_i = '1' then
+           s_check_code_viol_p   <='0';
+           s_sample_bit_p_d1     <='0';
+           s_sample_bit_p_d2     <='0';
+           s_serial_input_signal_d  <='0';
+
+         else
+
+           if sample_manch_bit_p_i = '1' then
+             s_serial_input_signal_d <= serial_input_signal_i; 
+           end if;
+
+            s_check_code_viol_p   <= s_sample_bit_p_d2; -- small delay
+            s_sample_bit_p_d2     <= s_sample_bit_p_d1;
+            s_sample_bit_p_d1     <= sample_bit_p_i;
+         end if;
+      end if;
+  end process; 
+
+ --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
+  manch_code_viol_p_o <= s_check_code_viol_p and 
+                        (not (serial_input_signal_i xor s_serial_input_signal_d));
+  
+
+end architecture rtl;
+--=================================================================================================
+--                                      architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                    E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
\ No newline at end of file
--- a/wf_manch_encoder.vhd
+++ b/wf_manch_encoder.vhd
+--=================================================================================================
+--! @file wf_manch_encoder.vhd
+--=================================================================================================
+
+--! standard library
+library IEEE; 
+
+--! standard packages
+use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
+use IEEE.NUMERIC_STD.all;     --! conversion functions
+
+--! specific packages
+use work.WF_PACKAGE.all;      --! definitions of supplemental types, subtypes, constants
+
+---------------------------------------------------------------------------------------------------
+--                                                                                               --
+--                                 wf_manch_encoder                                        --
+--                                                                                               --
+--                                  CERN, BE/CO/HT                                               --
+--                                                                                               --
+---------------------------------------------------------------------------------------------------
+--
+--
+--! @brief      
+--
+--
+--! @author    Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
+--!            Evangelia Gousiou (evangelia.gousiou@cern.ch)
+--
+--
+--! @date      06/2010
+--
+--
+--! @version   v0.02
+--
+--
+--! @details \n  
+--
+--!   \n<b>Dependencies:</b>\n
+--
+--
+--!   \n<b>Modified by:</b>\n
+--!     Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--!   \n\n<b>Last changes:</b>\n
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--! @todo 
+--!   -> 
+--
+--------------------------------------------------------------------------------------------------- 
+
+
+--=================================================================================================
+--!                           Entity declaration for wf_manch_encoder
+--=================================================================================================
+
+entity wf_manch_encoder is
+generic(word_length :  natural);
+  port (
+  -- INPUT 
+
+    word_i :       in std_logic_vector(word_length-1 downto 0);          
+
+  -- OUTPUT
+
+    word_manch_o : out std_logic_vector((2*word_length)-1 downto 0)
+      );
+end entity wf_manch_encoder;
+
+
+--=================================================================================================
+--!                                  architecture declaration
+--=================================================================================================
+architecture rtl of wf_manch_encoder is
+
+
+--=================================================================================================
+--                                      architecture begin
+--=================================================================================================  
+  begin
+
+---------------------------------------------------------------------------------------------------
+--! @brief combinatorial process Manchester_Encoder_byte: The process takes a byte (8 bits) and
+--! creates its manchester encoded equivalent (16 bits). Each bit '1' is replaced by '10' and each
+--! bit '0' by '01'. 
+
+  Manchester_Encoder_byte: process(word_i)
+  begin
+    for I in word_i'range loop
+      word_manch_o(I*2)   <= not word_i(I);
+      word_manch_o(I*2+1) <= word_i(I);
+    end loop;
+  end process;
+
+
+end architecture rtl;
+--=================================================================================================
+--                                      architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                    E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
\ No newline at end of file
--- a/wf_model_constr_decoder.vhd
+++ b/wf_model_constr_decoder.vhd
--- a/wf_package.vhd
+++ b/wf_package.vhd
--- a/wf_produced_vars.vhd
+++ b/wf_produced_vars.vhd
--- a/wf_prod_data_lgth_calc.vhd
+++ b/wf_prod_data_lgth_calc.vhd
+--=================================================================================================
+--! @file wf_prod_data_lgth_calc.vhd
+--=================================================================================================
+
+--! standard library
+library IEEE; 
+
+--! standard packages
+use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
+use IEEE.NUMERIC_STD.all;     --! conversion functions
+
+--! specific packages
+use work.WF_PACKAGE.all;      --! definitions of supplemental types, subtypes, constants
+
+---------------------------------------------------------------------------------------------------
+--                                                                                               --
+--                                 wf_prod_data_lgth_calc                                        --
+--                                                                                               --
+--                                  CERN, BE/CO/HT                                               --
+--                                                                                               --
+---------------------------------------------------------------------------------------------------
+--
+--
+--! @brief     Calculation of the total amount of data bytes that have to be transferreed when a
+--!            variable is produced (including the rp_dat.Control, rp_dat.Data.mps and
+--!            rp_dat.Data.nanoFIPstatus bytes)
+--
+--
+--! @author    Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
+--!            Evangelia Gousiou (evangelia.gousiou@cern.ch)
+--
+--
+--! @date      06/2010
+--
+--
+--! @version   v0.02
+--
+--
+--! @details \n  
+--
+--!   \n<b>Dependencies:</b>\n
+--
+--
+--!   \n<b>Modified by:</b>\n
+--!     Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--!   \n\n<b>Last changes:</b>\n
+--
+--------------------------------------------------------------------------------------------------- 
+--
+--! @todo 
+--!   -> 
+--
+--------------------------------------------------------------------------------------------------- 
+
+
+--=================================================================================================
+--!                           Entity declaration for wf_prod_data_lgth_calc
+--=================================================================================================
+
+entity wf_prod_data_lgth_calc is
+
+  port (
+  -- INPUTS 
+    -- User Interface general signals 
+    slone_i :          in std_logic;                    
+    nostat_i :         in std_logic;  
+    p3_lgth_i :        in std_logic_vector (2 downto 0);
+
+   -- Signals from wf_engine_control
+    var_i:             in t_var;
+
+  -- OUTPUT
+    -- Signal to wf_engine_control
+    tx_data_length_o : out std_logic_vector(7 downto 0)
+      );
+end entity wf_prod_data_lgth_calc;
+
+
+--=================================================================================================
+--!                                  architecture declaration
+--=================================================================================================
+architecture rtl of wf_prod_data_lgth_calc is
+
+signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
+--=================================================================================================
+--                                      architecture begin
+--=================================================================================================  
+  begin
+---------------------------------------------------------------------------------------------------
+--!@brief:Combinatorial process data_length_calcul: calculation of the total amount of data
+--! bytes that have to be transferreed when a variable is produced, including the rp_dat.Control as
+--! well as the rp_dat.Data.mps and rp_dat.Data.nanoFIPstatus bytes. In the case of the presence 
+--! and the identification variables, the data length is predefined in the wf_package.
+--! In the case of a var_3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation. 
+
+  data_length_calcul: process ( var_i, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i )
+  begin
+
+
+    s_p3_length_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i)));
+
+    case var_i is
+
+
+      --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
+      when presence_var => 
+      -- data length information retreival from the c_VARS_ARRAY matrix (wf_package) 
+        s_tx_data_length <= c_VARS_ARRAY(c_PRESENCE_VAR_INDEX).array_length;
+
+
+      --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
+      when identif_var => 
+      -- data length information retreival from the c_VARS_ARRAY matrix (wf_package) 
+        s_tx_data_length <= c_VARS_ARRAY(c_IDENTIF_VAR_INDEX).array_length;
+
+
+      --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
+      when var_3 =>  
+      -- data length calculation according to the operational mode (memory or stand-alone)
+
+      -- in slone mode                   2 bytes of user-data are produced
+      -- to these there should be added: 1 byte rp_dat.Control
+      --                                 1 byte PDU
+      --                                 1 byte Length
+      --                                 1 byte MPS 
+      --                      optionally 1 byte nFIP status
+  
+      -- in memory mode the signal      "s_p3_length_decoded" indicates the amount of user-data
+      -- to these, there should be added 1 byte rp_dat.Control
+      --                                 1 byte PDU
+      --                                 1 byte Length
+      --                                 1 byte MPS 
+      --                      optionally 1 byte nFIP status  
+
+        if slone_i = '1' then
+
+          if nostat_i = '1' then                              -- 6 bytes (counting starts from 0)
+            s_tx_data_length <= to_unsigned(5, s_tx_data_length'length); 
+
+          else                                                -- 7 bytes (counting starts from 0)
+            s_tx_data_length <= to_unsigned(6, s_tx_data_length'length); 
+          end if;
+
+
+        else
+          if nostat_i = '0' then
+            s_tx_data_length <= s_p3_length_decoded + 4; -- (bytes counting starts from 0)
+
+           else
+            s_tx_data_length <= s_p3_length_decoded + 3; -- (bytes counting starts from 0)
+           end if;          
+          end if;
+
+      when var_1 => 
+        s_tx_data_length <= (others => '0');
+
+      when var_2 =>
+        s_tx_data_length <= (others => '0');
+
+      when reset_var =>  
+        s_tx_data_length <= (others => '0');
+
+      when others => 
+        s_tx_data_length <= (others => '0');
+
+    end case;
+  end process;
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
+
+  tx_data_length_o <= std_logic_vector (s_tx_data_length);
+
+
+end architecture rtl;
+--=================================================================================================
+--                                      architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                    E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
\ No newline at end of file
--- a/wf_reset_unit.vhd
+++ b/wf_reset_unit.vhd
--- a/wf_rx.vhd
+++ b/wf_rx.vhd
--- a/wf_rx_deglitcher.vhd
+++ b/wf_rx_deglitcher.vhd
@@ -68,23 +68,24 @@ entity wf_rx_deglitcher is
  port( 
  -- INPUTS  
    -- User interface general signal   
-    uclk_i :               in std_logic; --! 40 MHz clock
+    uclk_i :                  in std_logic; --! 40 MHz clock

    -- Signal from the wf_reset_unit unit  
-    nFIP_rst_i :           in std_logic; --! internal reset
+    nFIP_u_rst_i :              in std_logic; --! internal reset

    -- FIELDRIVE input signal
-    rx_data_i :            in std_logic; --! buffered fd_rxd
+    rxd_i :                   in std_logic; --! buffered fd_rxd

    -- Signals from the wf_osc unit
-    sample_bit_p_i :       in std_logic; --! pulsed signal signaling a new bit
-    sample_manch_bit_p_i : in std_logic; --! pulsed signal signaling a new manchestered bit 
+    sample_bit_p_i :          in std_logic; --! pulsed signal signaling a new bit
+    sample_manch_bit_p_i :    in std_logic; --! pulsed signal signaling a new manchestered bit 

  -- OUTPUTS  
    -- Output signals needed for the receiverwf_rx
-    sample_bit_p_o :       out  std_logic;
-    rx_data_filtered_o :   out  std_logic;
-    sample_manch_bit_p_o : out  std_logic
+    sample_bit_p_o :          out std_logic;
+    rxd_filtered_o :          out std_logic;
+    rxd_filtered_f_edge_p_o : out std_logic;
+    sample_manch_bit_p_o :    out std_logic
      );
 end wf_rx_deglitcher;

@@ -95,9 +96,11 @@ end wf_rx_deglitcher;
 --=================================================================================================
 architecture Behavioral of wf_rx_deglitcher is

-signal s_count_ones_c : signed(C_ACULENGTH - 1 downto 0);
-signal s_rx_data_filtered: STD_LOGIC;
-signal s_rx_data_filtered_d : std_logic;
+signal s_count_ones_c :      signed(C_ACULENGTH - 1 downto 0);
+signal s_rxd_filtered    :   std_logic;
+signal s_rxd_filtered_d  :   std_logic;
+signal s_rxd_filtered_buff : std_logic_vector (1 downto 0);
+


 --=================================================================================================
@@ -111,14 +114,14 @@ process(uclk_i)
  begin
  if rising_edge(uclk_i) then

-    if nFIP_rst_i = '1' then
+    if nFIP_u_rst_i = '1' then
      s_count_ones_c <= (others =>'0');
    else

      if sample_manch_bit_p_i = '1' then  -- arrival of a new manchester bit
        s_count_ones_c <= (others =>'0'); -- counter initialized

-      elsif  rx_data_i = '1' then         -- counting the number of ones 
+      elsif  rxd_i = '1' then             -- counting the number of ones 
        s_count_ones_c <= s_count_ones_c - 1;
      else
        s_count_ones_c <= s_count_ones_c + 1;
@@ -133,26 +136,51 @@ process(uclk_i)
  begin
  if rising_edge(uclk_i) then

-    if nFIP_rst_i = '1' then
-      s_rx_data_filtered <= '0';
-      s_rx_data_filtered_d <= '0';
+    if nFIP_u_rst_i = '1' then
+      s_rxd_filtered <= '0';
+      s_rxd_filtered_d <= '0';
    else

 	  if sample_manch_bit_p_i = '1' then 		
-        s_rx_data_filtered <= s_count_ones_c (s_count_ones_c'left); -- if the ones are more than
-                                                                      -- the zeros, the output is 1
-                                                                      -- otherwise, 0	 
+        s_rxd_filtered <= s_count_ones_c (s_count_ones_c'left); -- if the ones are more than
+                                                                -- the zeros, the output is 1
+                                                                -- otherwise, 0	 
      end if;

-      s_rx_data_filtered_d <= s_rx_data_filtered; 
+      s_rxd_filtered_d <= s_rxd_filtered; 

    end if;
  end if;
 end process;

-      rx_data_filtered_o <= s_rx_data_filtered_d;
-      sample_manch_bit_p_o <= sample_manch_bit_p_i;  
-      sample_bit_p_o <= sample_bit_p_i;
+---------------------------------------------------------------------------------------------------
+--!@brief synchronous process Detect_f_edge_rx_data_filtered: detection of a falling edge on the 
+--! deglitched input signal (rx_data_filtered). A buffer is used to store the last 2 bits of the 
+--! signal. A falling edge is detected if the last bit of the buffer (new bit) is a zero and the 
+--! first (old) is a one. 
+
+  Detect_f_edge_rx_data_filtered: process(uclk_i)
+    begin
+      if rising_edge(uclk_i) then 
+        if nFIP_u_rst_i = '1' then
+          s_rxd_filtered_buff <= (others => '0');
+          rxd_filtered_f_edge_p_o <= '0';
+        else
+
+          -- buffer s_rxd_filtered_buff keeps the last 2 bits of s_rxd_filtered_d
+          s_rxd_filtered_buff <= s_rxd_filtered_buff(0) & s_rxd_filtered_d;
+          -- falling edge detected if last bit is a 0 and previous was a 1
+          rxd_filtered_f_edge_p_o <= s_rxd_filtered_buff(1)and(not s_rxd_filtered_buff(0));
+        end if;
+      end if;
+end process;
+
+
+---------------------------------------------------------------------------------------------------
+
+  rxd_filtered_o <= s_rxd_filtered_d;
+  sample_manch_bit_p_o <= sample_manch_bit_p_i;  
+  sample_bit_p_o <= sample_bit_p_i;

 end Behavioral;


--- a/wf_rx_tx_osc.vhd
+++ b/wf_rx_tx_osc.vhd
--- a/wf_slone_DATI_bytes_sampler.vhd
+++ b/wf_slone_DATI_bytes_sampler.vhd
--- a/wf_slone_bytes_to_DATO.vhd
+++ b/wf_slone_bytes_to_DATO.vhd
--- a/wf_status_bytes_gen.vhd
+++ b/wf_status_bytes_gen.vhd
--- a/wf_tx.vhd
+++ b/wf_tx.vhd
--- a/wf_tx_rx.vhd
+++ b/wf_tx_rx.vhd