Skip to content

N
nanoFIP - Gateware
Commit 8994c7c1 authored by egousiou's avatar egousiou
Browse files
Options

wf_engine_control simplifications. 

wf_prod_permit and wf_cons_outcome units added.

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@108 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 40153778
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1889 additions and 1339 deletions
DualClkRAM.vhd
View file @ 8994c7c1
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file DualClkRAM.vhd
--! @file DualClkRAM.vhd |
---------------------------------------------------------------------------------------------------
--! Standard library
......@@ -77,17 +77,17 @@ entity DualClkRAM is
port(
-- INPUTS
-- Inpouts concerning port A
DINA : in std_logic_vector (7 downto 0); --! data in A
CLKA : in std_logic; --! clock A for synchronous read/ write operations
ADDRA : in std_logic_vector (8 downto 0); --! address A
DINA : in std_logic_vector (7 downto 0); --! data in A
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKA : in std_logic; --! clock A for synchronous read/ write operations
-- may be indipendant of clock B
-- Inpouts concerning port B
DINB : in std_logic_vector (7 downto 0); --! data in B
CLKB : in std_logic; --! clock B for synchronous read/ write operations
ADDRB : in std_logic_vector (8 downto 0); --! address B
DINB : in std_logic_vector (7 downto 0); --! data in B
RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKB : in std_logic; --! clock B for synchronous read/ write operations
-- may be indipendant of clock A
-- Reset
RESETn : in std_logic; --! sets all outputs low; does not reset the memory
......
nanofip.vhd
View file @ 8994c7c1
This diff is collapsed.
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ 8994c7c1
......@@ -77,18 +77,22 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
entity WF_DualClkRAM_clka_rd_clkb_wr is
generic (C_RAM_DATA_LGTH : integer; -- length of data word
c_RAM_ADDR_LGTH : integer); -- memory depth
port (
-- INPUTS
-- Inputs concerning port A
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
-- Inputs concerning port B
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
data_portb_i : in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
write_en_portb_i : in std_logic;
port (
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
data_portb_i : in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
write_en_portb_i : in std_logic;
data_porta_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
-- OUTPUT
-- Output concerning port A
data_porta_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
);
end WF_DualClkRAM_clka_rd_clkb_wr;
......@@ -102,15 +106,15 @@ architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
--!@brief: component DualClkRam declaration
component DualClkRam is
port(
DINA : in std_logic_vector (7 downto 0);
CLKA : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
DINA : in std_logic_vector (7 downto 0);
RWA : in std_logic;
CLKA : in std_logic;
DINB : in std_logic_vector (7 downto 0);
CLKB : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DINB : in std_logic_vector (7 downto 0);
RWB : in std_logic;
CLKB : in std_logic;
RESETn : in std_logic;
DOUTA : out std_logic_vector (7 downto 0);
......@@ -178,4 +182,4 @@ end syn;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_bits_to_txd.vhd
View file @ 8994c7c1
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_bits_to_txd.vhd
--! @file WF_bits_to_txd.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -27,7 +27,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief According to the state of the FSM of the wf_tx_serializer, the unit is responsible
--! @brief According to the state of the FSM of the WF_tx_serializer, the unit is responsible
--! for putting in nanoFIP's output FD_TXD one by one all the bits required for the
--! formation of the RP_DAT frame (that is: manch. encoded FSS, data, CRC and FES bits).
--! The unit also manages the output FD_TXENA.
......@@ -48,7 +48,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_tx_rx_osc \n
--! wf_tx_serializer \n
--! WF_tx_serializer \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -82,7 +82,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
entity WF_bits_to_txd is
generic (c_TX_CLK_BUFF_LGTH: natural := 4); -- default
generic (c_TX_CLK_BUFF_LGTH: natural := 4); --! length of the clk buffer used for
--! the transmission synchronization
port (
-- INPUTS
-- nanoFIP User Interface, General signals
......@@ -91,20 +92,20 @@ entity WF_bits_to_txd is
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the wf_tx_serializer
txd_bit_index_i : in unsigned(4 downto 0); --! index of bit inside a byte
data_byte_manch_i : in std_logic_vector (15 downto 0);--! manch. encoded data byte to be sent
-- Signals from the WF_tx_serializer unit
crc_byte_manch_i : in std_logic_vector (31 downto 0);--! manch. encoded CRC bytes to be sent
sending_fss_i : in std_logic; --! wf_tx_serializer FSM states
sending_data_i : in std_logic; --! -----"----"-----
sending_crc_i : in std_logic; --! -----"----"-----
sending_fes_i : in std_logic; --! -----"----"-----
stop_transmission_i : in std_logic; --! -----"----"-----
data_byte_manch_i : in std_logic_vector (15 downto 0);--! manch. encoded data byte to be sent
sending_fss_i : in std_logic; --! WF_tx_serializer FSM states
sending_data_i : in std_logic; --! -------"----"-----"--------
sending_crc_i : in std_logic; --! -------"----"-----"--------
sending_fes_i : in std_logic; --! -------"----"-----"--------
stop_transmission_i : in std_logic; --! -------"----"-----"--------
txd_bit_index_i : in unsigned(4 downto 0); --! index of a bit inside a byte
-- Signals for the receiver WF_tx_rx_osc
tx_clk_p_i : in std_logic;
--!clk for transmission synchronization
-- Signals from the WF_tx_rx_osc unit
tx_clk_p_i : in std_logic; --!clk for transmission synchronization
-- OUTPUTS
-- nanoFIP FIELDRIVE outputs
......@@ -126,7 +127,7 @@ begin
---------------------------------------------------------------------------------------------------
--! @brief Synchronous process Bits_Delivery: managment of nanoFIP output signal FD_TXD by
--! placing bits of data according to the state of wf_tx_serializer's state machine (sending_fss,
--! placing bits of data according to the state of WF_tx_serializer's state machine (sending_fss,
--! sending_data, sending_crc, sending_fes, stop_transmission) and to the counter txd_bit_index.
--! The delivery is synchronised by the tx_clk_p_buff(1) signal.
......
wf_cons_bytes_processor.vhd
View file @ 8994c7c1
This diff is collapsed.
wf_cons_bytes_to_dato.vhd
View file @ 8994c7c1
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file wf_cons_bytes_to_dato.vhd |
--! @file WF_cons_bytes_to_dato.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -22,17 +22,20 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- wf_cons_bytes_to_dato --
-- WF_cons_bytes_to_dato --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief In stand-alone mode, if a consumed or consumed broadcast variable has been received,
--! the unit is responsible for transering the two desirialized data-bytes from the
--! filedbus to the 2-bytes long bus DAT_O. The bytes are put in the bus one by one as
--! they arrive, as signal transfer_byte_p_i indicates.
--! Note: After the reception of a correct FCS and the FES the signal VAR1_RDY/ VAR2_RDY
--! is asserted and that signals the user that the data in DAT_O are valid and stable.
--! @brief In stand-alone mode, after the reception of a consumed or consumed broadcast
--! variable, the unit is responsible for transering the two data-bytes of the variable
--! to the 2-bytes long bus DAT_O.
--! The bytes are put in the bus one by one as they arrive, as the signal
--! transfer_byte_p_i indicates.
--!
--! Note: The validity of these transfered bytes is indicated by the "nanoFIP
--! User Interface, NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY which arrive after
--! the reception of the FCS and FES bytes.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......@@ -49,7 +52,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! wf_cons_bytes_processor \n
--! WF_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -59,8 +62,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG unit created
--! -> 10/1/2011 v0.02 EG unit renamed from wf_slone_cons_bytes_to_dato to
--! wf_cons_bytes_to_dato; cleaning-up + commenting
--! -> 10/1/2011 v0.02 EG unit renamed from WF_slone_cons_bytes_to_dato to
--! WF_cons_bytes_to_dato; cleaning-up + commenting
--
---------------------------------------------------------------------------------------------------
--
......@@ -77,10 +80,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
--! Entity declaration for wf_cons_bytes_to_dato
--! Entity declaration for WF_cons_bytes_to_dato
--=================================================================================================
entity wf_cons_bytes_to_dato is
entity WF_cons_bytes_to_dato is
port (
-- INPUTS
......@@ -90,24 +93,24 @@ entity wf_cons_bytes_to_dato is
-- Signal from the WF_reset_unit unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the wf_cons_bytes_processor
-- Signals from the WF_cons_bytes_processor
byte_i : in std_logic_vector (7 downto 0); --! de-serialised byte
transfer_byte_p_i : in std_logic_vector (1 downto 0); --! 01: byte_i transfered to DAT_O(7:0)
--! 10: byte_i transfered to DAT_O(15:8)
byte_i : in std_logic_vector (7 downto 0); --! de-serialised byte
-- OUTPUTS
-- Signal to the wf_prod_bytes_retriever
-- Signal to the WF_prod_bytes_retriever
slone_data_o : out std_logic_vector (15 downto 0) --! output bus DAT_O
);
end entity wf_cons_bytes_to_dato;
end entity WF_cons_bytes_to_dato;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_cons_bytes_to_dato is
architecture rtl of WF_cons_bytes_to_dato is
--=================================================================================================
......
wf_cons_frame_validator.vhd
View file @ 8994c7c1
This diff is collapsed.
wf_consumption.vhd
View file @ 8994c7c1
This diff is collapsed.
wf_crc.vhd
View file @ 8994c7c1
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_crc.vhd
--! @file WF_crc.vhd |
---------------------------------------------------------------------------------------------------
--! Standard library
......@@ -44,6 +44,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_rx_deserializer \n
--! WF_tx_serializer \n
--
--
--! \n<b>Modified by:</b> \n
......@@ -78,18 +81,23 @@ entity WF_crc is
generic (c_GENERATOR_POLY_length : natural := 16); --! default value
port (
-- INPUTS
-- Inputs from the wf_rx_deserializer/ wf_tx_serializer
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
start_crc_p_i : in std_logic; --! beginning of the CRC calculation
-- Signals from the WF_rx_deserializer/ WF_tx_serializer units
data_bit_i : in std_logic; --! incoming data bit stream
data_bit_ready_p_i : in std_logic; --! indicator of sampling time for data_bit_i
start_crc_p_i : in std_logic; --! beginning of the CRC calculation
-- OUTPUTS
-- Signal to the wf_rx_deserializer
-- Signal to the WF_rx_deserializer unit
crc_ok_p : out std_logic; --! signaling of a correct received CRC syndrome
-- Signal to the wf_tx_serializer
-- Signal to the WF_tx_serializer unit
crc_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC
);
......@@ -189,4 +197,4 @@ end architecture rtl;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_decr_counter.vhd
View file @ 8994c7c1
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_decr_counter.vhd
--! @file WF_decr_counter.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -78,9 +78,9 @@ entity WF_decr_counter is
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from any unit
counter_top : in unsigned (g_counter_lgth-1 downto 0); --! load value
counter_load_i : in std_logic; --! load enable
counter_decr_p_i : in std_logic; --! decrement enable
counter_load_i : in std_logic; --! load enable
counter_top : in unsigned (g_counter_lgth-1 downto 0); --! load value
-- OUTPUTS
......
wf_engine_control.vhd
View file @ 8994c7c1
This diff is collapsed.
wf_incr_counter.vhd
View file @ 8994c7c1
......@@ -6,8 +6,8 @@
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------
--! @file WF_incr_counter.vhd
---------------------------------------------------------------------------------------------------
--! @file WF_incr_counter.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -72,8 +72,9 @@ entity WF_incr_counter is
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from any unit
reinit_counter_i : in std_logic; --! reinitializes counter to 0
incr_counter_i : in std_logic; --! increment enable
reinit_counter_i : in std_logic; --! reinitializes counter to 0
-- OUTPUT
-- Signal to any unit
......
wf_inputs_synchronizer.vhd
View file @ 8994c7c1
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_inputs_synchronizer.vhd
--! @file WF_inputs_synchronizer.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -85,28 +85,28 @@ entity WF_inputs_synchronizer is
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40MHz clock
nostat_a_i : in std_logic;
rstin_a_i : in std_logic;
slone_a_i : in std_logic;
nostat_a_i : in std_logic;
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP WorldFIP Settings
rate_a_i : in std_logic_vector(1 downto 0);
subs_a_i : in std_logic_vector(7 downto 0);
m_id_a_i : in std_logic_vector(3 downto 0);
c_id_a_i : in std_logic_vector(3 downto 0);
m_id_a_i : in std_logic_vector(3 downto 0);
p3_lgth_a_i : in std_logic_vector(2 downto 0);
rate_a_i : in std_logic_vector(1 downto 0);
subs_a_i : in std_logic_vector(7 downto 0);
-- nanoFIP User Interface, WISHBONE Slave
clk_wb_i : in std_logic; --! WISHBONE clock
wb_rst_a_i : in std_logic; --! WISHBONE reset
wb_clk_i : in std_logic; --! WISHBONE clock
dat_a_i : in std_logic_vector(15 downto 0);
wb_adr_a_i : in std_logic_vector(9 downto 0);
wb_cyc_a_i : in std_logic;
wb_we_a_i : in std_logic;
wb_rst_a_i : in std_logic; --! WISHBONE reset
wb_stb_a_i : in std_logic;
wb_adr_a_i : in std_logic_vector(9 downto 0);
dat_a_i : in std_logic_vector(15 downto 0);
wb_we_a_i : in std_logic;
-- nanoFIP User Interface, non WISHBONE
var1_access_a_i : in std_logic;
......@@ -114,48 +114,48 @@ entity WF_inputs_synchronizer is
var3_access_a_i : in std_logic;
-- nanoFIP FIELDRIVE
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_rxcdn_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
-- OUTPUTS
-- nanoFIP User Interface, General signals
nostat_o : out std_logic;
rsti_o : out std_logic;
urst_r_edge_o : out std_logic;
slone_o : out std_logic;
nostat_o : out std_logic;
urst_r_edge_o : out std_logic;
-- nanoFIP WorldFIP Settings
rate_o : out std_logic_vector(1 downto 0);
subs_o : out std_logic_vector(7 downto 0);
m_id_o : out std_logic_vector(3 downto 0);
c_id_o : out std_logic_vector(3 downto 0);
m_id_o : out std_logic_vector(3 downto 0);
p3_lgth_o : out std_logic_vector(2 downto 0);
rate_o : out std_logic_vector(1 downto 0);
subs_o : out std_logic_vector(7 downto 0);
-- nanoFIP User Interface, WISHBONE Slave
wb_adri_o : out std_logic_vector(9 downto 0);
wb_cyc_o : out std_logic;
wb_we_o : out std_logic;
wb_dati_o : out std_logic_vector(7 downto 0);
wb_stb_o : out std_logic;
wb_stb_r_edge_o : out std_logic;
wb_dati_o : out std_logic_vector(7 downto 0);
wb_adri_o : out std_logic_vector(9 downto 0);
wb_we_o : out std_logic;
-- nanoFIP User Interface, non WISHBONE
slone_dati_o : out std_logic_vector(15 downto 0);
var1_access_o : out std_logic;
var2_access_o : out std_logic;
var3_access_o : out std_logic;
slone_dati_o : out std_logic_vector(15 downto 0);
-- nanoFIP FIELDRIVE
fd_wdgn_o : out std_logic;
fd_txer_o : out std_logic;
fd_rxd_o : out std_logic;
fd_rxd_o : out std_logic;
fd_rxd_edge_p_o : out std_logic;
fd_rxd_f_edge_p_o : out std_logic;
fd_rxd_r_edge_p_o : out std_logic;
fd_rxd_f_edge_p_o : out std_logic
fd_txer_o : out std_logic;
fd_wdgn_o : out std_logic
);
end entity WF_inputs_synchronizer;
......@@ -289,9 +289,9 @@ begin
---------------------------------------------------------------------------------------------------
WISHBONE_inputs_synchronisation: process (clk_wb_i)
WISHBONE_inputs_synchronisation: process (wb_clk_i)
begin
if rising_edge (clk_wb_i) then
if rising_edge (wb_clk_i) then
if wb_rst_a_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
s_wb_dati_d1 <= (others => '0');
s_wb_dati_d2 <= (others => '0');
......
wf_manch_code_viol_check.vhd
View file @ 8994c7c1
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_manch_code_viol_check.vhd
--! @file WF_rx_manch_code_check.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -22,7 +22,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_manch_code_viol_check --
-- WF_rx_manch_code_check --
-- --
---------------------------------------------------------------------------------------------------
--
......@@ -55,6 +55,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_rx_deglitcher \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -74,10 +76,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
--! Entity declaration for WF_manch_code_viol_check
--! Entity declaration for WF_rx_manch_code_check
--=================================================================================================
entity WF_manch_code_viol_check is
entity WF_rx_manch_code_check is
port (
-- INPUTS
-- nanoFIP User Interface general signal
......@@ -86,23 +88,23 @@ entity WF_manch_code_viol_check is
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the wf_rx_deserializer
serial_input_signal_i : in std_logic; --! input signal
-- Signals from the WF_rx_deglitcher unit
sample_bit_p_i : in std_logic; --! pulse for the sampling of a new bit
sample_manch_bit_p_i : in std_logic; --! pulse for the sampling of a new manch. bit
serial_input_signal_i : in std_logic; --! input signal
-- OUTPUTS
-- Signal to the wf_rx_deserializer
-- Signal to the WF_rx_deserializer unit
manch_code_viol_p_o : out std_logic --! pulse indicating a code violation
);
end entity WF_manch_code_viol_check;
end entity WF_rx_manch_code_check;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_manch_code_viol_check is
architecture rtl of WF_rx_manch_code_check is
signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_signal_d : std_logic;
......
wf_manch_encoder.vhd
View file @ 8994c7c1
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_manch_encoder.vhd
--! @file WF_manch_encoder.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -71,26 +71,27 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
--! Entity declaration for wf_manch_encoder
--! Entity declaration for WF_manch_encoder
--=================================================================================================
entity wf_manch_encoder is
entity WF_manch_encoder is
generic (word_length : natural := 8); --! default length: 8
generic (word_length : natural := 8); --! default word length: 8
port (
-- INPUT
word_i : in std_logic_vector(word_length-1 downto 0); --! input word
-- OUTPUT
word_manch_o : out std_logic_vector((2*word_length)-1 downto 0) --! output encoded word
);
end entity wf_manch_encoder;
end entity WF_manch_encoder;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_manch_encoder is
architecture rtl of WF_manch_encoder is
--=================================================================================================
......
wf_model_constr_decoder.vhd
View file @ 8994c7c1
......@@ -97,17 +97,17 @@ entity WF_model_constr_decoder is
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP WorldFIP Settings (synchronised with uclk_i)
model_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
constr_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
model_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
-- OUTPUTS
-- nanoFIP WorldFIP Settings output
select_id_o : out std_logic_vector (1 downto 0); --! Identification selection
-- Signal to the wf_prod_bytes_retriever
model_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded
constr_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded
-- Signal to the WF_prod_bytes_retriever unit
constr_id_dec_o : out std_logic_vector (7 downto 0); --! Constructor identification decoded
model_id_dec_o : out std_logic_vector (7 downto 0) --! Model identification decoded
);
end entity WF_model_constr_decoder;
......
wf_package.vhd
View file @ 8994c7c1
This diff is collapsed.
wf_prod_bytes_retriever.vhd
View file @ 8994c7c1
This diff is collapsed.
wf_prod_bytes_to_dati.vhd
View file @ 8994c7c1
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file wf_prod_bytes_from_dati.vhd
--! @file WF_prod_bytes_from_dati.vhd
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -22,7 +22,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- wf_prod_bytes_from_dati --
-- WF_prod_bytes_from_dati --
-- --
---------------------------------------------------------------------------------------------------
--
......@@ -57,7 +57,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG unit created
--! -> 4/1/2011 v0.02 EG unit renamed from WF_slone_prod_dati_bytes_sampler to
--! wf_prod_bytes_from_dati; cleaning-up + commenting
--! WF_prod_bytes_from_dati; cleaning-up + commenting
--!
--
---------------------------------------------------------------------------------------------------
......@@ -75,10 +75,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
--! Entity declaration for wf_prod_bytes_from_dati
--! Entity declaration for WF_prod_bytes_from_dati
--=================================================================================================
entity wf_prod_bytes_from_dati is
entity WF_prod_bytes_from_dati is
port (
-- INPUTS
......@@ -92,22 +92,22 @@ entity wf_prod_bytes_from_dati is
slone_data_i : in std_logic_vector (15 downto 0); --! input data bus for stand-alone mode
-- (synchronised with uclk)
-- Signals from the WF_engine_control
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes
-- Signals from the WF_prod_permit
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
-- OUTPUTS
-- Signal to the wf_prod_bytes_retriever
-- Signal to the WF_prod_bytes_retriever
slone_byte_o : out std_logic_vector (7 downto 0) --! byte to be sent
);
end entity wf_prod_bytes_from_dati;
end entity WF_prod_bytes_from_dati;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_prod_bytes_from_dati is
architecture rtl of WF_prod_bytes_from_dati is
signal s_var3_rdy_d4 : std_logic_vector (3 downto 0);
signal s_sampled_data : std_logic_vector (15 downto 0);
......
wf_prod_data_lgth_calc.vhd
View file @ 8994c7c1
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_prod_data_lgth_calc.vhd
--! @file WF_prod_data_lgth_calc.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -80,17 +80,21 @@ entity WF_prod_data_lgth_calc is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
-- nanoFIP WorldFIP Settings (synchronized with uclk)
p3_lgth_i : in std_logic_vector (2 downto 0); --! produced var user-data length
-- User Interface, General signals (synchronized with uclk)
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
-- Signal from the WF_engine_control unit
var_i : in t_var; --! variable type that is being treated
-- Signal from the WF_engine_control
var_i : in t_var; --! variable type that is being treated
-- OUTPUT
-- Signal to the WF_engine_control
-- Signal to the WF_engine_control and WF_production units
prod_data_length_o : out std_logic_vector(7 downto 0)
);
end entity WF_prod_data_lgth_calc;
......
wf_prod_permit.vhd 0 → 100644
View file @ 8994c7c1
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_prod_permit.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_permit --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY,
--! according to the variable (var_i) that is being treated.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 14/1/2011
--
--
--! @version v0.01
--
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_engine_control \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 1/2011 v0.01 EG First version \n
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 5, 6 of var_i(0 to 6) are unused" --
-- var_i is one-hot encoded and has 7 values. --
-- The unit is treating only the variables var_1, var_2, var_3 and var_rst. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_prod_permit
--=================================================================================================
entity WF_prod_permit is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_engine_control
var_i : in t_var; --! variable type that is being treated
-- OUTPUT
-- nanoFIP User Interface, NON-WISHBONE outputs
var3_rdy_o : out std_logic --! signals the user that data can safely be written
);
end entity WF_prod_permit;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_prod_permit is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process VAR3_RDY_Generation:
--! VAR3_RDY (for produced vars): signals that the user can safely write to the produced variable
--! memory or access the DAT_I bus. It is deasserted right after the end of the reception of a
--! correct var3 ID_DAT frame and stays de-asserted until the end of the transmission of the
--! corresponding RP_DAT from nanoFIP.
--! Note: A correct ID_DAT frame along with the variable it contained is signaled by the var_i.
--! For produced variables, the signal var_i gets its value (var3, var_presence, var_identif)
--! after the reception of a correct ID_DAT frame (with correct FSS, Control, PDU_TYPE, Length, CRC
--! and FES bytes and with a correct manch. encoding) and retains it until the end of the
--! transmission of the corresponding RP_DAT (in detail, until the end of the transmission of the
--! RP_DAT.data field;var_i becomes var_whatever during the RP_DAT.FCS and RP_DAT.FES transmission).
VAR_RDY_Generation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
var3_rdy_o <= '0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
case var_i is
when var_3 => -- nanoFIP is producing
---------------------
var3_rdy_o <= '0'; -- while producing, VAR3_RDY is 0
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
var3_rdy_o <= '1';
end case;
end if;
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_production.vhd
View file @ 8994c7c1
This diff is collapsed.
wf_reset_unit.vhd
View file @ 8994c7c1
......@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details
--
--! \n<b>Dependencies:</b> \n
--! wf_cons_bytes_processor \n
--! WF_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -73,10 +73,12 @@ entity WF_reset_unit is
uclk_i : in std_logic; --! 40 MHz clock
urst_i : in std_logic; --! initialisation control, active low
urst_r_edge_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding
rate_i : in std_logic_vector (1 downto 0);
-- Signal from the central control unit WF_engine_control
-- nanoFIP WorldFIP Settings (synchronized with uclk)
subs_i : in std_logic_vector (7 downto 0); --! subscriber number coding
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- Signal from the WF_engine_control unit
var_i : in t_var; --! variable type that is being treated
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
......
wf_rx_deglitcher.vhd
View file @ 8994c7c1
......@@ -25,10 +25,10 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit applies a glitch filter; it follows each manchester bit of the input signal
--! fd_rxd (synchronized with uclk), counts the number of zeros and ones throughout
--! its duration and finally outputs the majority. The output deglitched signal is one
--! half-bit-clock period later that the input, synchronised fd_rxd.
--! @brief The unit applies a glitch filter; it follows each manchester bit of the "nanoFIP
--! FIELDRIVE" input signal fd_rxd (synchronized with uclk), counts the number of zeros
--! and ones throughout its duration and finally outputs the majority. The output
--! deglitched signal is one half-bit-clock period later than the input.
--! Note: the term sample_manch_bit_p refers to the moments when a manch. encoded bit
--! should be sampled (before and after a significant edge), whereas the
--! sample_bit_p includes only the sampling of the 1st part, before the transition.
......@@ -52,8 +52,8 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @details
--
--! \n<b>Dependencies:</b>\n
--! WF_osc \n
--! WF_reset_unit \n
--! WF_tx-_rx_osc \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -75,7 +75,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
--! Entity declaration for wf_rx_deglitcher
--! Entity declaration for WF_rx_deglitcher
--=================================================================================================
entity WF_rx_deglitcher is
......@@ -92,13 +92,13 @@ entity WF_rx_deglitcher is
-- nanoFIP FIELDRIVE (synchronized with uclk)
rxd_i : in std_logic; --! ____|--------|________|--------|________
-- Signals from the WF_osc unit
-- Signals from the WF_tx_rx_osc unit
sample_bit_p_i : in std_logic; --! ____|-|_______________|-|_______________
sample_manch_bit_p_i : in std_logic; --! ____|-|______|-|______|-|______|-|______
-- OUTPUTS
-- Signals to the wf_rx_deserializer
-- Signals to the WF_rx_deserializer unit
rxd_filtered_o : out std_logic; --! filtered output signal
rxd_filtered_f_edge_p_o : out std_logic; --! indicates a falling edge on the filtered signal
sample_bit_p_o : out std_logic; --! same as sample_bit_p_i
......@@ -208,4 +208,4 @@ end Behavioral;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_rx_deserializer.vhd
View file @ 8994c7c1
This diff is collapsed.
wf_rx_tx_osc.vhd
View file @ 8994c7c1
......@@ -27,8 +27,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
-- unit name WF_rx_tx_osc
--
--! @brief Generation the clock signals needed for the receiver (wf_rx_deglitcher and
--! wf_rx_deserializer)and transmiter(wf_tx_serializer)\n
--! @brief Generation the clock signals needed for the receiver (WF_rx_deglitcher and
--! WF_rx_deserializer)and transmiter(WF_tx_serializer)\n
--!
--! Concerning the reception, even if the bit rate of the communication is known, jitter
--! is expected to affect the arriving time of the incoming signal. The main idea of the
......@@ -64,7 +64,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_synchronizer \n
--! wf_rx_deserializer \n
--! WF_rx_deserializer \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -113,20 +113,21 @@ entity WF_rx_tx_osc is
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); --! bit rate
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_synchronizer
-- Signal from the WF_synchronizer unit
rxd_edge_i : in std_logic; --! indication of an edge on fd_rxd
-- Signal from wf_rx_deserializer
-- Signal from WF_rx_deserializer unit
rst_rx_osc_i : in std_logic; --! resets the clock recovery procedure of the rx_osc
-- OUTPUTS
-- Output signals needed in the reception
-- Signals to the wf_rx_deserializer and the wf_rx_deglitcher
-- Signals to the WF_rx_deserializer and the WF_rx_deglitcher
rx_manch_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! 1) on a significant edge
--! 2) between adjacent bits
......@@ -144,7 +145,8 @@ entity WF_rx_tx_osc is
-- Output signals needed in the transmission
-- nanoFIP FIELDRIVE output
tx_clk_o : out std_logic; --! line driver half bit clock
-- Signal to the wf_tx_serializer
-- Signal to the WF_tx_serializer unit
tx_clk_p_buff_o : out std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0)
--! buffer keeping the last values of tx_clk_o
);
......@@ -188,18 +190,18 @@ begin
---------------------------------------------------------------------------------------------------
-- rx_osc
-- rx_osc --
---------------------------------------------------------------------------------------------------
-- Synchronous process rx_periods_count:
-- the rx_counter starts counting after a falling edge on the fd_rxd (indicated by the signal
-- rst_rx_osc_i from the wf_rx_deserializer unit); this edge should be representing the 1st
-- rst_rx_osc_i from the WF_rx_deserializer unit); this edge should be representing the 1st
-- Manchester (manch.) encoded bit '1' of the preamble.
-- Starting from this edge, other falling or rising significant edges, are expected around one
-- period later. A time window around the expected arrival time is set and its length is defined
-- as 1/4th of the period (1/8th before and 1/8th after the expected time). When the actual edge
-- arrives, the counter is reset.
-- If that first falling edge of fd_rxd is finally proven not to belong to a valid preambe
-- (the state machine of the wf_rx_deserializer unit is checking that and generating the
-- (the state machine of the WF_rx_deserializer unit is checking that and generating the
-- rst_rx_osc_i), the counter is reinitialialized.
rx_periods_count: process (uclk_i)
......@@ -348,8 +350,9 @@ begin
end process;
---------------------------------------------------------------------------------------------------
-- tx_osc
-- tx_osc --
---------------------------------------------------------------------------------------------------
-- Synchronous process tx_periods_count: implementation of a counter counting transmission periods.
......@@ -430,4 +433,4 @@ end architecture rtl;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_status_bytes_gen.vhd
View file @ 8994c7c1
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_status_bytes_gen.vhd
--! @file WF_status_bytes_gen.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -14,9 +22,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_status_bytes_generator --
-- WF_status_bytes_gen --
-- --
-- CERN, BE/CO/HT --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
......@@ -24,8 +32,20 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--
--! @brief Generation of the nanoFIP status and MPS status bytes.
--! The unit is also responsible for outputting the nanoFIP signals U_CACER, U_PACER,
--! R_TLER, R_FCSER
--! The unit is also responsible for outputting the "nanoFIP User Interface,
--! NON_WISHBONE" signals U_CACER, U_PACER, R_TLER, R_FCSER, that correspond to nanoFIP
--! status bits 2 to 5.
--!
--! The information contained in the nanoFIP status byte is coming from :
--! o the WF_consumption unit,
--! o the "nanoFIP FIELDRIVE" inputs fd_wdgn and fd_txer
--! o the "nanoFIP User Interface, NON_WISHBONE" inputs (VAR_ACC) and outputs (VAR_RDY).
--!
--! For the refreshment and significance bits of the MPS status, the signal
--! "nanoFIP User Interface, NON_WISHBONE" input VAR3_ACC is used.
--!
--! The MPS status byte and the bits 0 to 5 of the nanoFIP status byte are reset after
--! having been sent.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
......@@ -55,8 +75,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n\n<b>Last changes:</b>\n
--! -> 07/07/2009 v0.01 PA First version \n
--! -> 08/2010 v0.02 EG code violation & CRC errors considered
--! only during a concumed var reception.
--! -> 08/2010 v0.02 EG Internal extention of the var_rdy signals to avoid nanoFIP status
--! errors few cycles after var_rdy deactivation
--! -> 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_i
......@@ -86,42 +104,46 @@ entity WF_status_bytes_gen is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40 MHz Clock
slone_i : in std_logic; --! stand-alone mode
uclk_i : in std_logic; --! 40 MHz Clock
slone_i : in std_logic; --! stand-alone mode
-- Signal from the reset_logic unit
nfip_urst_i : in std_logic; --! nanaoFIP internal reset
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanaoFIP internal reset
-- nanoFIP FIELDRIVE
fd_wdgn_i : in std_logic; --! watchdog on transmitter
fd_txer_i : in std_logic; --! transmitter error
fd_txer_i : in std_logic; --! transmitter error
fd_wdgn_i : in std_logic; --! watchdog on transmitter
-- nanoFIP User Interface, NON-WISHBONE (synchronized with uclk)
var1_acc_i : in std_logic; --! variable 1 access
var2_acc_i : in std_logic; --! variable 2 access
var3_acc_i : in std_logic; --! variable 3 access
var1_acc_i : in std_logic; --! variable 1 access
var2_acc_i : in std_logic; --! variable 2 access
var3_acc_i : in std_logic; --! variable 3 access
-- Signals from the WF_consumption unit
nfip_status_r_fcser_p_i : in std_logic; --! wrong CRC bytes received
nfip_status_r_tler_i : in std_logic; --! wrong PDU_TYPE, Control or Length bytes received
var1_rdy_i : in std_logic; --! variable 1 ready
var2_rdy_i : in std_logic; --! variable 2 ready
-- Signals from the WF_prod_bytes_retriever unit
rst_status_bytes_p_i : in std_logic; --! reset for both status bytes (apart from bits 6 & 7
--! of nanoFIP status byte); the bytes are reset
--! right after having been delivered
-- Signal from the receiver wf_rx_deserializer
nfip_status_r_fcser_p_i : in std_logic;
-- Signals from the WF_prod_permit unit
var3_rdy_i : in std_logic; --! variable 3 ready
-- Signals from the central control unit WF_engine_control
var1_rdy_i : in std_logic; --! variable 1 ready
var2_rdy_i : in std_logic; --! variable 2 ready
var3_rdy_i : in std_logic; --! variable 3 ready
nfip_status_r_tler_i : in std_logic; --! wrong PDU_TYPE, Control or Length bytes received
rst_status_bytes_i : in std_logic; --! both status bytes are reinitialized
--! right after having been delivered
-- OUTPUTS
-- nanoFIP User Interface, NON-WISHBONE outputs
u_cacer_o : out std_logic; --! nanoFIP status byte, bit 2
u_pacer_o : out std_logic; --! nanoFIP status byte, bit 3
r_tler_o : out std_logic; --! nanoFIP status byte, bit 4
r_fcser_o : out std_logic; --! nanoFIP status byte, bit 5
-- Signal to the wf_prod_bytes_retriever
nFIP_status_byte_o : out std_logic_vector (7 downto 0); --! nanoFIP status byte
mps_status_byte_o : out std_logic_vector (7 downto 0) --! MPS status byte
r_fcser_o : out std_logic; --! nanoFIP status byte, bit 5
r_tler_o : out std_logic; --! nanoFIP status byte, bit 4
u_cacer_o : out std_logic; --! nanoFIP status byte, bit 2
u_pacer_o : out std_logic; --! nanoFIP status byte, bit 3
-- Signal to the WF_prod_bytes_retriever
mps_status_byte_o : out std_logic_vector (7 downto 0); --! MPS status byte
nFIP_status_byte_o : out std_logic_vector (7 downto 0) --! nanoFIP status byte
);
end entity WF_status_bytes_gen;
......@@ -144,7 +166,7 @@ begin
---------------------------------------------------------------------------------------------------
--! @brief Synchronous process Status_byte_Formation: Formation of the nanoFIP status byte
--! according to the definitions in Table 8 of specs.
--! according to the definitions in Table 8 of nanoFIP's functional specifications.
nFIP_status_byte_generation: process (uclk_i)
begin
......@@ -157,7 +179,7 @@ begin
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- reinitialisation after the transmission of a produced variable
if (rst_status_bytes_i = '1') then -- bits 0 to 5 reinitialised
if (rst_status_bytes_p_i = '1') then -- bits 0 to 5 reinitialised
s_nFIP_status_byte(5 downto 0) <= (others => '0'); -- after having been delivered
-- bits 6 and 7 are only reset
-- when nanoFIP is reset
......@@ -289,8 +311,8 @@ begin
s_refreshment <= '0';
else
if rst_status_bytes_i = '1' then -- the bit is reinitialized
s_refreshment <= '0';
if rst_status_bytes_p_i = '1' then -- the bit is reinitialized
s_refreshment <= '0';
elsif (var3_acc_i = '1') then -- indication that the memory has been accessed
s_refreshment <= '1';
......
wf_tx_serializer.vhd
View file @ 8994c7c1
---------------------------------------------------------------------------------------------------
--! @file wf_tx_serializer.vhd
--! @file WF_tx_serializer.vhd
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -14,13 +14,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- wf_tx_serializer --
-- WF_tx_serializer --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: wf_tx_serializer
-- unit name: WF_tx_serializer
--
--
--! @brief Serializes the WorldFIP data.
......@@ -66,9 +66,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
--! Entity declaration for WF_tx_rx
--! Entity declaration for WF_tx_serializer
--=================================================================================================
entity wf_tx_serializer is
entity WF_tx_serializer is
generic (c_TX_CLK_BUFF_LGTH: natural);
port (
-- INPUTS
......@@ -87,7 +87,7 @@ entity wf_tx_serializer is
last_byte_p_i : in std_logic; --! indication that it is the last byte of data
-- CRC bytes follow
-- Signals from the wf_prod_bytes_retriever
-- Signals from the WF_prod_bytes_retriever
byte_i : in std_logic_vector (7 downto 0);
--! data byte to be delivered
......@@ -105,14 +105,14 @@ entity wf_tx_serializer is
tx_enable_o : out std_logic --! transmitter enable
);
end entity wf_tx_serializer;
end entity WF_tx_serializer;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_tx_serializer is
architecture rtl of WF_tx_serializer is
type tx_state_t is (idle, send_fss, send_data_byte, send_crc_bytes, send_queue, stop_transmission);
......@@ -177,7 +177,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_data_byte" state: delivery of manchester encoded bits of data that arrive from the
-- wf_prod_bytes_retriever unit (byte_i), with the coordination of the WF_engine_control (byte_ready_p_i)
-- WF_prod_bytes_retriever unit (byte_i), with the coordination of the WF_engine_control (byte_ready_p_i)
-- request of a new byte on tx_clk_p_buff (0) assertion (with s_bit_index = 0)
-- bit delivery after tx_clk_p_buff (1) assertion
-- new byte available after tx_clk_p_buff (2) assertion (to be sent on the next tx_clk_p_buff (1))
......@@ -185,7 +185,7 @@ begin
-- (between 0 and 16 for each byte, until the
-- last_byte_p_i gives a pulse)
-- the first data byte from the wf_prod_bytes_retriever unit is already available after the assertion of the
-- the first data byte from the WF_prod_bytes_retriever unit is already available after the assertion of the
-- start_prod_p_i signal; for the rest, there is a request of a new byte when the s_bit_index
-- arrives to zero and on the assertion of the tx_clk_p_buff (0). A pulse on the request_byte signal
-- triggers the WF_control_engine to send a new address to the memory of the produced_vars unit (new
......@@ -522,7 +522,7 @@ Input_Byte_Sampling: process (uclk_i)
tx_data_o <= s_txd;
request_byte_p_o <= s_sending_data and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4);
-- request for a new byte from the wf_prod_bytes_retriever unit (passing from WF_engine_control)
-- request for a new byte from the WF_prod_bytes_retriever unit (passing from WF_engine_control)
end architecture rtl;
......@@ -531,4 +531,6 @@ end architecture rtl;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------===============================================================================================
-- architecture end
--=======================================================
\ No newline at end of file
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment