Changed recipe for a robust deglitch circuit.

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@149 7f0067c9-7624-46c7-bd39-3fb5400c0213

Changed recipe for a robust deglitch circuit.
git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@149 7f0067c9-7624-46c7-bd39-3fb5400c0213
84a07903 · serrano · 6917c97d · 84a07903
Commit 84a07903 authored Jan 26, 2011 by serrano
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javier.txt CodeReview_24Jan11/javier.txt +8 -4

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--- a/CodeReview_24Jan11/javier.txt
+++ b/CodeReview_24Jan11/javier.txt
@@ -75,10 +75,14 @@ detectors as robust as possible, and add deglitching here. With the
 current implementation if there is a glitch in the rx line, even
 narrower than one uclk period, there is a risk of generating a
 spurious edge pulse. Making something much more robust is easy and
-cheap: add two more stages to the pipeline and do a super-robust edge
-detector by requiring that two signals are zero and the other two are
-one. This will induce a delay, which might have to be compensated in
-other signals (fd_rxd_o) so the whole thing is coherent.
+cheap: add four more stages to the pipeline (for a total of six usable
+signals) and do a super-robust edge detector by requiring that at
+least two signals are zero (out of the first three) and at least two
+are one (out of the last three). Viceversa of course for detecting the
+other edge. For extra-robustness, inhibit detection for a while after
+a detected edge. This will induce a delay, which might have to be
+compensated in other signals (fd_rxd_o) so the whole thing is
+coherent.

 Line 250 onwards. Cosmetics: the vector notation is shorter, so I'd
 stick to it for all cases, including the varX_access.