- status byte informs for bytes excess

- engine control state "produce" finishes upon FES transmission (bf it was before CRC and FES transmission) - cosmetixx git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@214 7f0067c9-7624-46c7-bd39-3fb5400c0213

- status byte informs for bytes excess
- engine control state "produce" finishes upon FES transmission (bf it was before CRC and FES transmission) - cosmetixx git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@214 7f0067c9-7624-46c7-bd39-3fb5400c0213
7cc216bb · egousiou · babfa06e · 7cc216bb · 7cc216bb · 7cc216bb
Commit 7cc216bb authored Apr 13, 2011 by egousiou
27 changed files
--- a/DualClkRAM.vhd
+++ b/DualClkRAM.vhd
--- a/nanofip.vhd
+++ b/nanofip.vhd
--- a/wf_DualClkRAM_clka_rd_clkb_wr.vhd
+++ b/wf_DualClkRAM_clka_rd_clkb_wr.vhd
@@ -7,18 +7,17 @@
 --________________________________________________________________________________________________|

 ---------------------------------------------------------------------------------------------------
--! @file WF_DualClkRAM_clka_rd_clkb_wr.vhd                                                       |
+-- File         WF_DualClkRAM_clka_rd_clkb_wr.vhd                                                 |
 ---------------------------------------------------------------------------------------------------

--! Standard library
+-- Standard library
 library IEEE;
+-- Standard packages
+use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
+use IEEE.NUMERIC_STD.all;    -- conversion functions

--! Standard packages
-use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
-use IEEE.NUMERIC_STD.all;     --! conversion functions
-
--! Specific Packages
-use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
+-- Specific packages
+use work.WF_PACKAGE.all;     -- definitions of types, constants, entities

 ---------------------------------------------------------------------------------------------------
 --                                                                                               --
@@ -27,49 +26,39 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 --
 --
--! @brief     The unit provides the memory triplication, transparently to the outside world.
--!            The component DualClkRam (512 bytes) is triplicated: each incoming byte is written
--!            at the same position in the three memories, whereas each outgoing byte is the
--!            outcome of a majority voter.
--!            The memory is dual port; port A is used for reading only, port B for writing only.
--!
--!            Remark: MajorityVoter(A,B,C) = (A and B) OR (A and C) OR (B and C)
--
--
--! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--!            Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)     \n
+-- Description  The unit provides the memory triplication, transparently to the outside world.
+--              The component DualClkRam (512 bytes) is triplicated: each incoming byte is written
+--              at the same position in the three memories, whereas each outgoing byte is the
+--              outcome of a majority voter.
+--              The memory is dual port; port A is used for reading only, port B for writing only.
 --
+--              Remark: MajorityVoter(A,B,C) = (A and B) OR (A and C) OR (B and C)
 --
--! @date      10/12/2010
 --
+-- Authors      Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
+--              Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)
 --
--! @version   v0.02
 --
+-- Date         10/12/2010
 --
--! @details\n
 --
--!   \n<b>Dependencies:</b>\n
--!            DualClkRAM.vhd \n
+-- Version      v0.02
 --
 --
--!   \n<b>Modified by:</b>\n
--!            Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
+-- Depends on   DualClkRAM.vhd
 --
--!   \n\n<b>Last changes: </b>\n
--!     -> 12/2010  v0.02  EG  code cleaned-up+commented \n
 --
 ---------------------------------------------------------------------------------------------------
 --
--! @todo
+-- Last changes
+--     -> 12/2010  v0.02  EG  code cleaned-up+commented
 --
 ---------------------------------------------------------------------------------------------------



 --=================================================================================================
--!                   Entity declaration for WF_DualClkRAM_clka_rd_clkb_wr
+--                   Entity declaration for WF_DualClkRAM_clka_rd_clkb_wr
 --=================================================================================================

 entity WF_DualClkRAM_clka_rd_clkb_wr is
@@ -96,7 +85,7 @@ end WF_DualClkRAM_clka_rd_clkb_wr;


 --=================================================================================================
--!                                    architecture declaration
+--                                    architecture declaration
 --=================================================================================================
 architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is

@@ -107,7 +96,7 @@ architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is


 --=================================================================================================
--!                                       architecture begin
+--                                       architecture begin
 --=================================================================================================
 begin

@@ -116,11 +105,11 @@ begin
  s_rwB   <= not write_en_portb_i;

 ---------------------------------------------------------------------------------------------------
--!@brief: memory triplication
--! The component DualClkRam is generated three times.
--! Port A is used for reading only, port B for writing only.
--! The input DINB is written in the same position in the 3 memories.
--! The output DOUTA from each memory is kept in the array s_data_o_A_array.
+-- memory triplication
+-- The component DualClkRam is generated three times.
+-- Port A is used for reading only, port B for writing only.
+-- The input DINB is written in the same position in the 3 memories.
+-- The output DOUTA from each memory is kept in the array s_data_o_A_array.

 --  G_memory_triplication: for I in 0 to 2 generate

@@ -145,11 +134,11 @@ begin


 ---------------------------------------------------------------------------------------------------
--!@brief Combinatorial Majority_Voter
+-- Combinatorial Majority_Voter

--Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
--                                (s_data_o_A_array(1) and s_data_o_A_array(2)) or
--                                (s_data_o_A_array(2) and s_data_o_A_array(0));
+-- Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
+--                                 (s_data_o_A_array(1) and s_data_o_A_array(2)) or
+--                                 (s_data_o_A_array(2) and s_data_o_A_array(0));

 end syn;
 --=================================================================================================

--- a/wf_bits_to_txd.vhd
+++ b/wf_bits_to_txd.vhd
--- a/wf_cons_bytes_processor.vhd
+++ b/wf_cons_bytes_processor.vhd
--- a/wf_cons_outcome.vhd
+++ b/wf_cons_outcome.vhd
--- a/wf_consumption.vhd
+++ b/wf_consumption.vhd
--- a/wf_crc.vhd
+++ b/wf_crc.vhd
@@ -7,18 +7,17 @@
 --________________________________________________________________________________________________|

 ---------------------------------------------------------------------------------------------------
--! @file WF_crc.vhd                                                                              |
+-- File         WF_crc.vhd                                                                        |
 ---------------------------------------------------------------------------------------------------

--! Standard library
+-- Standard library
 library IEEE;
+-- Standard packages
+use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
+use IEEE.NUMERIC_STD.all;    -- conversion functions

--! Standard packages
-use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
-use IEEE.NUMERIC_STD.all;    --! conversion functions
-
--! specific packages
-use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
+-- Specific packages
+use work.WF_PACKAGE.all;     -- definitions of types, constants, entities

 ---------------------------------------------------------------------------------------------------
 --                                                                                               --
@@ -27,97 +26,86 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 --
 --
--! @brief     The unit creates the modules:
--!              o for the generation of the CRC of serial data,
--!              o for the verification of an incoming CRC syndrome.
--
+-- Description  The unit creates the modules for:
+--                o the generation of the CRC of serial data,
+--                o the verification of an incoming CRC syndrome.
 --
--! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
 --
+-- Authors      Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
 --
--! @date      23/02/2011
 --
+-- Date         23/02/2011
 --
--! @version   v0.04
 --
+-- Version      v0.04
 --
--! @details \n
 --
--!   \n<b>Dependencies:</b>\n
--!            WF_reset_unit       \n
--!            WF_rx_deserializer  \n
--!            WF_tx_serializer    \n
+-- Depends on   WF_reset_unit
+--              WF_rx_deserializer
+--              WF_tx_serializer
 --
 --
--!   \n<b>Modified by:</b>   \n
--!            Pablo Alvarez Sanchez \n
--!            Evangelia Gousiou     \n
--
 ---------------------------------------------------------------------------------------------------
 --
--!   \n\n<b>Last changes:</b>\n
--!     -> 07/08/2009  v0.02  PAS Entity Ports added, start of architecture content \n
--!     -> 08/2010     v0.03  EG  Data_FCS_select and crc_ready_p_o signals removed,
--!                               variable v_q_check_mask replaced with a signal,
--!                               code cleaned-up+commented \n
--!     -> 02/2011     v0.04  EG  s_q_check_mask was not in Syndrome_Verification sensitivity list!
--!                               xor replaced with if(Syndrome_Verification); processes rewritten;
--!                               delay on data_bit_ready_p_i removed.
+-- Last changes
+--     -> 07/08/2009  v0.02  PAS Entity Ports added, start of architecture content
+--     -> 08/2010     v0.03  EG  Data_FCS_select and crc_ready_p_o signals removed,
+--                               variable v_q_check_mask replaced with a signal,
+--                               code cleaned-up+commented
+--     -> 02/2011     v0.04  EG  s_q_check_mask was not in Syndrome_Verification sensitivity list!
+--                               xor replaced with if(Syndrome_Verification); processes rewritten;
+--                               delay on data_bit_ready_p_i removed.
 --
 ---------------------------------------------------------------------------------------------------
--
--! @todo
--!
---------------------------------------------------------------------------------------------------



 --=================================================================================================
--!                                 Entity declaration for WF_crc
+--                                 Entity declaration for WF_crc
 --=================================================================================================
 entity WF_crc is
  port (
  -- INPUTS
    -- nanoFIP User Interface, General signals
-    uclk_i             : in std_logic;              --! 40 MHz clock
+    uclk_i             : in std_logic;              -- 40 MHz clock

    -- Signal from the WF_reset_unit
-    nfip_rst_i         : in std_logic;              --! nanoFIP internal reset
+    nfip_rst_i         : in std_logic;              -- nanoFIP internal reset

    -- Signals from the WF_rx_deserializer/ WF_tx_serializer units
-    data_bit_i         : in std_logic;              --! incoming data bit stream
-    data_bit_ready_p_i : in std_logic;              --! indicates the sampling moment of data_bit_i
-    start_crc_p_i      : in std_logic;              --! beginning of the CRC calculation
+    data_bit_i         : in std_logic;              -- incoming data bit stream
+    data_bit_ready_p_i : in std_logic;              -- indicates the sampling moment of data_bit_i
+    start_crc_p_i      : in std_logic;              -- beginning of the CRC calculation


  -- OUTPUTS
    -- Signal to the WF_rx_deserializer unit
-    crc_ok_p_o         : out std_logic;             --! signals a correct received CRC syndrome
+    crc_ok_p_o         : out std_logic;             -- signals a correct received CRC syndrome

    -- Signal to the WF_tx_serializer unit
-    crc_o              : out  std_logic_vector (c_CRC_POLY_LGTH-1 downto 0)--!calculated CRC
+    crc_o              : out  std_logic_vector (c_CRC_POLY_LGTH-1 downto 0) -- calculated CRC
     );

 end entity WF_crc;


 --=================================================================================================
--!                                    architecture declaration
+--                                    architecture declaration
 --=================================================================================================
 architecture rtl of WF_crc is

  signal s_q, s_q_nx : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0);

-
 --=================================================================================================
--!                                       architecture begin
+--                                       architecture begin
 --=================================================================================================
 begin

+
 ---------------------------------------------------------------------------------------------------
--!@brief The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
--! of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
--! are interconnected as a linear feedback shift register.
+-- The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
+-- of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
+-- are interconnected as a linear feedback shift register.

  Generate_16_bit_Register_and_Interconnections:

@@ -130,24 +118,24 @@ begin


 ---------------------------------------------------------------------------------------------------
--!@brief Synchronous process CRC_calculation: the process "moves" the shift register described
--! above, for the calculation of the CRC.
+-- Synchronous process CRC_calculation: the process "moves" the shift register described
+-- above, for the calculation of the CRC.

  CRC_calculation: process (uclk_i)
  begin
    if rising_edge (uclk_i) then

      if nfip_rst_i = '1' then
-        s_q               <= (others => '0');
+        s_q     <= (others => '0');

      else

        if start_crc_p_i = '1' then
-          s_q             <= (others => '1');-- register initialization
+          s_q   <= (others => '1');          -- register initialization
                                             -- (initially preset, according to the Annex)

        elsif data_bit_ready_p_i = '1' then  -- new bit to be considered for the CRC calculation
-          s_q             <= s_q_nx;         -- data propagation
+          s_q   <= s_q_nx;                   -- data propagation

        end if;
      end if;
@@ -155,15 +143,15 @@ begin
  end process;

  --  --  --  --  --
-  crc_o <= not s_q;
+  crc_o         <= not s_q;


 ---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Syndrome_Verification: On the reception, the CRC is being
--! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_CRC_VERIF_POLY. When the CRC calculated from the received data matches the
--! c_CRC_VERIF_POLY, it is implied that a correct CRC word has been received for the preceded
--! data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
+-- Combinatorial process Syndrome_Verification: On the reception, the CRC is being
+-- calculated as data is arriving (same as in the transmission) and it is being compared to the
+-- predefined c_CRC_VERIF_POLY. When the CRC calculated from the received data matches the
+-- c_CRC_VERIF_POLY, it is implied that a correct CRC word has been received for the preceded
+-- data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.

  Syndrome_Verification: process (s_q, data_bit_ready_p_i)
  begin

--- a/wf_decr_counter.vhd
+++ b/wf_decr_counter.vhd
@@ -7,15 +7,14 @@
 --________________________________________________________________________________________________|

 ---------------------------------------------------------------------------------------------------
--! @file WF_decr_counter.vhd                                                                     |
+-- file         WF_decr_counter.vhd                                                               |
 ---------------------------------------------------------------------------------------------------

--! standard library
+-- Standard library
 library IEEE;
-
--! standard packages
-use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
-use IEEE.NUMERIC_STD.all;     --! conversion functions
+-- Standard packages
+use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
+use IEEE.NUMERIC_STD.all;    -- conversion functions

 ---------------------------------------------------------------------------------------------------
 --                                                                                               --
@@ -24,81 +23,72 @@ use IEEE.NUMERIC_STD.all;     --! conversion functions
 ---------------------------------------------------------------------------------------------------
 --
 --
--! @brief     Decreasing counter with synchronous reset, load enable and decrease enable.
--
--
--! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--!            Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)
--
+-- Description  Decreasing counter with synchronous reset, load enable and decrease enable.
 --
--! @date      10/2010
 --
+-- Authors      Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
+--              Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)
 --
--! @version   v0.01
 --
+-- Date         10/2010
 --
--! @details \n
 --
--!   \n<b>Dependencies:</b>\n
+-- Version      v0.01
 --
 --
--!   \n<b>Modified by:</b>\n
+-- Depends on   WF_reset_unit
 --
---------------------------------------------------------------------------------------------------
--
--!   \n\n<b>Last changes:</b>\n
 --
 ---------------------------------------------------------------------------------------------------
 --
--! @todo
--!   ->
+-- Last changes
 --
 ---------------------------------------------------------------------------------------------------



 --=================================================================================================
--!                           Entity declaration for WF_decr_counter
+--                           Entity declaration for WF_decr_counter
 --=================================================================================================

 entity WF_decr_counter is
-  generic (g_counter_lgth : natural := 4);                        --! default length
+  generic (g_counter_lgth : natural := 4);                        -- default length
  port (
  -- INPUTS
    -- nanoFIP User Interface general signal
-    uclk_i            : in std_logic;                             --! 40 MHz clock
+    uclk_i            : in std_logic;                             -- 40 MHz clock

    -- Signal from the WF_reset_unit
-    nfip_rst_i        : in std_logic;                             --! nanoFIP internal reset
+    nfip_rst_i        : in std_logic;                             -- nanoFIP internal reset

    -- Signals from any unit
-    counter_decr_p_i  : in std_logic;                             --! decrement enable
-    counter_load_i    : in std_logic;                             --! load enable
-    counter_top       : in unsigned (g_counter_lgth-1 downto 0);  --! load value
+    counter_decr_p_i  : in std_logic;                             -- decrement enable
+    counter_load_i    : in std_logic;                             -- load enable
+    counter_top       : in unsigned (g_counter_lgth-1 downto 0);  -- load value


  -- OUTPUTS
    -- Signal to any unit
-    counter_o         : out unsigned (g_counter_lgth-1 downto 0); --! counter
-    counter_is_zero_o : out std_logic                             --! empty counter indication
+    counter_o         : out unsigned (g_counter_lgth-1 downto 0); -- counter
+    counter_is_zero_o : out std_logic                             -- empty counter indication
      );
 end entity WF_decr_counter;


 --=================================================================================================
--!                                    architecture declaration
+--                                    architecture declaration
 --=================================================================================================
 architecture rtl of WF_decr_counter is

  signal s_counter_is_zero : std_logic;
  signal s_counter         : unsigned (g_counter_lgth-1 downto 0);

-
 --=================================================================================================
--!                                       architecture begin
+--                                       architecture begin
 --=================================================================================================
 begin

+
 ---------------------------------------------------------------------------------------------------
  -- Synchronous process Decr_Counter


--- a/wf_engine_control.vhd
+++ b/wf_engine_control.vhd
--- a/wf_fd_receiver.vhd
+++ b/wf_fd_receiver.vhd
--- a/wf_fd_transmitter.vhd
+++ b/wf_fd_transmitter.vhd
--- a/wf_incr_counter.vhd
+++ b/wf_incr_counter.vhd
@@ -7,83 +7,74 @@
 --________________________________________________________________________________________________|

 ---------------------------------------------------------------------------------------------------
--! @file WF_incr_counter.vhd                                                                     |
+-- File         WF_incr_counter.vhd                                                               |
 ---------------------------------------------------------------------------------------------------

--! standard library
+-- Standard library
 library IEEE;
-
--! standard packages
-use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
-use IEEE.NUMERIC_STD.all;     --! conversion functions
+-- Standard packages
+use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
+use IEEE.NUMERIC_STD.all;    -- conversion functions

 ---------------------------------------------------------------------------------------------------
 --                                                                                               --
--                                         WF_incr_counter                                       --
+--                                        WF_incr_counter                                        --
 --                                                                                               --
 ---------------------------------------------------------------------------------------------------
 --
 --
--! @brief     Increasing counter with synchronous reset, reinitialise and increase enable.
--
--
--! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--!            Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)
--
+-- Description  Increasing counter with synchronous reset, reinitialise and increase enable.
 --
--! @date      10/2010
 --
+-- Authors      Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
+--              Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)
 --
--! @version   v0.01
 --
+-- Date         10/2010
 --
--! @details \n
 --
--!   \n<b>Dependencies:</b>\n
+-- Version      v0.01
 --
 --
--!   \n<b>Modified by:</b>\n
+-- Depends on
 --
---------------------------------------------------------------------------------------------------
--
--!   \n\n<b>Last changes:</b>\n
--!     -> 01/2011  EG  v0.011  counter_full became a constant
 --
 ---------------------------------------------------------------------------------------------------
 --
--! @todo
--!   ->
+-- Last changes
+--     -> 01/2011  EG  v0.011  counter_full became a constant
 --
 ---------------------------------------------------------------------------------------------------


+
 --=================================================================================================
--!                           Entity declaration for WF_incr_counter
+--                           Entity declaration for WF_incr_counter
 --=================================================================================================

 entity WF_incr_counter is
-  generic (g_counter_lgth : natural := 4);                       --! default length
+  generic (g_counter_lgth : natural := 4);                       -- default length
  port (
  -- INPUTS
    -- nanoFIP User Interface general signal
-    uclk_i           : in std_logic;                             --! 40 MHz clock
+    uclk_i           : in std_logic;                             -- 40 MHz clock

   -- Signals from any unit
-   incr_counter_i    : in std_logic;                             --! increment enable
-   reinit_counter_i  : in std_logic;                             --! reinitializes counter to 0
+   incr_counter_i    : in std_logic;                             -- increment enable
+   reinit_counter_i  : in std_logic;                             -- reinitializes counter to 0


  -- OUTPUT
    -- Signal to any unit
-   counter_o         : out unsigned (g_counter_lgth-1 downto 0); --! counter
-   counter_is_full_o : out std_logic                             --! counter full indication
-      );                                                         --! (all bits to '1')
+   counter_o         : out unsigned (g_counter_lgth-1 downto 0); -- counter
+   counter_is_full_o : out std_logic                             -- counter full indication
+      );                                                         -- (all bits to '1')

 end entity WF_incr_counter;


 --=================================================================================================
--!                                    architecture declaration
+--                                    architecture declaration
 --=================================================================================================
 architecture rtl of WF_incr_counter is

@@ -91,7 +82,7 @@ constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1'
 signal   s_counter      : unsigned (g_counter_lgth-1 downto 0);

 --=================================================================================================
--!                                       architecture begin
+--                                       architecture begin
 --=================================================================================================
 begin

@@ -119,6 +110,7 @@ begin
  counter_o         <= s_counter;
  counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';

+
 end architecture rtl;
 --=================================================================================================
 --                                        architecture end

--- a/wf_model_constr_decoder.vhd
+++ b/wf_model_constr_decoder.vhd
--- a/wf_package.vhd
+++ b/wf_package.vhd
--- a/wf_prod_bytes_retriever.vhd
+++ b/wf_prod_bytes_retriever.vhd
--- a/wf_prod_data_lgth_calc.vhd
+++ b/wf_prod_data_lgth_calc.vhd
--- a/wf_prod_permit.vhd
+++ b/wf_prod_permit.vhd
--- a/wf_production.vhd
+++ b/wf_production.vhd
--- a/wf_reset_unit.vhd
+++ b/wf_reset_unit.vhd
--- a/wf_rx_deglitcher.vhd
+++ b/wf_rx_deglitcher.vhd
--- a/wf_rx_deserializer.vhd
+++ b/wf_rx_deserializer.vhd
--- a/wf_rx_osc.vhd
+++ b/wf_rx_osc.vhd
--- a/wf_status_bytes_gen.vhd
+++ b/wf_status_bytes_gen.vhd
--- a/wf_tx_osc.vhd
+++ b/wf_tx_osc.vhd
--- a/wf_tx_serializer.vhd
+++ b/wf_tx_serializer.vhd
--- a/wf_wb_controller.vhd
+++ b/wf_wb_controller.vhd