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nanoFIP - Gateware
Commit 6ead92d5 authored by egousiou's avatar egousiou
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units rearranged; general timeout added in wf_engine_control; deglitcher changed 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@163 7f0067c9-7624-46c7-bd39-3fb5400c0213
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DualClkRAM.vhd
View file @ 6ead92d5
......@@ -14,8 +14,8 @@
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! ProASIC3 library
library PROASIC3;
......@@ -73,39 +73,39 @@ use PROASIC3.all;
--! Entity declaration for DualClkRAM
--=================================================================================================
entity DualClkRAM is
entity DualClkRAM is
port(
-- INPUTS
-- Inputs concerning port A
CLKA : in std_logic; --! clock A for synchronous read/ write operations
ADDRA : in std_logic_vector (8 downto 0); --! address A
DINA : in std_logic_vector (7 downto 0); --! data in A
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKA : in std_logic; --! clock A for synchronous read/ write operations
ADDRA : in std_logic_vector (8 downto 0); --! address A
DINA : in std_logic_vector (7 downto 0); --! data in A
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
-- Inputs concerning port B
CLKB : in std_logic; --! clock B for synchronous read/ write operations
ADDRB : in std_logic_vector (8 downto 0); --! address B
DINB : in std_logic_vector (7 downto 0); --! data in B
RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKB : in std_logic; --! clock B for synchronous read/ write operations
ADDRB : in std_logic_vector (8 downto 0); --! address B
DINB : in std_logic_vector (7 downto 0); --! data in B
RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
-- Reset
RESETn : in std_logic; --! sets all outputs low; does not reset the memory
RESETn : in std_logic; --! sets all outputs low; does not reset the memory
-- OUTPUTS
-- Output concerning port A
DOUTA : out std_logic_vector (7 downto 0);--! data out A
DOUTA : out std_logic_vector (7 downto 0); --! data out A
-- Output concerning port B
DOUTB : out std_logic_vector (7 downto 0) --! data out B
);
end DualClkRAM;
DOUTB : out std_logic_vector (7 downto 0) --! data out B
);
end DualClkRAM;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture RAM4K9 of DualClkRAM is
architecture RAM4K9 of DualClkRAM is
---------------------------------------------------------------------------------------------------
-- !@brief component RAM4K9 :
......@@ -137,7 +137,7 @@ architecture RAM4K9 of DualClkRAM is
--! pass-through behavior where the data being written will appear on the output immediately.
component RAM4K9
generic (MEMORYFILE:string := "");
generic (MEMORYFILE : string := "");
port(
ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6,
......@@ -153,12 +153,12 @@ architecture RAM4K9 of DualClkRAM is
BLKA, BLKB,
WENA, WENB,
CLKA, CLKB,
RESET : in std_logic:= 'U';
RESET : in std_logic := 'U';
DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0,
DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic
);
end component;
);
end component;
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the component VCC
......@@ -176,15 +176,15 @@ architecture RAM4K9 of DualClkRAM is
---------------------------------------------------------------------------------------------------
signal POWER, GROUND : std_logic ;
signal POWER, GROUND : std_logic;
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
power_supply_signal : VCC port map (Y => POWER);
ground_signal : GND port map (Y => GROUND);
begin
power_supply_signal : VCC port map (Y => POWER);
ground_signal : GND port map (Y => GROUND);
---------------------------------------------------------------------------------------------------
--!@brief: Instantiation of the component RAM4K9.
......@@ -196,9 +196,9 @@ begin
--! o PIPEA, PIPEB : GND (not pipelined read)
--! o WMODEA, WMODEB : GND (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map(
-- INPUTS
A9D8DualClkRAM_R0C0 : RAM4K9
port map (
-- INPUTS
-- INPUTS concerning port A
-- data in A (1 byte, (7 downto 0))
......@@ -213,12 +213,12 @@ begin
DINA0 => DINA(0),
-- address A (512 bytes depth, (8 downto 0))
ADDRA11 => GROUND,
ADDRA10 => GROUND,
ADDRA10 => GROUND,
ADDRA9 => GROUND,
ADDRA8 => ADDRA(8),
ADDRA7 => ADDRA(7),
ADDRA6 => ADDRA(6),
ADDRA5 => ADDRA(5),
ADDRA5 => ADDRA(5),
ADDRA4 => ADDRA(4),
ADDRA3 => ADDRA(3),
ADDRA2 => ADDRA(2),
......@@ -251,58 +251,58 @@ begin
ADDRB10 => GROUND,
ADDRB9 => GROUND,
ADDRB8 => ADDRB(8),
ADDRB7 => ADDRB(7),
ADDRB7 => ADDRB(7),
ADDRB6 => ADDRB(6),
ADDRB5 => ADDRB(5),
ADDRB4 => ADDRB(4),
ADDRB3 => ADDRB(3),
ADDRB2 => ADDRB(2),
ADDRB2 => ADDRB(2),
ADDRB1 => ADDRB(1),
ADDRB0 => ADDRB(0),
-- read/ write mode for B
WENB => RWB,
WENB => RWB,
-- clock for B
CLKB => CLKB,
-- aspect ratio, block, pipeline, write mode configurations for port B
WIDTHB0 => POWER,
WIDTHB0 => POWER,
WIDTHB1 => POWER,
BLKB => GROUND,
PIPEB => GROUND,
WMODEB => GROUND,
WMODEB => GROUND,
-- reset
RESET => RESETn,
RESET => RESETn,
-- Oututs
-- output concerning port A
-- Oututs
-- output concerning port A
-- data out A (1 byte)
DOUTA8 => OPEN,
DOUTA7 => DOUTA(7),
DOUTA6 => DOUTA(6),
DOUTA5 => DOUTA(5),
DOUTA4 => DOUTA(4),
DOUTA3 => DOUTA(3),
DOUTA2 => DOUTA(2),
DOUTA1 => DOUTA(1),
DOUTA0 => DOUTA(0),
-- output concerning port B
DOUTA8 => open,
DOUTA7 => DOUTA(7),
DOUTA6 => DOUTA(6),
DOUTA5 => DOUTA(5),
DOUTA4 => DOUTA(4),
DOUTA3 => DOUTA(3),
DOUTA2 => DOUTA(2),
DOUTA1 => DOUTA(1),
DOUTA0 => DOUTA(0),
-- output concerning port B
-- data out B (1 byte)
DOUTB8 => OPEN,
DOUTB7 => DOUTB(7),
DOUTB6 => DOUTB(6),
DOUTB5 => DOUTB(5),
DOUTB4 => DOUTB(4),
DOUTB3 => DOUTB(3),
DOUTB2 => DOUTB(2),
DOUTB1 => DOUTB(1),
DOUTB0 => DOUTB(0)
);
DOUTB8 => open,
DOUTB7 => DOUTB(7),
DOUTB6 => DOUTB(6),
DOUTB5 => DOUTB(5),
DOUTB4 => DOUTB(4),
DOUTB3 => DOUTB(3),
DOUTB2 => DOUTB(2),
DOUTB1 => DOUTB(1),
DOUTB0 => DOUTB(0)
);
end RAM4K9;
end RAM4K9;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
nanofip.vhd
View file @ 6ead92d5
This diff is collapsed.
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ 6ead92d5
......@@ -66,11 +66,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -78,30 +73,30 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
entity WF_DualClkRAM_clka_rd_clkb_wr is
generic (C_RAM_DATA_LGTH : integer; -- length of data word
c_RAM_ADDR_LGTH : integer); -- memory depth
generic (g_ram_data_lgth : integer; -- length of data word
g_ram_addr_lgth : integer); -- memory depth
port (
-- INPUTS
-- Inputs concerning port A
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
addr_porta_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
-- Inputs concerning port B
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
data_portb_i : in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
addr_portb_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
data_portb_i : in std_logic_vector (g_ram_data_lgth - 1 downto 0);
write_en_portb_i : in std_logic;
-- OUTPUT
-- Output concerning port A
data_porta_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
data_porta_o : out std_logic_vector (g_ram_data_lgth -1 downto 0)
);
end WF_DualClkRAM_clka_rd_clkb_wr;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
......@@ -115,7 +110,7 @@ signal s_zeros : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -160,8 +155,8 @@ Majority_Voter: data_porta_o <= (data_o_A_array(0) and data_o_A_array(1)) or
end syn;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_bits_to_txd.vhd
View file @ 6ead92d5
......@@ -70,11 +70,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -82,8 +77,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
entity WF_bits_to_txd is
generic (c_TX_CLK_BUFF_LGTH: natural := 4); --! length of the clk buffer used for
--! the transmission synchronization
port (
-- INPUTS
-- nanoFIP User Interface, General signals
......@@ -116,12 +109,12 @@ end entity WF_bits_to_txd;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_bits_to_txd is
signal s_fss : std_logic_vector (31 downto 0);
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -198,8 +191,8 @@ s_fss<=c_FSS;
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_cons_bytes_processor.vhd
View file @ 6ead92d5
......@@ -98,11 +98,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -112,7 +107,7 @@ entity WF_cons_bytes_processor is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode (active high)
......@@ -156,7 +151,7 @@ end entity WF_cons_bytes_processor;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_cons_bytes_processor is
......@@ -164,12 +159,12 @@ signal s_slone_data : std_logic_vector (15 downto 0);
signal s_addr : std_logic_vector (8 downto 0);
signal s_mem_data_out, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_slone_write_byte_p : std_logic_vector (1 downto 0);
signal two : unsigned(7 downto 0);
signal s_base_addr : unsigned(8 downto 0);
signal two : unsigned (7 downto 0);
signal s_base_addr : unsigned (8 downto 0);
signal s_write_byte_to_mem_p : std_logic;
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -183,13 +178,13 @@ begin
--! (for both the consumed and consumed broadcast variables)
Consumed_Bytes_To_RAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map(
c_RAM_DATA_LGTH => 8, -- 8 bits: length of data word
c_RAM_ADDR_LGTH => 9) -- 2^9: depth of consumed RAM
generic map (
g_ram_data_lgth => 8, -- 8 bits: length of data word
g_ram_addr_lgth => 9) -- 2^9: depth of consumed RAM
-- first 2 bits: identification of the memory block
-- remaining 7 bits: address of a byte inside the block
-- port A: WISHBONE that reads from the Consumed RAM; port B: nanoFIP that writes
port map(
port map (
clk_porta_i => wb_clk_i, -- WISHBONE clock
addr_porta_i => wb_adr_i(8 downto 0), -- address of byte to be read
-----------------------------------------------------------------------------
......@@ -209,7 +204,7 @@ begin
--! to DAT_O;
Consumed_Bytes_To_DATO: WF_cons_bytes_to_dato
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
transfer_byte_p_i => s_slone_write_byte_p,
......@@ -258,17 +253,18 @@ begin
--! If the consumed variable is the reset one the process latches the first and second data bytes.
Bytes_Processing: process (var_i, byte_index_i, slone_i, byte_i, two,
byte_ready_p_i, s_base_addr, s_cons_lgth_byte)
begin
s_addr <= std_logic_vector (unsigned(byte_index_i)+s_base_addr - 1); -- memory address of
s_addr <= std_logic_vector (unsigned(byte_index_i)+s_base_addr - 1); -- memory address of
-- the byte to be written
-- (-1 bc the Ctrl
-- byte is not written)
Bytes_Processing: process (var_i, byte_index_i, slone_i, byte_i, two,
byte_ready_p_i, s_base_addr, s_cons_lgth_byte)
begin
case var_i is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -455,8 +451,8 @@ Register_Ctrl_PDU_Length_bytes: process (uclk_i)
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_cons_bytes_to_dato.vhd
View file @ 6ead92d5
......@@ -87,7 +87,7 @@ entity WF_cons_bytes_to_dato is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit unit
......@@ -108,13 +108,13 @@ end entity WF_cons_bytes_to_dato;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_cons_bytes_to_dato is
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -152,8 +152,8 @@ Data_Transfer_To_Dat_o: process (uclk_i)
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_cons_frame_validator.vhd
View file @ 6ead92d5
......@@ -81,13 +81,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 2, 5, 6 of var_i(0 to 6) are unused" --
-- var_i is one-hot encoded and has 7 values. --
-- The unit is treating only the consumed variables var_1, var_2 and var_rst. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -107,6 +100,8 @@ entity WF_cons_frame_validator is
rx_fss_crc_fes_manch_ok_p_i: in std_logic; --! indication of a frame with correct FSS, FES, CRC
--! and manch. encoding
rx_crc_or_manch_wrong_p_i : in std_logic; --! indication .................
-- Signals from the WF_engine_control unit
rx_byte_index_i : in std_logic_vector (7 downto 0); --! index of byte being received
var_i : in t_var; --! variable type that is being treated
......@@ -125,14 +120,14 @@ end entity WF_cons_frame_validator;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_cons_frame_validator is
signal s_cons_ctrl_byte_ok, s_cons_pdu_byte_ok, s_cons_lgth_byte_ok : std_logic;
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -145,7 +140,7 @@ begin
--! the checks of the FSS, CRC, FES and of the manch. encoding.
Consumed_Frame_Validator: process (var_i, cons_ctrl_byte_i, rx_byte_index_i, cons_pdu_byte_i,
rx_fss_crc_fes_manch_ok_p_i, cons_lgth_byte_i)
rx_fss_crc_fes_manch_ok_p_i, cons_lgth_byte_i, rx_crc_or_manch_wrong_p_i)
begin
case var_i is
......@@ -170,8 +165,10 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_fss_crc_fes_manch_ok_p_i = '1' then -- checking the RP_DAT.Data.Length
-- byte, when the FES arrives.
if rx_fss_crc_fes_manch_ok_p_i = '1' or rx_crc_or_manch_wrong_p_i = '1' then -- checking the
-- RP_DAT.Data.Length byte,
-- when the FES arrives
if unsigned(rx_byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5) then
s_cons_lgth_byte_ok <= '1'; -- rx_byte_index starts counting
-- from 0 and apart from the
......@@ -214,8 +211,8 @@ end process;
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_cons_outcome.vhd
View file @ 6ead92d5
......@@ -89,25 +89,25 @@ entity WF_cons_outcome is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode
-- nanoFIP WorldFIP Settings (synchronized with uclk)
subs_i : in std_logic_vector(7 downto 0);--! subscriber number coding
-- nanoFIP WorldFIP Settings
subs_i : in std_logic_vector (7 downto 0);--! subscriber number coding
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_cons_frame_validator
cons_frame_ok_p_i : in std_logic; --! pulse after a correct cons frame
cons_frame_ok_p_i : in std_logic; --! pulse after a correct cons frame
-- Signal from the WF_engine_control unit
var_i : in t_var; --! variable type that is being treated
var_i : in t_var; --! variable type that is being treated
-- Signals from the WF_cons_bytes_processor
cons_var_rst_byte_1_i : in std_logic_vector(7 downto 0);--! 1st data-byte of a received var_rst
cons_var_rst_byte_2_i : in std_logic_vector(7 downto 0);--! 2nd data-byte of a received var_rst
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);--! 1st data-byte of a received var_rst
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);--! 2nd data-byte of a received var_rst
-- OUTPUTS
......@@ -128,7 +128,7 @@ end entity WF_cons_outcome;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_cons_outcome is
......@@ -136,7 +136,7 @@ signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic;
signal s_rst_nfip_and_fd, s_assert_rston : std_logic;
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -294,8 +294,8 @@ begin
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_consumption.vhd
View file @ 6ead92d5
This diff is collapsed.
wf_crc.vhd
View file @ 6ead92d5
......@@ -67,18 +67,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--!
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_crc
--=================================================================================================
entity WF_crc is
generic (c_GENERATOR_POLY_length : natural := 16); --! default value
port (
-- INPUTS
-- nanoFIP User Interface, General signals
......@@ -98,22 +92,22 @@ port (
crc_ok_p : out std_logic; --! signals a correct received CRC syndrome
-- Signal to the WF_tx_serializer unit
crc_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC
crc_o : out std_logic_vector (c_CRC_GENER_POLY_LGTH-1 downto 0)--!calculated CRC
);
end entity WF_crc;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_crc is
signal s_crc_bit_ready_p : std_logic;
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0);
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0);
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -124,14 +118,14 @@ begin
Gen_16_bit_Register_and_Interconnections:
for I in 0 to c_GENERATOR_POLY'left generate
for I in 0 to c_CRC_GENER_POLY'left generate
iteration_0: if I = 0 generate
s_q_nx(I) <= ((data_bit_i) xor s_q(s_q'left));
end generate;
next_iterations: if I > 0 generate
s_q_nx(I) <= s_q(I-1) xor (c_GENERATOR_POLY(I) and (data_bit_i xor s_q(s_q'left)));
s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left)));
end generate;
end generate;
......@@ -171,15 +165,15 @@ crc_o <= not s_q;
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Syndrome_Verification: On the reception, the CRC is being
--! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_VERIFICATION_MASK. When the CRC calculated from the received data matches the
--! c_VERIFICATION_MASK, it is implied that a correct CRC word has been received for the preceded
--! predefined c_CRC_VERIFIC_MASK. When the CRC calculated from the received data matches the
--! c_CRC_VERIFIC_MASK, it is implied that a correct CRC word has been received for the preceded
--! data and the signal crc_ok_p gives a 1 uclk-wide pulse.
Syndrome_Verification: process (s_q, s_crc_bit_ready_p)
begin
s_q_check_mask <= s_q xor c_VERIFICATION_MASK;
s_q_check_mask <= s_q xor c_CRC_VERIFIC_MASK;------------
if (unsigned(not s_q_check_mask)) = 0 then
crc_ok_p <= s_crc_bit_ready_p;
......@@ -194,8 +188,8 @@ end process;
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_decr_counter.vhd
View file @ 6ead92d5
......@@ -55,11 +55,6 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -91,14 +86,14 @@ end entity WF_decr_counter;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_decr_counter is
signal s_counter : unsigned(g_counter_lgth-1 downto 0);
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -126,7 +121,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for output signals
-- Concurrent assignments for the output signals
counter_o <= s_counter;
counter_is_zero_o <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';
......@@ -134,8 +129,8 @@ begin
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_engine_control.vhd
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wf_fd_receiver.vhd 0 → 100644
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wf_incr_counter.vhd
View file @ 6ead92d5
......@@ -68,9 +68,6 @@ entity WF_incr_counter is
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from any unit
incr_counter_i : in std_logic; --! increment enable
reinit_counter_i : in std_logic; --! reinitializes counter to 0
......@@ -86,15 +83,15 @@ end entity WF_incr_counter;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_incr_counter is
constant c_COUNTER_FULL : unsigned(g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned(g_counter_lgth-1 downto 0);
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -105,11 +102,7 @@ begin
Incr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_counter <= (others => '0');
elsif reinit_counter_i = '1' then
if reinit_counter_i = '1' then
s_counter <= (others => '0');
elsif incr_counter_i = '1' then
......@@ -128,8 +121,8 @@ begin
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_inputs_synchronizer.vhd
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wf_manch_code_viol_check.vhd
View file @ 6ead92d5
......@@ -111,14 +111,14 @@ end entity WF_rx_manch_code_check;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_rx_manch_code_check is
signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_signal_d : std_logic;
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -165,8 +165,8 @@ begin
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_model_constr_decoder.vhd
View file @ 6ead92d5
......@@ -75,11 +75,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -115,7 +110,7 @@ end entity WF_model_constr_decoder;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_model_constr_decoder is
......@@ -127,7 +122,7 @@ architecture rtl of WF_model_constr_decoder is
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -182,11 +177,10 @@ begin
--!@brief Instantiation of a counter WF_incr_counter
Free_Counter: WF_incr_counter
generic map(g_counter_lgth => 2)
port map(
generic map (g_counter_lgth => 2)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
reinit_counter_i => '0',
reinit_counter_i => nfip_rst_i,
incr_counter_i => '1',
-----------------------------------------
counter_o => s_counter,
......@@ -206,8 +200,8 @@ begin
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_package.vhd
View file @ 6ead92d5
This diff is collapsed.
wf_prod_bytes_retriever.vhd
View file @ 6ead92d5
......@@ -129,7 +129,7 @@ entity WF_prod_bytes_retriever is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
......@@ -139,23 +139,23 @@ entity WF_prod_bytes_retriever is
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_adr_i : in std_logic_vector(8 downto 0); --! WISHBONE address to memory
wb_data_i : in std_logic_vector(7 downto 0); --! WISHBONE data bus
wb_adr_i : in std_logic_vector (8 downto 0); --! WISHBONE address to memory
wb_data_i : in std_logic_vector (7 downto 0); --! WISHBONE data bus
-- Signal from the WF_wb_controller
wb_ack_prod_p_i : in std_logic; --! WISHBONE acknowledge
-- latching moment of wb_data_i
-- nanoFIP User Interface, NON WISHBONE (synchronized with uclk)
slone_data_i : in std_logic_vector(15 downto 0); --! input data bus for slone mode
-- nanoFIP User Interface, NON WISHBONE
slone_data_i : in std_logic_vector (15 downto 0);--! input data bus for slone mode
-- Signals from the WF_engine_control unit
byte_index_i : in std_logic_vector(7 downto 0); --!index of the byte to be retrieved
byte_index_i : in std_logic_vector (7 downto 0); --!index of the byte to be retrieved
byte_being_sent_p_i : in std_logic; --! pulse on the beginning of the
--! delivery of a new byte
data_length_i : in std_logic_vector(7 downto 0); --! # bytes of the Conrol&Data fields
data_length_i : in std_logic_vector (7 downto 0); --! # bytes of the Conrol&Data fields
-- of the RP_DAT frame; includes:
-- 1 byte RP_DAT.Control,
-- 1 byte RP_DAT.Data.PDU_type,
......@@ -172,12 +172,12 @@ entity WF_prod_bytes_retriever is
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
-- Signals from the WF_status_bytes_gen
mps_status_byte_i : in std_logic_vector(7 downto 0); --! MPS status byte
nFIP_status_byte_i : in std_logic_vector(7 downto 0); --! nanoFIP status byte
mps_status_byte_i : in std_logic_vector (7 downto 0); --! MPS status byte
nFIP_status_byte_i : in std_logic_vector (7 downto 0); --! nanoFIP status byte
-- Signals from the WF_model_constr_dec unit
constr_id_dec_i : in std_logic_vector(7 downto 0); --! decoded constructor id settings
model_id_dec_i : in std_logic_vector(7 downto 0); --! decoded model id settings
constr_id_dec_i : in std_logic_vector (7 downto 0);--! decoded constructor id settings
model_id_dec_i : in std_logic_vector (7 downto 0);--! decoded model id settings
-- OUTPUTS
......@@ -187,18 +187,18 @@ entity WF_prod_bytes_retriever is
--! the delivery of the last one (MPS)
-- Signal to the WF_tx_serializer
byte_o : out std_logic_vector(7 downto 0) --! output byte to be serialized
byte_o : out std_logic_vector (7 downto 0) --! output byte to be serialized
);
end entity WF_prod_bytes_retriever;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_prod_bytes_retriever is
signal s_base_addr, s_mem_addr_offset : unsigned(8 downto 0);
signal s_base_addr, s_mem_addr_offset : unsigned (8 downto 0);
signal s_byte_index_d_aux : integer range 0 to 15;
signal s_lgth_byte, s_mem_byte, s_slone_byte : std_logic_vector (7 downto 0);
signal s_byte_index_d : std_logic_vector (7 downto 0);
......@@ -206,7 +206,7 @@ architecture rtl of WF_prod_bytes_retriever is
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -218,13 +218,13 @@ begin
--!@brief Instantiation of a Produced Dual Port RAM
Produced_Bytes_From_RAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map(
c_RAM_DATA_LGTH => 8, -- 8 bits: length of data word
c_RAM_ADDR_LGTH => 9) -- 2^9: depth of produced ram
generic map (
g_ram_data_lgth => 8, -- 8 bits: length of data word
g_ram_addr_lgth => 9) -- 2^9: depth of produced ram
-- first 2 bits : identification of memory block
-- remaining 7 : address of a byte inside the blck
-- port A corresponds to: nanoFIP that reads from the Produced ram & B to: WISHBONE that writes
port map(
port map (
clk_porta_i => uclk_i, -- 40 MHz clock
addr_porta_i => s_mem_addr_A, -- address of byte to be read from memory
------------------------------------------------------------------------------------
......@@ -245,7 +245,7 @@ begin
--! has been de-asserted.
Produced_Bytes_From_DATI: WF_prod_bytes_from_dati
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
slone_data_i => slone_data_i,
......@@ -271,8 +271,7 @@ begin
Bytes_Generation: process (var_i, s_byte_index_d, data_length_i, constr_id_dec_i, model_id_dec_i,
nFIP_status_byte_i, mps_status_byte_i, s_slone_byte, s_byte_index_d_aux,
s_mem_byte, s_byte_index_d_aux, nostat_i, byte_being_sent_p_i,
s_lgth_byte, slone_i)
s_mem_byte, nostat_i, byte_being_sent_p_i, s_lgth_byte, slone_i)
begin
......@@ -486,8 +485,8 @@ begin
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_prod_bytes_to_dati.vhd
View file @ 6ead92d5
......@@ -90,7 +90,7 @@ entity WF_prod_bytes_from_dati is
-- nanoFIP User Interface, NON-WISHBONE
slone_data_i : in std_logic_vector (15 downto 0); --! input data bus for stand-alone mode
-- (synchronized with uclk)
-- Signals from the WF_engine_control unit
byte_index_i : in std_logic_vector (7 downto 0); --! index of the byte to be produced
......@@ -106,7 +106,7 @@ end entity WF_prod_bytes_from_dati;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_prod_bytes_from_dati is
......@@ -114,7 +114,7 @@ architecture rtl of WF_prod_bytes_from_dati is
signal s_sampled_data : std_logic_vector (15 downto 0);
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -150,8 +150,8 @@ Sample_DAT_I_bus: process (uclk_i)
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_prod_data_lgth_calc.vhd
View file @ 6ead92d5
......@@ -84,11 +84,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -99,10 +94,10 @@ entity WF_prod_data_lgth_calc is
port (
-- INPUTS
-- nanoFIP WorldFIP Settings (synchronized with uclk)
-- nanoFIP WorldFIP Settings
p3_lgth_i : in std_logic_vector (2 downto 0); --! produced var user-data length
-- User Interface, General signals (synchronized with uclk)
-- User Interface, General signals
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
......@@ -112,21 +107,21 @@ entity WF_prod_data_lgth_calc is
-- OUTPUT
-- Signal to the WF_engine_control and WF_production units
prod_data_length_o : out std_logic_vector(7 downto 0)
prod_data_length_o : out std_logic_vector (7 downto 0)
);
end entity WF_prod_data_lgth_calc;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_prod_data_lgth_calc is
signal s_prod_data_length, s_p3_length_decoded : unsigned(7 downto 0);
signal s_prod_data_length, s_p3_length_decoded : unsigned (7 downto 0);
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -211,8 +206,8 @@ begin
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_prod_permit.vhd
View file @ 6ead92d5
......@@ -79,7 +79,7 @@ entity WF_prod_permit is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
......@@ -97,13 +97,13 @@ end entity WF_prod_permit;
--=================================================================================================
--! architecture declaration
--! architecture declaration
--=================================================================================================
architecture rtl of WF_prod_permit is
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
......@@ -150,8 +150,8 @@ begin
end architecture rtl;
--=================================================================================================
-- architecture end
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_production.vhd
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wf_reset_unit.vhd
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wf_rx_deglitcher.vhd
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wf_rx_deserializer.vhd
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wf_rx_osc.vhd 0 → 100644
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wf_status_bytes_gen.vhd
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wf_tx_osc.vhd 0 → 100644
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This diff is collapsed.
wf_tx_serializer.vhd
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This diff is collapsed.
wf_wb_controller.vhd
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