Commit 4abbe8b9 authored by egousiou's avatar egousiou

wf_engine_control turnaround&silence counter 18 bits instead of 15 (was badly…

wf_engine_control turnaround&silence counter 18 bits instead of 15 (was badly calculated and not respecting 31.25kbps silence time)

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@165 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 8b11d6ea
......@@ -95,6 +95,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! 01/2011 v0.04 EG signals named according to their origin; signals var_rdy (1,2,3),
--! assert_rston_p_o,rst_nfip_and_fd_p_o, nFIP status bits and
--! rx_byte_ready_p_o removed cleaning-up+commenting
--! 02/2011 v0.05 EG session timeout counter added; time counter 18 digits instead of 15
--
---------------------------------------------------------------------------------------------------
--
......@@ -207,18 +208,18 @@ architecture rtl of WF_engine_control is
consume_wait_FSS, consume,
produce_wait_turnar_time, produce);
signal control_st, nx_control_st : control_st_t;
signal s_var_aux, s_var : t_var;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_id_dat_subs_byte : std_logic;
signal s_id_dat_frame_ok, s_cons_wait_FSS, s_consuming, s_prod_wait_turnar_time : std_logic;
signal s_producing, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
signal s_rst_rx_bytes_counter, s_inc_rx_bytes_counter, s_var_identified : std_logic;
signal s_load_time_counter, s_time_c_is_zero, s_session_timedout : std_logic;
signal s_tx_byte_request_accept_p, s_tx_byte_request_accept_p_d1 : std_logic;
signal s_tx_byte_request_accept_p_d2, s_tx_last_byte_p, s_tx_last_byte_p_d : std_logic;
signal s_prod_data_length_match, s_tx_start_prod_p, s_broadcast_var : std_logic;
signal s_time_counter_top, s_turnaround_time, s_silence_time : unsigned (14 downto 0);
signal control_st, nx_control_st : control_st_t;
signal s_var_aux, s_var : t_var;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_id_dat_subs_byte : std_logic;
signal s_id_dat_frame_ok, s_cons_wait_FSS, s_consuming, s_prod_wait_turnar_time : std_logic;
signal s_producing, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
signal s_rst_rx_bytes_counter, s_inc_rx_bytes_counter, s_var_identified : std_logic;
signal s_load_time_counter, s_time_c_is_zero, s_session_timedout : std_logic;
signal s_tx_byte_request_accept_p, s_tx_byte_request_accept_p_d1 : std_logic;
signal s_tx_byte_request_accept_p_d2, s_tx_last_byte_p, s_tx_last_byte_p_d : std_logic;
signal s_prod_data_length_match, s_tx_start_prod_p, s_broadcast_var : std_logic;
signal s_rx_bytes_c, s_prod_bytes_c : unsigned (7 downto 0);
signal s_time_counter_top, s_turnaround_time, s_silence_time : unsigned (17 downto 0);
signal s_tx_byte_index, s_rx_byte_index, s_prod_data_length : std_logic_vector (7 downto 0);
signal s_produce_or_consume : std_logic_vector (1 downto 0);
......@@ -764,7 +765,7 @@ begin
--! states "produce_wait_turnar_time" and "consume_wait_FSS" respectively.
Turnaround_and_Silence_Time_Counter: WF_decr_counter
generic map (g_counter_lgth => 15)
generic map (g_counter_lgth => 18)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......
......@@ -115,10 +115,10 @@ end entity WF_model_constr_decoder;
architecture rtl of WF_model_constr_decoder is
signal s_counter_is_full : std_logic;
signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0);
signal s_counter_is_full : std_logic;
signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0);
--=================================================================================================
......@@ -155,10 +155,10 @@ begin
s_constr_stage1 <= constr_id_i; -- same for the constructor
if s_counter = "01" then
if s_counter = "10" then
model_id_dec_o <= s_model_stage2(3) & s_model_stage1(3) & -- putting together
s_model_stage2(2) & s_model_stage1(2) & -- odd and even bits
s_model_stage2(2) & s_model_stage1(2) & -- even and odd bits
s_model_stage2(1) & s_model_stage1(1) &
s_model_stage2(0) & s_model_stage1(0);
......
......@@ -685,21 +685,27 @@ free_counter: WF_incr_counter
-- Output Signals --
---------------------------------------------------------------------------------------------------
wb_rst_o <= rst_i or s_wb_por;
nFIP_rst_o <= s_intern_rst_from_RSTIN or s_intern_rst_from_var_rst or s_u_por;
wb_rst_o <= rst_i or s_wb_por;
nFIP_rst_o <= s_intern_rst_from_RSTIN or s_intern_rst_from_var_rst or s_u_por;
-- Flip-flop with asynchronous reset to be sure that whenever nanoFIP is reset the user is not
RSTON_Buffering: process (uclk_i, s_u_por, s_intern_rst_from_RSTIN, s_intern_rst_from_var_rst)
begin
if s_intern_rst_from_RSTIN = '1' or s_intern_rst_from_var_rst = '1' or s_u_por = '1' then
rston_o <= '1';
elsif rising_edge (uclk_i) then
rston_o <= not s_rston;
end if;
end process;
Outputs_Buffering: process (uclk_i)
FD_RST_Buffering: process (uclk_i)
begin
if rising_edge (uclk_i) then
rston_o <= not s_rston;
fd_rstn_o <= not (s_FD_rst_from_RSTIN or s_FD_rst_from_var_rst or s_u_por);
fd_rstn_o <= not (s_FD_rst_from_RSTIN or s_FD_rst_from_var_rst or s_u_por);
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
......
......@@ -128,7 +128,7 @@ architecture rtl of WF_rx_osc is
signal s_period_c, s_period, s_jitter : unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_half_period, s_one_forth_period : unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_counter_reinit, s_counter_is_full : std_logic;
signal s_reinit_counter, s_counter_is_full : std_logic;
signal s_adjac_bits_window, s_signif_edge_window : std_logic;
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
signal s_bit_clk, s_bit_clk_d1, s_manch_clk, s_manch_clk_d1 : std_logic;
......@@ -164,7 +164,7 @@ begin
generic map (g_counter_lgth => c_PERIODS_COUNTER_LENGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_counter_reinit,
reinit_counter_i => s_reinit_counter,
incr_counter_i => '1',
counter_is_full_o => open,
------------------------------------------
......@@ -176,7 +176,7 @@ begin
-- if the rx_osc_rst_i is active or
-- if an edge is detected in the expected window or
-- if it fills up
s_counter_reinit <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i) or s_counter_is_full;
s_reinit_counter <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i) or s_counter_is_full;
......
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