Commit 0325ed9a authored by egousiou's avatar egousiou

no manch. code violations checked finally! we believe that the crc will show…

no manch. code violations checked finally! we believe that the crc will show errors that may have occurred because of manch.encoding.
corrections in detecting errors if bits are not multiple of 8.



git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@207 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 7d13b53b
......@@ -326,7 +326,7 @@ architecture struc of nanofip is
-- WF_production outputs
signal s_byte_to_tx : std_logic_vector (7 downto 0);
-- WF_fd_transmitter outputs
signal s_tx_last_byte_p : std_logic;
signal s_tx_last_byte_p, s_tx_completed_p : std_logic;
-- WF_engine_control outputs
signal s_tx_start_p, s_tx_request_byte_p, s_byte_request_accepted_p : std_logic;
signal s_rx_rst : std_logic;
......@@ -378,25 +378,25 @@ TP14 <= s_rx_fss_crc_fes_manch_ok_p;
---------------------------------------------------------------------------------------------------
Consumption: WF_consumption
port map (
uclk_i => uclk_i,
slone_i => slone_i,
nfip_rst_i => s_nfip_intern_rst,
subs_i => subs_i,
rx_byte_i => s_rx_byte,
rx_byte_ready_p_i => s_rx_byte_ready_p,
rx_fss_crc_fes_manch_ok_p_i => s_rx_fss_crc_fes_manch_ok_p,
rx_crc_or_manch_wrong_p_i => s_rx_crc_or_manch_wrong_p,
wb_clk_i => wclk_i,
wb_adr_i => adr_i (8 downto 0),
var_i => s_var,
byte_index_i => s_prod_cons_byte_index,
uclk_i => uclk_i,
slone_i => slone_i,
nfip_rst_i => s_nfip_intern_rst,
subs_i => subs_i,
rx_byte_i => s_rx_byte,
rx_byte_ready_p_i => s_rx_byte_ready_p,
rx_fss_crc_fes_ok_p_i => s_rx_fss_crc_fes_manch_ok_p,
rx_crc_wrong_p_i => s_rx_crc_or_manch_wrong_p,
wb_clk_i => wclk_i,
wb_adr_i => adr_i (8 downto 0),
var_i => s_var,
byte_index_i => s_prod_cons_byte_index,
-------------------------------------------------------------
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
data_o => dat_o,
nfip_status_r_tler_p_o => s_nfip_status_r_tler,
assert_rston_p_o => s_assert_RSTON_p,
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p);
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
data_o => dat_o,
nfip_status_r_tler_p_o => s_nfip_status_r_tler,
assert_rston_p_o => s_assert_RSTON_p,
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p);
-------------------------------------------------------------
......@@ -406,17 +406,17 @@ TP14 <= s_rx_fss_crc_fes_manch_ok_p;
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver: WF_fd_receiver
port map (
uclk_i => uclk_i,
rate_i => rate_i,
fd_rxd_a_i => fd_rxd_i,
nfip_rst_i => s_nfip_intern_rst,
rx_rst_i => s_rx_rst,
uclk_i => uclk_i,
rate_i => rate_i,
fd_rxd_a_i => fd_rxd_i,
nfip_rst_i => s_nfip_intern_rst,
rx_rst_i => s_rx_rst,
-------------------------------------------------------------
rx_byte_o => s_rx_byte,
rx_byte_ready_p_o => s_rx_byte_ready_p,
rx_fss_crc_fes_manch_ok_p_o => s_rx_fss_crc_fes_manch_ok_p,
rx_fss_received_p_o => s_rx_fss_received_p,
rx_crc_or_manch_wrong_p_o => s_rx_crc_or_manch_wrong_p);
rx_byte_o => s_rx_byte,
rx_byte_ready_p_o => s_rx_byte_ready_p,
rx_fss_crc_fes_ok_p_o => s_rx_fss_crc_fes_manch_ok_p,
rx_fss_received_p_o => s_rx_fss_received_p,
rx_crc_wrong_p_o => s_rx_crc_or_manch_wrong_p);
-------------------------------------------------------------
......@@ -471,16 +471,17 @@ TP14 <= s_rx_fss_crc_fes_manch_ok_p;
nfip_rst_i => s_nfip_intern_rst,
tx_byte_i => s_byte_to_tx,
tx_byte_request_accept_p_i => s_byte_request_accepted_p,
tx_last_byte_p_i => s_tx_last_byte_p,
tx_last_data_byte_p_i => s_tx_last_byte_p,
tx_start_p_i => s_tx_start_p,
-------------------------------------------------------------
tx_byte_request_p_o => s_tx_request_byte_p,
tx_completed_p_o => s_tx_completed_p,
tx_data_o => fd_txd_o,
tx_enable_o => fd_txena_o,
tx_clk_o => fd_txck_o);
-------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- WF_engine_control --
......@@ -491,11 +492,12 @@ TP14 <= s_rx_fss_crc_fes_manch_ok_p;
uclk_i => uclk_i,
nfip_rst_i => s_nfip_intern_rst,
tx_byte_request_p_i => s_tx_request_byte_p,
tx_completed_p_i => s_tx_completed_p,
rx_fss_received_p_i => s_rx_fss_received_p,
rx_byte_i => s_rx_byte,
rx_byte_ready_p_i => s_rx_byte_ready_p,
rx_fss_crc_fes_manch_ok_p_i => s_rx_fss_crc_fes_manch_ok_p,
rx_crc_or_manch_wrong_p_i => s_rx_crc_or_manch_wrong_p,
rx_fss_crc_fes_ok_p_i => s_rx_fss_crc_fes_manch_ok_p,
rx_crc_wrong_p_i => s_rx_crc_or_manch_wrong_p,
rate_i => rate_i,
subs_i => subs_i,
p3_lgth_i => p3_lgth_i,
......@@ -505,7 +507,7 @@ TP14 <= s_rx_fss_crc_fes_manch_ok_p;
var_o => s_var,
tx_start_p_o => s_tx_start_p,
tx_byte_request_accept_p_o => s_byte_request_accepted_p,
tx_last_byte_p_o => s_tx_last_byte_p,
tx_last_data_byte_p_o => s_tx_last_byte_p,
prod_cons_byte_index_o => s_prod_cons_byte_index,
prod_data_lgth_o => s_prod_data_lgth,
rx_rst_o => s_rx_rst);
......
......@@ -32,7 +32,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o the Control, PDU_TYPE and Length bytes;
--! the bytes are received from the the WF_consumption unit.
--! o the CRC, FSS, FES bytes and the Manchester encoding;
--! the rx_fss_crc_fes_manch_ok_p_i pulse from the WF_fd_receiver unit groups
--! the rx_fss_crc_fes_ok_p_i pulse from the WF_fd_receiver unit groups
--! these checks.
--!
--! Then, according to the consumed variable that has been received (var_1, var_2,
......@@ -108,49 +108,49 @@ entity WF_cons_outcome is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode
-- nanoFIP WorldFIP Settings
subs_i : in std_logic_vector (7 downto 0);--! subscriber number coding
subs_i : in std_logic_vector (7 downto 0);--! subscriber number coding
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_fd_receiver unit
rx_fss_crc_fes_manch_ok_p_i : in std_logic; --! indication of a frame with correct FSS, FES, CRC
--! and manch. encoding; pulse upon FES detection
rx_fss_crc_fes_ok_p_i : in std_logic; --! indication of a frame with correct FSS, FES, CRC
--! and manch. encoding; pulse upon FES detection
rx_crc_or_manch_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC or manch.
-- pulse upon FES detection
rx_crc_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC or manch.
-- pulse upon FES detection
-- Signals from the WF_consumption unit
cons_ctrl_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT Control byte
cons_lgth_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT Length byte
cons_pdu_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT PDU_TYPE byte
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);--! received var_rst RP_DAT, 1st data-byte
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);--! received var_rst RP_DAT, 2nd data-byte
cons_ctrl_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT Control byte
cons_lgth_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT Length byte
cons_pdu_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT PDU_TYPE byte
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);--! received var_rst RP_DAT, 1st data-byte
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);--! received var_rst RP_DAT, 2nd data-byte
-- Signals from the WF_engine_control unit
rx_byte_index_i : in std_logic_vector (7 downto 0);--! index of byte being received
var_i : in t_var; --! variable type that is being treated
rx_byte_index_i : in std_logic_vector (7 downto 0);--! index of byte being received
var_i : in t_var; --! variable type that is being treated
-- OUTPUTS
-- nanoFIP User Interface, NON-WISHBONE outputs
var1_rdy_o : out std_logic;--! signals new data is received and can safely be read
var2_rdy_o : out std_logic;--! signals new data is received and can safely be read
var1_rdy_o : out std_logic;--! signals new data is received and can safely be read
var2_rdy_o : out std_logic;--! signals new data is received and can safely be read
-- Signal to the WF_status_bytes_gen unit
nfip_status_r_tler_p_o : out std_logic;--! received PDU_TYPE or Length error
--! nanoFIP status byte bit 4
nfip_status_r_tler_p_o : out std_logic;--! received PDU_TYPE or Length error
--! nanoFIP status byte bit 4
-- Signals to the WF_reset_unit
assert_rston_p_o : out std_logic;--! indicates that a var_rst with its 2nd data-byte
--! containing the station's address has been
--! correctly received
assert_rston_p_o : out std_logic;--! indicates that a var_rst with its 2nd data-byte
--! containing the station's address has been
--! correctly received
rst_nfip_and_fd_p_o : out std_logic --! indicates that a var_rst with its 1st data-byte
rst_nfip_and_fd_p_o : out std_logic --! indicates that a var_rst with its 1st data-byte
--! containing the station's address has been
--! correctly received
);
......@@ -177,18 +177,18 @@ begin
--! respect to the Ctrl, PDU_TYPE and Length bytes as well as to the CRC, FSS, FES and to the
--! Manchester encoding. The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that
--! arrive at the beginning of a frame, have been registered and keep their values until the end
--! of it. The signal rx_fss_crc_fes_manch_ok_p_i, is a pulse at the end of the FES that combines
--! of it. The signal rx_fss_crc_fes_ok_p_i, is a pulse at the end of the FES that combines
--! the checks of the FSS, CRC, FES and of the manch. encoding.
--! To check the correctness of the the RP_DAT.Data.Length byte, we compare it to the value of the
--! rx_byte_index, when the FES is detected (pulse rx_fss_crc_fes_manch_ok_p_i).
--! rx_byte_index, when the FES is detected (pulse rx_fss_crc_fes_ok_p_i).
--! Note: In addition to the &Length bytes, the rx_byte_index also counts the Control, PDU_TYPE,
--! Length, the 2 CRC and the FES bytes (and counting starts from 0!).
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! The same process is also used for the generation of the of the nanoFIP status byte, bit 4, that
--! indicates a received Control or PDU_TYPE byte error or a Length byte incoherency in a consumed
--! RP_DAT frame.
--! Note: The end of a frame is marked by either the signal rx_fss_crc_fes_manch_ok_p_i or by the
--! rx_crc_or_manch_wrong_p_i.
--! Note: The end of a frame is marked by either the signal rx_fss_crc_fes_ok_p_i or by the
--! rx_crc_wrong_p_i.
Frame_Validation: process (uclk_i)
begin
......@@ -201,7 +201,7 @@ begin
if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) then -- only consumed RP_DATs
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if (rx_fss_crc_fes_manch_ok_p_i = '1') and -- FSS CRC FES Manch. check
if (rx_fss_crc_fes_ok_p_i = '1') and -- FSS CRC FES Manch. check
(cons_ctrl_byte_i = c_RP_DAT_CTRL_BYTE) and -- CTRL byte check
(cons_pdu_byte_i = c_PROD_CONS_PDU_TYPE_BYTE) and -- PDU_TYPE byte check
(unsigned(rx_byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5)) then --LGTH byte check
......@@ -212,10 +212,10 @@ begin
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if ((rx_fss_crc_fes_manch_ok_p_i = '1') or (rx_crc_or_manch_wrong_p_i = '1')) and-- end of frame
((cons_ctrl_byte_i /= c_RP_DAT_CTRL_BYTE) or -- CTRL byte check
((cons_pdu_byte_i /= c_PROD_CONS_PDU_TYPE_BYTE) or -- PDU_TYPE byte check
(unsigned(rx_byte_index_i ) /= (unsigned(cons_lgth_byte_i) + 5)))) then -- LGTH byte check
if ((rx_fss_crc_fes_ok_p_i = '1') or (rx_crc_wrong_p_i = '1')) and-- end of frame
((cons_ctrl_byte_i /= c_RP_DAT_CTRL_BYTE) or -- CTRL byte check
((cons_pdu_byte_i /= c_PROD_CONS_PDU_TYPE_BYTE) or -- PDU_TYPE byte check
(unsigned(rx_byte_index_i ) /= (unsigned(cons_lgth_byte_i) + 5)))) then -- LGTH byte check
nfip_status_r_tler_p_o <= '1';
else
......
......@@ -147,8 +147,8 @@ entity WF_consumption is
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
rx_crc_or_manch_wrong_p_i : in std_logic;
rx_fss_crc_fes_ok_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -246,25 +246,25 @@ begin
Consumption_Outcome : WF_cons_outcome
port map (
uclk_i => uclk_i,
slone_i => slone_i,
subs_i => subs_i,
nfip_rst_i => nfip_rst_i,
rx_fss_crc_fes_manch_ok_p_i => rx_fss_crc_fes_manch_ok_p_i,
rx_crc_or_manch_wrong_p_i => rx_crc_or_manch_wrong_p_i,
var_i => var_i,
rx_byte_index_i => byte_index_i,
cons_ctrl_byte_i => s_cons_ctrl_byte,
cons_pdu_byte_i => s_cons_pdu_byte,
cons_lgth_byte_i => s_cons_lgth_byte,
cons_var_rst_byte_1_i => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_i => s_cons_var_rst_byte_2,
uclk_i => uclk_i,
slone_i => slone_i,
subs_i => subs_i,
nfip_rst_i => nfip_rst_i,
rx_fss_crc_fes_ok_p_i => rx_fss_crc_fes_ok_p_i,
rx_crc_wrong_p_i => rx_crc_wrong_p_i,
var_i => var_i,
rx_byte_index_i => byte_index_i,
cons_ctrl_byte_i => s_cons_ctrl_byte,
cons_pdu_byte_i => s_cons_pdu_byte,
cons_lgth_byte_i => s_cons_lgth_byte,
cons_var_rst_byte_1_i => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_i => s_cons_var_rst_byte_2,
--------------------------------------------------------
var1_rdy_o => var1_rdy_o,
var2_rdy_o => var2_rdy_o,
nfip_status_r_tler_p_o => nfip_status_r_tler_p_o,
assert_rston_p_o => assert_rston_p_o,
rst_nfip_and_fd_p_o => rst_nfip_and_fd_p_o);
var1_rdy_o => var1_rdy_o,
var2_rdy_o => var2_rdy_o,
nfip_status_r_tler_p_o => nfip_status_r_tler_p_o,
assert_rston_p_o => assert_rston_p_o,
rst_nfip_and_fd_p_o => rst_nfip_and_fd_p_o);
--------------------------------------------------------
......
This diff is collapsed.
......@@ -105,36 +105,36 @@ entity WF_fd_receiver is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHZ clock
uclk_i : in std_logic; --! 40 MHZ clock
-- nanoFIP WorldFIP Settings
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- nanoFIP FIELDRIVE
fd_rxd_a_i : in std_logic; --! receiver data
fd_rxd_a_i : in std_logic; --! receiver data
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_engine_control unit
rx_rst_i : in std_logic; --! reset during production or
--! reset pulse when consumption is lasting more than
--! expected (ID_DAT > 8 bytes, RP_DAT > 134 bytes)
rx_rst_i : in std_logic; --! reset during production or
--! reset pulse when consumption is lasting more than
--! expected (ID_DAT > 8 bytes, RP_DAT > 134 bytes)
-- OUTPUTS
-- Signals to the WF_engine_control and WF_consumption
rx_byte_o : out std_logic_vector (7 downto 0); --! retrieved data byte
rx_byte_ready_p_o : out std_logic;--! pulse indicating a new retrieved data byte
rx_fss_crc_fes_manch_ok_p_o : out std_logic;--! indication of a frame (ID_DAT or RP_DAT) with
--! correct FSS, FES, CRC and manch. encoding
rx_byte_o : out std_logic_vector (7 downto 0); --! retrieved data byte
rx_byte_ready_p_o : out std_logic;--! pulse indicating a new retrieved data byte
rx_fss_crc_fes_ok_p_o : out std_logic;--! indication of a frame (ID_DAT or RP_DAT) with
--! correct FSS, FES, CRC and manch. encoding
-- Signals to the WF_engine_control
rx_fss_received_p_o : out std_logic;--! pulse after the reception of a correct FSS(ID/RP)
rx_fss_received_p_o : out std_logic;--! pulse after the reception of a correct FSS(ID/RP)
-- Signal to the WF_engine_control and the WF_production units
rx_crc_or_manch_wrong_p_o : out std_logic --! indication of a wrong CRC or manch. encoding on
--!a ID_DAT or RP_DAT;pulse after the FES detection
rx_crc_wrong_p_o : out std_logic --! indication of a wrong CRC or manch. encoding on
--!a ID_DAT or RP_DAT;pulse after the FES detection
);
end entity WF_fd_receiver;
......@@ -147,7 +147,7 @@ end entity WF_fd_receiver;
architecture struc of WF_fd_receiver is
signal s_rx_osc_rst, s_adjac_bits_window, s_signif_edge_window : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p, s_rxd_filtered, s_rx_code_viol_p : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p, s_rxd_filtered : std_logic;
signal s_rxd_filtered_edge_p, s_rxd_filtered_f_edge_p, s_rxd_filtered_r_edge_p : std_logic;
......@@ -194,7 +194,6 @@ begin
------------------------------------------------------
rx_manch_clk_p_o => s_sample_manch_bit_p,
rx_bit_clk_p_o => s_sample_bit_p,
rx_manch_code_viol_p_o => s_rx_code_viol_p,
rx_signif_edge_window_o => s_signif_edge_window,
rx_adjac_bits_window_o => s_adjac_bits_window);
-----------------------------------------------------
......@@ -209,24 +208,23 @@ begin
FIELDRIVE_Receiver_Deserializer: WF_rx_deserializer
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
rx_rst_i => rx_rst_i,
manch_code_viol_p_i => s_rx_code_viol_p,
sample_bit_p_i => s_sample_bit_p,
sample_manch_bit_p_i => s_sample_manch_bit_p,
signif_edge_window_i => s_signif_edge_window,
adjac_bits_window_i => s_adjac_bits_window,
fd_rxd_f_edge_p_i => s_rxd_filtered_f_edge_p,
fd_rxd_r_edge_p_i => s_rxd_filtered_r_edge_p,
fd_rxd_i => s_rxd_filtered,
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
rx_rst_i => rx_rst_i,
sample_bit_p_i => s_sample_bit_p,
sample_manch_bit_p_i => s_sample_manch_bit_p,
signif_edge_window_i => s_signif_edge_window,
adjac_bits_window_i => s_adjac_bits_window,
fd_rxd_f_edge_p_i => s_rxd_filtered_f_edge_p,
fd_rxd_r_edge_p_i => s_rxd_filtered_r_edge_p,
fd_rxd_i => s_rxd_filtered,
------------------------------------------------------
byte_ready_p_o => rx_byte_ready_p_o,
byte_o => rx_byte_o,
fss_crc_fes_manch_ok_p_o => rx_fss_crc_fes_manch_ok_p_o,
rx_osc_rst_o => s_rx_osc_rst,
fss_received_p_o => rx_fss_received_p_o,
crc_or_manch_wrong_p_o => rx_crc_or_manch_wrong_p_o);
byte_ready_p_o => rx_byte_ready_p_o,
byte_o => rx_byte_o,
fss_crc_fes_ok_p_o => rx_fss_crc_fes_ok_p_o,
rx_osc_rst_o => s_rx_osc_rst,
fss_received_p_o => rx_fss_received_p_o,
crc_wrong_p_o => rx_crc_wrong_p_o);
------------------------------------------------------
......
......@@ -121,13 +121,16 @@ entity WF_fd_transmitter is
tx_byte_i : in std_logic_vector (7 downto 0); --! byte to be delivered
-- Signals from the WF_engine_control
tx_byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
tx_last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
tx_start_p_i : in std_logic; --! indication for the start of the production
tx_byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
tx_last_data_byte_p_i : in std_logic; --! indication of he last data byte
-- (CRC, FES not included)
-- OUTPUTS
-- Signal to the WF_engine_control
tx_completed_p_o : out std_logic;
tx_byte_request_p_o : out std_logic;--! request for a new byte to be transmitted; pulse
--! at the end of the transmission of a previous byte
......@@ -186,10 +189,11 @@ begin
tx_start_p_i => tx_start_p_i,
byte_request_accept_p_i => tx_byte_request_accept_p_i,
byte_i => tx_byte_i,
last_byte_p_i => tx_last_byte_p_i,
last_byte_p_i => tx_last_data_byte_p_i,
tx_clk_p_buff_i => s_tx_clk_p_buff,
-----------------------------------------------
byte_request_p_o => tx_byte_request_p_o,
tx_byte_request_p_o => tx_byte_request_p_o,
tx_completed_p_o => tx_completed_p_o,
tx_data_o => tx_data_o,
tx_osc_rst_p_o => s_tx_osc_rst_p,
tx_enable_o => tx_enable_o );
......
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This diff is collapsed.
......@@ -70,6 +70,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 12/2010 v0.03 EG code cleaned-up
--! -> 01/2011 v0.031 EG rxd_edge_i became fd_rxd_edge_p_i; small correctiond on comments
--! -> 02/2011 v0.04 EG 2 units WF_rx_osc and WF_tx_osc; process replaced by WF_incr_counter
--! check for code violations removed completely
--
---------------------------------------------------------------------------------------------------
--
......@@ -103,7 +104,7 @@ entity WF_rx_osc is
-- OUTPUTS
-- Signals to the WF_rx_deserializer
rx_manch_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! o on a significant edge
--! o on a significant edge
--! o between adjacent bits
--! ____|-|___|-|___|-|___
......@@ -111,8 +112,6 @@ entity WF_rx_osc is
--! o between adjacent bits
--! __________|-|_________
rx_manch_code_viol_p_o : out std_logic; --! pulse upon manch. code violation detection
rx_signif_edge_window_o : out std_logic; --! time window where a significant edge is expected
rx_adjac_bits_window_o : out std_logic --! time window where a transition between adjacent
......@@ -212,7 +211,6 @@ begin
s_manch_clk_d1 <= '0';
s_signif_edge_found <= '0';
s_adjac_bits_edge_found <= '0';
rx_manch_code_viol_p_o <= '0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
......@@ -224,7 +222,6 @@ begin
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_signif_edge_found <= '1'; -- indication that the edge was found
s_adjac_bits_edge_found <= '0';
rx_manch_code_viol_p_o <= '0';
-- if a significant edge is not found where expected (code violation), the rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
......@@ -232,8 +229,7 @@ begin
s_manch_clk <= not s_manch_clk;
s_adjac_bits_edge_found <= '0'; -- re-initialization before the
-- next cycle
rx_manch_code_viol_p_o <= '1';
-- next cycle
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
......@@ -248,8 +244,6 @@ begin
s_signif_edge_found <= '0'; -- re-initialization before next cycle
rx_manch_code_viol_p_o <= '0';
-- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right
-- after the end of it
......@@ -259,12 +253,7 @@ begin
s_bit_clk <= not s_bit_clk;
s_signif_edge_found <= '0'; -- re-initialization before next cycle
rx_manch_code_viol_p_o <= '0';
else
rx_manch_code_viol_p_o <= '0';
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_manch_clk_d1 <= s_manch_clk;
......
......@@ -113,7 +113,8 @@ entity WF_tx_serializer is
-- Signals from the WF_engine_control unit
tx_start_p_i : in std_logic; --! indication for the start of the production
byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
last_byte_p_i : in std_logic; --! indication of the last data byte
-- (CRC, FES not included)
-- Signal from the WF_tx_osc
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
......@@ -123,7 +124,8 @@ entity WF_tx_serializer is
-- OUTPUTS
-- Signal to the WF_engine_control unit
byte_request_p_o : out std_logic;
tx_byte_request_p_o : out std_logic;
tx_completed_p_o : out std_logic;
-- Signal to the WF_tx_osc unit
tx_osc_rst_p_o : out std_logic;
......@@ -223,74 +225,73 @@ begin
case tx_state is
when idle =>
if tx_start_p_i = '1' then
nx_tx_state <= sync_to_txck;
else
nx_tx_state <= idle;
end if;
if tx_start_p_i = '1' then
nx_tx_state <= sync_to_txck;
else
nx_tx_state <= idle;
end if;
when sync_to_txck =>
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4) = '1' then
nx_tx_state <= send_fss;
if s_session_timedout = '1' then
nx_tx_state <= idle;
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
elsif tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4) = '1' then
nx_tx_state <= send_fss;
else
nx_tx_state <= sync_to_txck;
end if;
else
nx_tx_state <= sync_to_txck;
end if;
when send_fss =>
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1') then
nx_tx_state <= send_data_byte;
if s_session_timedout = '1' then
nx_tx_state <= idle;
elsif (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1') then
nx_tx_state <= send_data_byte;
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= send_fss;
end if;
else
nx_tx_state <= send_fss;
end if;
when send_data_byte =>
if last_byte_p_i = '1' then
nx_tx_state <= send_crc_bytes;
if s_session_timedout = '1' then
nx_tx_state <= idle;
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
elsif last_byte_p_i = '1' then
nx_tx_state <= send_crc_bytes;
else
nx_tx_state <= send_data_byte;
end if;
else
nx_tx_state <= send_data_byte;
end if;
when send_crc_bytes =>
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
nx_tx_state <= send_fes; -- state change early enough (tx_clk_p_buff_i(2))
if s_session_timedout = '1' then
nx_tx_state <= idle;
elsif (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
nx_tx_state <= send_fes; -- state change early enough (tx_clk_p_buff_i(2))
-- for the Outgoing_Bits_Index, that is loaded on
-- tx_clk_p_buff_i(3), to get the 31 as top value
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= send_crc_bytes;
end if;
else
nx_tx_state <= send_crc_bytes;
end if;
when send_fes =>
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
nx_tx_state <= stop_transmission; -- state change early enough (tx_clk_p_buff_i(2))
if s_session_timedout = '1' then
nx_tx_state <= idle;
elsif (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
nx_tx_state <= stop_transmission; -- state change early enough (tx_clk_p_buff_i(2))
-- for the Outgoing_Bits_Index that is loaded on
-- tx_clk_p_buff_i(3) to get the 15 as top value
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= send_fes;
end if;
else
nx_tx_state <= send_fes;
end if;
when stop_transmission =>
......@@ -592,7 +593,9 @@ Input_Byte_Retrieval: process (uclk_i)
tx_osc_rst_p_o <= s_session_timedout;
byte_request_p_o <= s_sending_data and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4);
tx_completed_p_o <= s_stop_transmission and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2);
tx_byte_request_p_o <= s_sending_data and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4);
-- request for a new byte from the WF_prod_bytes_retriever unit (passing from WF_engine_control)
......
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