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Commit e9ad5e92 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: several fixes to make SPEC+SVEC wr_node_demo, as well as 'top' testbench to work

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.gitignore
View file @ e9ad5e92
......@@ -64,7 +64,6 @@ _xmsgs
*.psr
*.xdl
*.orig
*.ram
pa.fromNcd.tcl
pa.fromNetlist.tcl
planAhead_run_*
......
hdl/sw/debug-test/debug-test.ram 0 → 100644
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hdl/syn/spec/wr_node_demo/spec_wr_node_demo.xise deleted 100644 → 0
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hdl/syn/svec/wr_node_demo/svec_wr_node_demo.xise deleted 100644 → 0
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hdl/testbench/top/Manifest.py
View file @ e9ad5e92
sim_tool = "modelsim"
top_module="main"
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../include/wb +incdir+../include/vme64x_bfm +incdir+../include +incdir+../../sim"
vcom_opt="-mixedsvvh l"
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
syn_device="xc6slx150t"
include_dirs=["../../sim", "../include", "../include/vme64x_bfm"]
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx150t"
vcom_opt = "-mixedsvvh"
files = [ "main.sv" ]
include_dirs = [
"../include",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/",
"../../ip_cores/general-cores/sim/",
]
modules = { "local" : [ "../../rtl" ] }
files = [
"main.sv",
]
modules = {
"local" : [
"../../rtl",
"../../ip_cores/etherbone-core",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
],
}
hdl/testbench/top/run.do
View file @ e9ad5e92
vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include +incdir+../include +incdir+../../sim
vsim -L unisim work.main -novopt
set StdArithNoWarnings 1
......
hdl/top/spec/wr_node_demo/Manifest.py
View file @ e9ad5e92
......@@ -5,5 +5,8 @@ fetchto = "../../ip_cores"
modules = {
"local" : [ "../../../rtl/wrnc",
"../node_template",
"../../../ip_cores/wr-cores",
"../../../ip_cores/etherbone-core",
"../../../ip_cores/general-cores",
"../../../ip_cores/gn4124-core" ],
}
hdl/top/spec/wr_node_demo/spec_top.ucf
View file @ e9ad5e92
......@@ -8,11 +8,11 @@ NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_gtp_n_i" LOC = D11;
#NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_gtp_p_i" LOC = C11;
#NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
......@@ -205,10 +205,10 @@ NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
#NET "uart_rxd_i" LOC= A2;
#NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
#NET "uart_txd_o" LOC= B2;
#NET "uart_txd_o" IOSTANDARD=LVCMOS25;
net "leds_n_o[0]" LOC= C20;
net "leds_n_o[1]" LOC= F18;
......@@ -222,7 +222,7 @@ net "leds_n_o[3]" IOSTANDARD=LVCMOS18;
# GN4124
NET "l_rst_n" TIG;
NET "*/U_GN4124_Core/rst_*" TIG;
NET "U_Node_Template/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
......@@ -232,7 +232,7 @@ NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk;
NET "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback;
NET "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
hdl/top/spec/wr_node_demo/spec_top.vhd
View file @ e9ad5e92
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2015-07-24
-- Last update: 2018-03-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -68,9 +68,6 @@ entity spec_top is
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
L_RST_N: in std_logic; -- Gennum Local bus reset
-- general purpose interface
......@@ -143,13 +140,6 @@ entity spec_top is
sfp_los_i : in std_logic := '0';
-------------------------------------------------------------------------
-- WR core UART
-------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
button1_i : in std_logic := '1';
button2_i : in std_logic := '1';
......@@ -244,8 +234,6 @@ begin
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
l_rst_n => l_rst_n,
gpio => gpio,
......@@ -284,18 +272,18 @@ begin
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_b => sfp_mod_def0_b,
sfp_mod_def0_i => sfp_mod_def0_b,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_b => sfp_rate_select_b,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
fmc0_dp_wb_o => fmc_dp_wb_out,
fmc0_dp_wb_i => fmc_dp_wb_in,
fmc0_host_wb_o => fmc_dp_wb_out,
fmc0_host_wb_i => fmc_dp_wb_in,
dp_master_i => (others => cc_dummy_master_in),
fmc0_clk_aux_i => '0',
fmc0_host_irq_i => '0'
......
hdl/top/svec/wr_node_demo/Manifest.py
View file @ e9ad5e92
......@@ -5,5 +5,8 @@ fetchto = "../../ip_cores"
modules = {
"local" : [ "../../../rtl/wrnc",
"../node_template",
"../../../ip_cores/wr-cores",
"../../../ip_cores/etherbone-core",
"../../../ip_cores/general-cores",
"../../../ip_cores/vme64x-core" ],
}
hdl/top/svec/wr_node_demo/svec_top.vhd
View file @ e9ad5e92
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2015-05-29
-- Last update: 2018-03-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -210,7 +210,8 @@ architecture rtl of svec_top is
cpu_count => 2,
cpu_memsizes => (32768, 32768, 0, 0, 0, 0, 0, 0),
hmq_config => c_hmq_config,
rmq_config => c_rmq_config
rmq_config => c_rmq_config,
shared_mem_size => 8192
);
signal clk_sys : std_logic;
......
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