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Mock Turtle
Commit ccfcdcee authored by Dimitris Lampridis's avatar Dimitris Lampridis
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doc: update HDL documentation to reflect latest code changes

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doc/hdl/index.rst
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......@@ -181,6 +181,14 @@ A VHDL component declaration for the MT top-level entity is included in the **mo
generic (
g_CONFIG : t_mt_config := c_DEFAULT_MT_CONFIG;
g_SYSTEM_CLOCK_FREQ : integer := 62500000;
g_CPU0_IRAM_INITF : string := "none";
g_CPU1_IRAM_INITF : string := "none";
g_CPU2_IRAM_INITF : string := "none";
g_CPU3_IRAM_INITF : string := "none";
g_CPU4_IRAM_INITF : string := "none";
g_CPU5_IRAM_INITF : string := "none";
g_CPU6_IRAM_INITF : string := "none";
g_CPU7_IRAM_INITF : string := "none";
g_WITH_WHITE_RABBIT : boolean := FALSE);
port (
clk_i : in std_logic;
......@@ -191,10 +199,8 @@ A VHDL component declaration for the MT top-level entity is included in the **mo
dp_master_i : in t_wishbone_master_in_array(0 to g_CONFIG.cpu_count-1) := (others => c_DUMMY_WB_MASTER_IN);
host_slave_i : in t_wishbone_slave_in;
host_slave_o : out t_wishbone_slave_out;
rmq_src_o : out t_mt_stream_source_out_array2d;
rmq_src_i : in t_mt_stream_source_in_array2d := (others => (others => c_MT_DUMMY_SOURCE_IN));
rmq_snk_o : out t_mt_stream_sink_out_array2d;
rmq_snk_i : in t_mt_stream_sink_in_array2d := (others => (others => c_MT_DUMMY_SINK_IN));
rmq_endpoint_o : out t_mt_rmq_endpoint_iface_out;
rmq_endpoint_i : in t_mt_rmq_endpoint_iface_in := c_MT_RMQ_ENDPOINT_IFACE_IN_DEFAULT_VALUE;
clk_ref_i : in std_logic := '0';
tm_i : in t_mt_timing_if := c_DUMMY_MT_TIMING;
gpio_o : out std_logic_vector(31 downto 0);
......@@ -219,6 +225,9 @@ g_SYSTEM_CLOCK_FREQ
keeping track of time when `White Rabbit Support`_ is not enabled and it is also used by
software to calculate delays.
g_CPUx_IRAM_INITF
Memory initialization file for CPUx, to be included in the FPGA bitstream, if any.
g_WITH_WHITE_RABBIT
Controls enabling of `White Rabbit Support`_.
......@@ -293,14 +302,36 @@ host_slave_i, host_slave_o
('1', '0', '0', '0', c_DUMMY_WB_DATA);
constant c_DUMMY_WB_MASTER_IN : t_wishbone_master_in := c_DUMMY_WB_SLAVE_OUT;
rmq_src_o, rmq_src_i, rmq_snk_o, rmq_snk_i
rmq_endpoint_o, rmq_endpoint_i
These ports provide the bidirectional interface from each of the configured soft CPUs to their
repspective remote message queue(s).
repspective end-points.
**t_mt_rmq_endpoint_iface_out** and **t_mt_rmq_endpoint_iface_in** are VHDL record types defined in
the **mock_turtle_pkg**::
type t_mt_rmq_endpoint_iface_out is record
src_out : t_mt_stream_source_out_array2d;
snk_out : t_mt_stream_sink_out_array2d;
src_config_out : t_mt_stream_config_out_array2d;
snk_config_out : t_mt_stream_config_out_array2d;
end record;
type t_mt_rmq_endpoint_iface_in is record
src_in : t_mt_stream_source_in_array2d;
snk_in : t_mt_stream_sink_in_array2d;
src_config_in : t_mt_stream_config_in_array2d;
snk_config_in : t_mt_stream_config_in_array2d;
end record;
*src_out*, *src_in*, *snk_out* and *snk_in* are used to transfer data to/from the end-point, while
the *config* signals are used to configure the end-points (e.g. to set the network destination for
the data).
**t_mt_stream_source_out_array2d**, **t_mt_stream_source_in_array2d**,
**t_mt_stream_sink_out_array2d** and **t_mt_stream_sink_in_array2d** are two-dimensional arrays of
**t_mt_stream_sink_out_array2d**, **t_mt_stream_sink_in_array2d**,
**t_mt_stream_config_out_array2d** and **t_mt_stream_config_in_array2d** are two-dimensional arrays of
VHDL records, defined in **mock_turtle_pkg** (for the first array dimension) and **mt_mqueue_pkg**
(for the second array dimension and for the records)::
(for the second array dimension and for the records themselves)::
subtype t_maxcpu_range is natural range 0 to 7;
subtype t_maxslot_range is natural range 0 to 7;
......@@ -314,6 +345,11 @@ VHDL records, defined in **mock_turtle_pkg** (for the first array dimension) and
subtype t_mt_stream_source_in_array2d is t_mt_stream_sink_out_array2d;
subtype t_mt_stream_source_out_array2d is t_mt_stream_sink_in_array2d;
type t_mt_stream_config_in_array2d is
array(t_maxcpu_range) of t_mt_stream_config_in_array(t_maxslot_range);
type t_mt_stream_config_out_array2d is
array(t_maxcpu_range) of t_mt_stream_config_out_array(t_maxslot_range);
-- defined in mt_mqueue_pkg
type t_mt_stream_sink_in_array is array(integer range<>) of t_mt_stream_sink_in;
type t_mt_stream_sink_out_array is array(integer range<>) of t_mt_stream_sink_out;
......@@ -334,16 +370,21 @@ VHDL records, defined in **mock_turtle_pkg** (for the first array dimension) and
pkt_ready : std_logic;
end record t_mt_stream_sink_out;
type t_mt_stream_config_out is record
adr : std_logic_vector(10 downto 0);
dat : std_logic_vector(31 downto 0);
we : std_logic;
end record t_mt_stream_config_out;
type t_mt_stream_config_in is record
dat : std_logic_vector(31 downto 0);
end record t_mt_stream_config_in;
subtype t_mt_stream_source_in is t_mt_stream_sink_out;
subtype t_mt_stream_source_out is t_mt_stream_sink_in;
constant c_MT_DUMMY_SOURCE_IN : t_mt_stream_sink_out :=
('0', '0');
constant c_MT_DUMMY_SINK_IN : t_mt_stream_sink_in :=
(x"00000000", '0', '0', '0', '0');
.. todo::
Describe how the RMQ interface works and update after Tom's endpoint work if necessary.
For an example of an end-point, please have a look at the provided Ethernet end-point, available
under *hdl/rtl/endpoint/mt_ep_ethernet_single.vhd*.
clk_ref_i
When `White Rabbit Support`_ is enabled (via the **g_WITH_WHITE_RABBIT** generic), the White
......@@ -448,8 +489,8 @@ the signals, store them for future reference, display them as waveforms, etc.
mock_turtle_core
----------------
The mock_turtle_core uses the top-level module of the MT as the Device Under Test (DUT). It loads
and executes a dedicated simulation verification program on the first CPU.
The mock_turtle_core testbench uses the top-level module of the MT as the Device Under Test
(DUT). It loads and executes a dedicated simulation verification program on the first CPU.
This program tests the following subsystems of the MT:
......@@ -467,11 +508,45 @@ The expected output from the simulation is::
UART MSG from core 0: #3 hmq
UART MSG from core 0: #4 rmq
UART MSG from core 0: Done
Simulation PASSED
.. note::
The mock_turtle_core testbench expects an already compiled software binary under
*tests/firmware/sim-verif*. Please compile the software prior to running the simulation.
mt_eth_ep
---------
The mt_eth_ep testbench uses the top-level module of the MT as the Device Under Test (DUT) and it
attaches an *mt_ep_ethernet_single* end-point to it. It loads and executes a dedicated simulation
verification program on the first CPU.
This program tests in particular the remote message queues and the mechanism to configure and control
end-points.
The expected output from the simulation is::
App ID: 0x115790de
Core count: 2
UART MSG from core 0: RMQ UDP EP test
802.1 DST [ff:ff:ff:ff:ff:ff] SRC: [00:00:00:00:00:00] Type = 0x0800 size = 50 F:( )
+000: 45 00 00 24 00 00 40 00-3c 11 83 ca c0 a8 5a 11
+010: c0 a8 5a ff 1e 61 30 39-00 10 00 00 de ad be ef
+020: 00 00 01 23
UART MSG from core 0: Recv id=21524110, val=fffffedc
UART MSG from core 0: rx(1): fffffedc
802.1 DST [ff:ff:ff:ff:ff:ff] SRC: [00:00:00:00:00:00] Type = 0x0800 size = 50 F:( )
+000: 45 00 00 24 00 00 40 00-3c 11 83 ca c0 a8 5a 11
+010: c0 a8 5a ff 1e 61 30 39-00 10 00 00 de ad be ef
+020: ff ff fe dc
UART MSG from core 0: Recv id=21524110, val=123
UART MSG from core 0: rx(2): 123
Simulation PASSED
.. note::
The mt_eth_ep testbench expects an already compiled software binary under
*tests/firmware/rmq-udp-send*. Please compile the software prior to running the simulation.
.. _OHWR general-cores: https://www.ohwr.org/project/general-cores/wiki
.. _White Rabbit PTP Core: https://www.ohwr.org/project/wr-cores/wiki/Wrpc_core/wiki
.. _Hdlmake: https://www.ohwr.org/project/hdl-make/wiki
......
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